From 2e6a838fa09d0ad1ac2b315ecd2ef6142a13bd92 Mon Sep 17 00:00:00 2001
From: Andrew Zoghby <azoghby@rivosinc.com>
Date: Fri, 9 Dec 2022 10:26:12 -0800
Subject: [PATCH] registers: add mseccfg

This register is included with the Smepmp extension.
---
 src/register/mod.rs     |  3 +++
 src/register/mseccfg.rs | 49 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 src/register/mseccfg.rs

diff --git a/src/register/mod.rs b/src/register/mod.rs
index 3e0b0f2d..d9acf293 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -103,6 +103,9 @@ pub use self::pmpcfgx::*;
 mod pmpaddrx;
 pub use self::pmpaddrx::*;
 
+// epmp configuration register
+pub mod mseccfg;
+
 // Machine Counter/Timers
 pub mod mcycle;
 pub mod mcycleh;
diff --git a/src/register/mseccfg.rs b/src/register/mseccfg.rs
new file mode 100644
index 00000000..311b81b9
--- /dev/null
+++ b/src/register/mseccfg.rs
@@ -0,0 +1,49 @@
+//! mseccfg register
+
+use bit_field::BitField;
+
+/// mseccfg register
+#[derive(Clone, Copy, Debug)]
+pub struct Mseccfg {
+    bits: usize,
+}
+
+impl Mseccfg {
+    /// Returns the contents of the register as raw bits
+    #[inline]
+    pub fn bits(&self) -> usize {
+        self.bits
+    }
+
+    /// Rule Locking Bypass
+    #[inline]
+    pub fn rlb(&self) -> bool {
+        self.bits.get_bit(2)
+    }
+
+    /// Machine Mode Whitelist Policy
+    #[inline]
+    pub fn mmwp(&self) -> bool {
+        self.bits.get_bit(1)
+    }
+
+    /// Machine Mode Lockdown
+    #[inline]
+    pub fn mml(&self) -> bool {
+        self.bits.get_bit(0)
+    }
+}
+
+read_csr_as!(Mseccfg, 0x747);
+set!(0x747);
+clear!(0x747);
+
+set_clear_csr!(
+    /// Rule Locking Bypass 
+    , set_rlb, clear_rlb, 1 << 2);
+set_clear_csr!(
+    /// Machine Mode Whitelist Policy 
+    , set_mmwp, clear_mmwp, 1 << 1);
+set_clear_csr!(
+    /// Machine Mode Lockdown 
+    , set_mml, clear_mml, 1 << 0);