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romancardenasAfoHT
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Add mecall backend
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-22
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5 files changed

+32
-22
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examples/hifive1/Cargo.lock

+23-11
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examples/hifive1/Cargo.toml

+2-2
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,11 @@ edition = "2021"
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[dependencies]
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rtic = { path = "../../rtic" }
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heapless = { version = "0.8.0", features = ["portable-atomic-unsafe-assume-single-core"] }
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hifive1 = { git = "https://github.com/riscv-rust/e310x.git", branch = "ehv1", features = ["board-redv"] }
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hifive1 = { version = "0.13.0", features = ["board-redv"] }
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riscv-rt = {version = "0.13.0", features = ["single-hart"]}
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riscv = "0.12.1"
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semihosting = { version = "0.1", features = ["stdio", "panic-handler"] }
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portable-atomic = { version = "1.9", features = ["unsafe-assume-single-core", "force-amo"] }
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portable-atomic = { version = "1", features = ["unsafe-assume-single-core", "force-amo"] }
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[features]
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riscv-clint-backend = ["rtic/riscv-clint-backend"]

rtic-macros/src/codegen/bindings/riscv_slic.rs

+1-6
Original file line numberDiff line numberDiff line change
@@ -108,10 +108,6 @@ pub fn pre_init_checks(app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream
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pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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// First, we reset and disable all the interrupt controllers
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stmts.push(quote!(rtic::export::clear_interrupts();));
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// Then, we set the corresponding priorities
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let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
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for (&p, name) in interrupt_ids.chain(
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app.hardware_tasks
@@ -122,8 +118,7 @@ pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<
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rtic::export::set_priority(slic::SoftwareInterrupt::#name, #p);
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));
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}
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// Finally, we activate the interrupts
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stmts.push(quote!(rtic::export::set_interrupts();));
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stmts
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}
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rtic/CHANGELOG.md

+3
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@@ -23,6 +23,9 @@ Example:
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### Changed
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- Updated esp32c3 dependency to v0.27.0
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### Added
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- Support for RISC-V targets compatible with `riscv-slic` using machine-level environment call exceptions.
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## [v2.1.2] - 2024-12-06
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rtic/src/export/slic.rs

+3-3
Original file line numberDiff line numberDiff line change
@@ -7,16 +7,16 @@ pub use riscv_slic::{lock, pend, run, InterruptNumber};
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compile_error!("Building for the riscv-slic, but no compatible backend selected");
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/// USE CASE RE-EXPORTS: needed for SLIC-only
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pub use riscv_slic::{self, clear_interrupts, codegen, set_interrupts, set_priority};
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pub use riscv_slic::{self, codegen, set_priority};
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pub mod interrupt {
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#[inline]
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pub fn disable() {
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riscv_slic::disable();
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riscv_slic::clear_interrupts();
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}
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#[inline]
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pub unsafe fn enable() {
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riscv_slic::set_interrupts();
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riscv_slic::enable();
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}
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}

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