diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index cedc0c458b..027dcfc874 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -1,9 +1,9 @@ // This code is automatically generated. DO NOT MODIFY. // -// Instead, modify `crates/stdarch-gen2/spec/` and run the following command to re-generate this file: +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: // // ``` -// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec // ``` #![allow(improper_ctypes)] @@ -27,7 +27,6 @@ pub unsafe fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8 let f: uint8x8_t = simd_cast(f); simd_add(a, simd_cast(f)) } - #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"] #[doc = "## Safety"] @@ -43,7 +42,6 @@ pub unsafe fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x let f: uint16x4_t = simd_cast(f); simd_add(a, simd_cast(f)) } - #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"] #[doc = "## Safety"] @@ -59,7 +57,6 @@ pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x let f: uint32x2_t = simd_cast(f); simd_add(a, simd_cast(f)) } - #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"] #[doc = "## Safety"] @@ -74,7 +71,6 @@ pub unsafe fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint let f: uint8x8_t = vabd_u8(d, e); simd_add(a, simd_cast(f)) } - #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"] #[doc = "## Safety"] @@ -89,7 +85,6 @@ pub unsafe fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uin let f: uint16x4_t = vabd_u16(d, e); simd_add(a, simd_cast(f)) } - #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"] #[doc = "## Safety"] @@ -104,7 +99,6 @@ pub unsafe fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uin let f: uint32x2_t = vabd_u32(d, e); simd_add(a, simd_cast(f)) } - #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"] #[doc = "## Safety"] @@ -123,7 +117,6 @@ pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vabd_f64(a, b) } - #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"] #[doc = "## Safety"] @@ -142,7 +135,6 @@ pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vabdq_f64(a, b) } - #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"] #[doc = "## Safety"] @@ -154,7 +146,6 @@ pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vabdd_f64(a: f64, b: f64) -> f64 { simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } - #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"] #[doc = "## Safety"] @@ -166,7 +157,6 @@ pub unsafe fn vabdd_f64(a: f64, b: f64) -> f64 { pub unsafe fn vabds_f32(a: f32, b: f32) -> f32 { simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } - #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] #[doc = "## Safety"] @@ -181,7 +171,6 @@ pub unsafe fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { let e: uint16x4_t = simd_cast(vabd_s16(c, d)); simd_cast(e) } - #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] #[doc = "## Safety"] @@ -196,7 +185,6 @@ pub unsafe fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { let e: uint32x2_t = simd_cast(vabd_s32(c, d)); simd_cast(e) } - #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] #[doc = "## Safety"] @@ -211,7 +199,6 @@ pub unsafe fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { let e: uint8x8_t = simd_cast(vabd_s8(c, d)); simd_cast(e) } - #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"] #[doc = "## Safety"] @@ -225,7 +212,6 @@ pub unsafe fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); simd_cast(vabd_u8(c, d)) } - #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"] #[doc = "## Safety"] @@ -239,7 +225,6 @@ pub unsafe fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); simd_cast(vabd_u16(c, d)) } - #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"] #[doc = "## Safety"] @@ -253,7 +238,6 @@ pub unsafe fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); simd_cast(vabd_u32(c, d)) } - #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"] #[doc = "## Safety"] @@ -265,7 +249,6 @@ pub unsafe fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { simd_fabs(a) } - #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"] #[doc = "## Safety"] @@ -277,7 +260,6 @@ pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { simd_fabs(a) } - #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"] #[doc = "## Safety"] @@ -289,7 +271,6 @@ pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { a.wrapping_add(b) } - #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"] #[doc = "## Safety"] @@ -301,7 +282,6 @@ pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 { a.wrapping_add(b) } - #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"] #[doc = "## Safety"] @@ -320,7 +300,6 @@ pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { } _vaddlv_s16(a) } - #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"] #[doc = "## Safety"] @@ -339,7 +318,6 @@ pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { } _vaddlvq_s16(a) } - #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"] #[doc = "## Safety"] @@ -358,7 +336,6 @@ pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { } _vaddlvq_s32(a) } - #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"] #[doc = "## Safety"] @@ -377,7 +354,6 @@ pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { } _vaddlv_s32(a) } - #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"] #[doc = "## Safety"] @@ -396,7 +372,6 @@ pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { } _vaddlv_u16(a.as_signed()).as_unsigned() } - #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"] #[doc = "## Safety"] @@ -415,7 +390,6 @@ pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { } _vaddlvq_u16(a.as_signed()).as_unsigned() } - #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"] #[doc = "## Safety"] @@ -434,7 +408,6 @@ pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { } _vaddlvq_u32(a.as_signed()).as_unsigned() } - #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"] #[doc = "## Safety"] @@ -453,7 +426,6 @@ pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { } _vaddlv_u32(a.as_signed()).as_unsigned() } - #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"] #[doc = "## Safety"] @@ -472,7 +444,6 @@ pub unsafe fn vaddv_f32(a: float32x2_t) -> f32 { } _vaddv_f32(a) } - #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"] #[doc = "## Safety"] @@ -491,7 +462,6 @@ pub unsafe fn vaddvq_f32(a: float32x4_t) -> f32 { } _vaddvq_f32(a) } - #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"] #[doc = "## Safety"] @@ -510,7 +480,6 @@ pub unsafe fn vaddvq_f64(a: float64x2_t) -> f64 { } _vaddvq_f64(a) } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"] #[doc = "## Safety"] @@ -529,7 +498,6 @@ pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } _vbcaxq_s8(a, b, c) } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"] #[doc = "## Safety"] @@ -548,7 +516,6 @@ pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t } _vbcaxq_s16(a, b, c) } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"] #[doc = "## Safety"] @@ -567,7 +534,6 @@ pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t } _vbcaxq_s32(a, b, c) } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"] #[doc = "## Safety"] @@ -586,7 +552,6 @@ pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t } _vbcaxq_s64(a, b, c) } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"] #[doc = "## Safety"] @@ -605,7 +570,6 @@ pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16 } _vbcaxq_u8(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"] #[doc = "## Safety"] @@ -624,7 +588,6 @@ pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x } _vbcaxq_u16(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"] #[doc = "## Safety"] @@ -643,7 +606,6 @@ pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x } _vbcaxq_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"] #[doc = "## Safety"] @@ -662,7 +624,6 @@ pub unsafe fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x } _vbcaxq_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] #[doc = "## Safety"] @@ -681,7 +642,6 @@ pub unsafe fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vcadd_rot270_f32(a, b) } - #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] #[doc = "## Safety"] @@ -700,7 +660,6 @@ pub unsafe fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vcaddq_rot270_f32(a, b) } - #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] #[doc = "## Safety"] @@ -719,7 +678,6 @@ pub unsafe fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vcaddq_rot270_f64(a, b) } - #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] #[doc = "## Safety"] @@ -738,7 +696,6 @@ pub unsafe fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vcadd_rot90_f32(a, b) } - #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] #[doc = "## Safety"] @@ -757,7 +714,6 @@ pub unsafe fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vcaddq_rot90_f32(a, b) } - #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] #[doc = "## Safety"] @@ -776,7 +732,6 @@ pub unsafe fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vcaddq_rot90_f64(a, b) } - #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"] #[doc = "## Safety"] @@ -795,7 +750,6 @@ pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } _vcage_f64(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"] #[doc = "## Safety"] @@ -814,7 +768,6 @@ pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } _vcageq_f64(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"] #[doc = "## Safety"] @@ -833,7 +786,6 @@ pub unsafe fn vcaged_f64(a: f64, b: f64) -> u64 { } _vcaged_f64(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"] #[doc = "## Safety"] @@ -852,7 +804,6 @@ pub unsafe fn vcages_f32(a: f32, b: f32) -> u32 { } _vcages_f32(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"] #[doc = "## Safety"] @@ -871,7 +822,6 @@ pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } _vcagt_f64(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"] #[doc = "## Safety"] @@ -890,7 +840,6 @@ pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } _vcagtq_f64(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"] #[doc = "## Safety"] @@ -909,7 +858,6 @@ pub unsafe fn vcagtd_f64(a: f64, b: f64) -> u64 { } _vcagtd_f64(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"] #[doc = "## Safety"] @@ -928,7 +876,6 @@ pub unsafe fn vcagts_f32(a: f32, b: f32) -> u32 { } _vcagts_f32(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"] #[doc = "## Safety"] @@ -940,7 +887,6 @@ pub unsafe fn vcagts_f32(a: f32, b: f32) -> u32 { pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { vcage_f64(b, a) } - #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"] #[doc = "## Safety"] @@ -952,7 +898,6 @@ pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { vcageq_f64(b, a) } - #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"] #[doc = "## Safety"] @@ -964,7 +909,6 @@ pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vcaled_f64(a: f64, b: f64) -> u64 { vcaged_f64(b, a) } - #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"] #[doc = "## Safety"] @@ -976,7 +920,6 @@ pub unsafe fn vcaled_f64(a: f64, b: f64) -> u64 { pub unsafe fn vcales_f32(a: f32, b: f32) -> u32 { vcages_f32(b, a) } - #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"] #[doc = "## Safety"] @@ -988,7 +931,6 @@ pub unsafe fn vcales_f32(a: f32, b: f32) -> u32 { pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { vcagt_f64(b, a) } - #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"] #[doc = "## Safety"] @@ -1000,7 +942,6 @@ pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { vcagtq_f64(b, a) } - #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"] #[doc = "## Safety"] @@ -1012,7 +953,6 @@ pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vcaltd_f64(a: f64, b: f64) -> u64 { vcagtd_f64(b, a) } - #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"] #[doc = "## Safety"] @@ -1024,7 +964,6 @@ pub unsafe fn vcaltd_f64(a: f64, b: f64) -> u64 { pub unsafe fn vcalts_f32(a: f32, b: f32) -> u32 { vcagts_f32(b, a) } - #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"] #[doc = "## Safety"] @@ -1036,7 +975,6 @@ pub unsafe fn vcalts_f32(a: f32, b: f32) -> u32 { pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { simd_eq(a, b) } - #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"] #[doc = "## Safety"] @@ -1048,7 +986,6 @@ pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"] #[doc = "## Safety"] @@ -1060,7 +997,6 @@ pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"] #[doc = "## Safety"] @@ -1072,7 +1008,6 @@ pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"] #[doc = "## Safety"] @@ -1084,7 +1019,6 @@ pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"] #[doc = "## Safety"] @@ -1096,7 +1030,6 @@ pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"] #[doc = "## Safety"] @@ -1108,7 +1041,6 @@ pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"] #[doc = "## Safety"] @@ -1120,7 +1052,6 @@ pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { simd_eq(a, b) } - #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"] #[doc = "## Safety"] @@ -1132,7 +1063,6 @@ pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { pub unsafe fn vceqd_f64(a: f64, b: f64) -> u64 { simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } - #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"] #[doc = "## Safety"] @@ -1144,7 +1074,6 @@ pub unsafe fn vceqd_f64(a: f64, b: f64) -> u64 { pub unsafe fn vceqs_f32(a: f32, b: f32) -> u32 { simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } - #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"] #[doc = "## Safety"] @@ -1156,7 +1085,6 @@ pub unsafe fn vceqs_f32(a: f32, b: f32) -> u32 { pub unsafe fn vceqd_s64(a: i64, b: i64) -> u64 { transmute(vceq_s64(transmute(a), transmute(b))) } - #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"] #[doc = "## Safety"] @@ -1168,7 +1096,6 @@ pub unsafe fn vceqd_s64(a: i64, b: i64) -> u64 { pub unsafe fn vceqd_u64(a: u64, b: u64) -> u64 { transmute(vceq_u64(transmute(a), transmute(b))) } - #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"] #[doc = "## Safety"] @@ -1181,7 +1108,6 @@ pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); simd_eq(a, transmute(b)) } - #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"] #[doc = "## Safety"] @@ -1194,7 +1120,6 @@ pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); simd_eq(a, transmute(b)) } - #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"] #[doc = "## Safety"] @@ -1207,7 +1132,6 @@ pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; simd_eq(a, transmute(b)) } - #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"] #[doc = "## Safety"] @@ -1220,7 +1144,6 @@ pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"] #[doc = "## Safety"] @@ -1233,7 +1156,6 @@ pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"] #[doc = "## Safety"] @@ -1246,7 +1168,6 @@ pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"] #[doc = "## Safety"] @@ -1259,7 +1180,6 @@ pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"] #[doc = "## Safety"] @@ -1272,7 +1192,6 @@ pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"] #[doc = "## Safety"] @@ -1285,7 +1204,6 @@ pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"] #[doc = "## Safety"] @@ -1298,7 +1216,6 @@ pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"] #[doc = "## Safety"] @@ -1311,7 +1228,6 @@ pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"] #[doc = "## Safety"] @@ -1324,7 +1240,6 @@ pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"] #[doc = "## Safety"] @@ -1337,7 +1252,6 @@ pub unsafe fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"] #[doc = "## Safety"] @@ -1350,7 +1264,6 @@ pub unsafe fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"] #[doc = "## Safety"] @@ -1363,7 +1276,6 @@ pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); simd_eq(a, transmute(b)) } - #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"] #[doc = "## Safety"] @@ -1376,7 +1288,6 @@ pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"] #[doc = "## Safety"] @@ -1389,7 +1300,6 @@ pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"] #[doc = "## Safety"] @@ -1402,7 +1312,6 @@ pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"] #[doc = "## Safety"] @@ -1415,7 +1324,6 @@ pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { let b: u16x4 = u16x4::new(0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"] #[doc = "## Safety"] @@ -1428,7 +1336,6 @@ pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"] #[doc = "## Safety"] @@ -1441,7 +1348,6 @@ pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { let b: u32x2 = u32x2::new(0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"] #[doc = "## Safety"] @@ -1454,7 +1360,6 @@ pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { let b: u32x4 = u32x4::new(0, 0, 0, 0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"] #[doc = "## Safety"] @@ -1467,7 +1372,6 @@ pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { let b: u64x1 = u64x1::new(0); simd_eq(a, transmute(b)) } - #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"] #[doc = "## Safety"] @@ -1480,7 +1384,6 @@ pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { let b: u64x2 = u64x2::new(0, 0); simd_eq(a, transmute(b)) } - #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"] #[doc = "## Safety"] @@ -1492,7 +1395,6 @@ pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { pub unsafe fn vceqzd_s64(a: i64) -> u64 { transmute(vceqz_s64(transmute(a))) } - #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"] #[doc = "## Safety"] @@ -1504,7 +1406,6 @@ pub unsafe fn vceqzd_s64(a: i64) -> u64 { pub unsafe fn vceqzd_u64(a: u64) -> u64 { transmute(vceqz_u64(transmute(a))) } - #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"] #[doc = "## Safety"] @@ -1516,7 +1417,6 @@ pub unsafe fn vceqzd_u64(a: u64) -> u64 { pub unsafe fn vceqzs_f32(a: f32) -> u32 { simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) } - #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"] #[doc = "## Safety"] @@ -1528,7 +1428,6 @@ pub unsafe fn vceqzs_f32(a: f32) -> u32 { pub unsafe fn vceqzd_f64(a: f64) -> u64 { simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) } - #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"] #[doc = "## Safety"] @@ -1540,7 +1439,6 @@ pub unsafe fn vceqzd_f64(a: f64) -> u64 { pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { simd_ge(a, b) } - #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"] #[doc = "## Safety"] @@ -1552,7 +1450,6 @@ pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"] #[doc = "## Safety"] @@ -1564,7 +1461,6 @@ pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"] #[doc = "## Safety"] @@ -1576,7 +1472,6 @@ pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"] #[doc = "## Safety"] @@ -1588,7 +1483,6 @@ pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"] #[doc = "## Safety"] @@ -1600,7 +1494,6 @@ pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_ge(a, b) } - #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"] #[doc = "## Safety"] @@ -1612,7 +1505,6 @@ pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vcged_f64(a: f64, b: f64) -> u64 { simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } - #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"] #[doc = "## Safety"] @@ -1624,7 +1516,6 @@ pub unsafe fn vcged_f64(a: f64, b: f64) -> u64 { pub unsafe fn vcges_f32(a: f32, b: f32) -> u32 { simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } - #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"] #[doc = "## Safety"] @@ -1636,7 +1527,6 @@ pub unsafe fn vcges_f32(a: f32, b: f32) -> u32 { pub unsafe fn vcged_s64(a: i64, b: i64) -> u64 { transmute(vcge_s64(transmute(a), transmute(b))) } - #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"] #[doc = "## Safety"] @@ -1648,7 +1538,6 @@ pub unsafe fn vcged_s64(a: i64, b: i64) -> u64 { pub unsafe fn vcged_u64(a: u64, b: u64) -> u64 { transmute(vcge_u64(transmute(a), transmute(b))) } - #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"] #[doc = "## Safety"] @@ -1661,7 +1550,6 @@ pub unsafe fn vcgez_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); simd_ge(a, transmute(b)) } - #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"] #[doc = "## Safety"] @@ -1674,7 +1562,6 @@ pub unsafe fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); simd_ge(a, transmute(b)) } - #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"] #[doc = "## Safety"] @@ -1687,7 +1574,6 @@ pub unsafe fn vcgez_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; simd_ge(a, transmute(b)) } - #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"] #[doc = "## Safety"] @@ -1700,7 +1586,6 @@ pub unsafe fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"] #[doc = "## Safety"] @@ -1713,7 +1598,6 @@ pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"] #[doc = "## Safety"] @@ -1726,7 +1610,6 @@ pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"] #[doc = "## Safety"] @@ -1739,7 +1622,6 @@ pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"] #[doc = "## Safety"] @@ -1752,7 +1634,6 @@ pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"] #[doc = "## Safety"] @@ -1765,7 +1646,6 @@ pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"] #[doc = "## Safety"] @@ -1778,7 +1658,6 @@ pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"] #[doc = "## Safety"] @@ -1791,7 +1670,6 @@ pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); simd_ge(a, transmute(b)) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"] #[doc = "## Safety"] @@ -1804,7 +1682,6 @@ pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); simd_ge(a, transmute(b)) } - #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"] #[doc = "## Safety"] @@ -1816,7 +1693,6 @@ pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { pub unsafe fn vcgezd_f64(a: f64) -> u64 { simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) } - #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"] #[doc = "## Safety"] @@ -1828,7 +1704,6 @@ pub unsafe fn vcgezd_f64(a: f64) -> u64 { pub unsafe fn vcgezs_f32(a: f32) -> u32 { simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) } - #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"] #[doc = "## Safety"] @@ -1840,7 +1715,6 @@ pub unsafe fn vcgezs_f32(a: f32) -> u32 { pub unsafe fn vcgezd_s64(a: i64) -> u64 { transmute(vcgez_s64(transmute(a))) } - #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"] #[doc = "## Safety"] @@ -1852,7 +1726,6 @@ pub unsafe fn vcgezd_s64(a: i64) -> u64 { pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { simd_gt(a, b) } - #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"] #[doc = "## Safety"] @@ -1864,7 +1737,6 @@ pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"] #[doc = "## Safety"] @@ -1876,7 +1748,6 @@ pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"] #[doc = "## Safety"] @@ -1888,7 +1759,6 @@ pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"] #[doc = "## Safety"] @@ -1900,7 +1770,6 @@ pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"] #[doc = "## Safety"] @@ -1912,7 +1781,6 @@ pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_gt(a, b) } - #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"] #[doc = "## Safety"] @@ -1924,7 +1792,6 @@ pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vcgtd_f64(a: f64, b: f64) -> u64 { simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } - #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"] #[doc = "## Safety"] @@ -1936,7 +1803,6 @@ pub unsafe fn vcgtd_f64(a: f64, b: f64) -> u64 { pub unsafe fn vcgts_f32(a: f32, b: f32) -> u32 { simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } - #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"] #[doc = "## Safety"] @@ -1948,7 +1814,6 @@ pub unsafe fn vcgts_f32(a: f32, b: f32) -> u32 { pub unsafe fn vcgtd_s64(a: i64, b: i64) -> u64 { transmute(vcgt_s64(transmute(a), transmute(b))) } - #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"] #[doc = "## Safety"] @@ -1960,7 +1825,6 @@ pub unsafe fn vcgtd_s64(a: i64, b: i64) -> u64 { pub unsafe fn vcgtd_u64(a: u64, b: u64) -> u64 { transmute(vcgt_u64(transmute(a), transmute(b))) } - #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"] #[doc = "## Safety"] @@ -1973,7 +1837,6 @@ pub unsafe fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); simd_gt(a, transmute(b)) } - #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"] #[doc = "## Safety"] @@ -1986,7 +1849,6 @@ pub unsafe fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); simd_gt(a, transmute(b)) } - #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"] #[doc = "## Safety"] @@ -1999,7 +1861,6 @@ pub unsafe fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; simd_gt(a, transmute(b)) } - #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"] #[doc = "## Safety"] @@ -2012,7 +1873,6 @@ pub unsafe fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"] #[doc = "## Safety"] @@ -2025,7 +1885,6 @@ pub unsafe fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"] #[doc = "## Safety"] @@ -2038,7 +1897,6 @@ pub unsafe fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"] #[doc = "## Safety"] @@ -2051,7 +1909,6 @@ pub unsafe fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"] #[doc = "## Safety"] @@ -2064,7 +1921,6 @@ pub unsafe fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"] #[doc = "## Safety"] @@ -2077,7 +1933,6 @@ pub unsafe fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"] #[doc = "## Safety"] @@ -2090,7 +1945,6 @@ pub unsafe fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"] #[doc = "## Safety"] @@ -2103,7 +1957,6 @@ pub unsafe fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); simd_gt(a, transmute(b)) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"] #[doc = "## Safety"] @@ -2116,7 +1969,6 @@ pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); simd_gt(a, transmute(b)) } - #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"] #[doc = "## Safety"] @@ -2128,7 +1980,6 @@ pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { pub unsafe fn vcgtzd_f64(a: f64) -> u64 { simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) } - #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"] #[doc = "## Safety"] @@ -2140,7 +1991,6 @@ pub unsafe fn vcgtzd_f64(a: f64) -> u64 { pub unsafe fn vcgtzs_f32(a: f32) -> u32 { simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) } - #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"] #[doc = "## Safety"] @@ -2152,7 +2002,6 @@ pub unsafe fn vcgtzs_f32(a: f32) -> u32 { pub unsafe fn vcgtzd_s64(a: i64) -> u64 { transmute(vcgtz_s64(transmute(a))) } - #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"] #[doc = "## Safety"] @@ -2164,7 +2013,6 @@ pub unsafe fn vcgtzd_s64(a: i64) -> u64 { pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { simd_le(a, b) } - #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"] #[doc = "## Safety"] @@ -2176,7 +2024,6 @@ pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"] #[doc = "## Safety"] @@ -2188,7 +2035,6 @@ pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"] #[doc = "## Safety"] @@ -2200,7 +2046,6 @@ pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"] #[doc = "## Safety"] @@ -2212,7 +2057,6 @@ pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"] #[doc = "## Safety"] @@ -2224,7 +2068,6 @@ pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_le(a, b) } - #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"] #[doc = "## Safety"] @@ -2236,7 +2079,6 @@ pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vcled_f64(a: f64, b: f64) -> u64 { simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } - #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"] #[doc = "## Safety"] @@ -2248,7 +2090,6 @@ pub unsafe fn vcled_f64(a: f64, b: f64) -> u64 { pub unsafe fn vcles_f32(a: f32, b: f32) -> u32 { simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } - #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"] #[doc = "## Safety"] @@ -2260,7 +2101,6 @@ pub unsafe fn vcles_f32(a: f32, b: f32) -> u32 { pub unsafe fn vcled_u64(a: u64, b: u64) -> u64 { transmute(vcle_u64(transmute(a), transmute(b))) } - #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"] #[doc = "## Safety"] @@ -2272,7 +2112,6 @@ pub unsafe fn vcled_u64(a: u64, b: u64) -> u64 { pub unsafe fn vcled_s64(a: i64, b: i64) -> u64 { transmute(vcle_s64(transmute(a), transmute(b))) } - #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"] #[doc = "## Safety"] @@ -2285,7 +2124,6 @@ pub unsafe fn vclez_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); simd_le(a, transmute(b)) } - #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"] #[doc = "## Safety"] @@ -2298,7 +2136,6 @@ pub unsafe fn vclezq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); simd_le(a, transmute(b)) } - #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"] #[doc = "## Safety"] @@ -2311,7 +2148,6 @@ pub unsafe fn vclez_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; simd_le(a, transmute(b)) } - #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"] #[doc = "## Safety"] @@ -2324,7 +2160,6 @@ pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"] #[doc = "## Safety"] @@ -2337,7 +2172,6 @@ pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"] #[doc = "## Safety"] @@ -2350,7 +2184,6 @@ pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"] #[doc = "## Safety"] @@ -2363,7 +2196,6 @@ pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"] #[doc = "## Safety"] @@ -2376,7 +2208,6 @@ pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"] #[doc = "## Safety"] @@ -2389,7 +2220,6 @@ pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"] #[doc = "## Safety"] @@ -2402,7 +2232,6 @@ pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"] #[doc = "## Safety"] @@ -2415,7 +2244,6 @@ pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); simd_le(a, transmute(b)) } - #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"] #[doc = "## Safety"] @@ -2428,7 +2256,6 @@ pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); simd_le(a, transmute(b)) } - #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"] #[doc = "## Safety"] @@ -2440,7 +2267,6 @@ pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { pub unsafe fn vclezd_f64(a: f64) -> u64 { simd_extract!(vclez_f64(vdup_n_f64(a)), 0) } - #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"] #[doc = "## Safety"] @@ -2452,7 +2278,6 @@ pub unsafe fn vclezd_f64(a: f64) -> u64 { pub unsafe fn vclezs_f32(a: f32) -> u32 { simd_extract!(vclez_f32(vdup_n_f32(a)), 0) } - #[doc = "Compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"] #[doc = "## Safety"] @@ -2464,7 +2289,6 @@ pub unsafe fn vclezs_f32(a: f32) -> u32 { pub unsafe fn vclezd_s64(a: i64) -> u64 { transmute(vclez_s64(transmute(a))) } - #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"] #[doc = "## Safety"] @@ -2476,7 +2300,6 @@ pub unsafe fn vclezd_s64(a: i64) -> u64 { pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { simd_lt(a, b) } - #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"] #[doc = "## Safety"] @@ -2488,7 +2311,6 @@ pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"] #[doc = "## Safety"] @@ -2500,7 +2322,6 @@ pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"] #[doc = "## Safety"] @@ -2512,7 +2333,6 @@ pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"] #[doc = "## Safety"] @@ -2524,7 +2344,6 @@ pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"] #[doc = "## Safety"] @@ -2536,7 +2355,6 @@ pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_lt(a, b) } - #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"] #[doc = "## Safety"] @@ -2548,7 +2366,6 @@ pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vcltd_u64(a: u64, b: u64) -> u64 { transmute(vclt_u64(transmute(a), transmute(b))) } - #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"] #[doc = "## Safety"] @@ -2560,7 +2377,6 @@ pub unsafe fn vcltd_u64(a: u64, b: u64) -> u64 { pub unsafe fn vcltd_s64(a: i64, b: i64) -> u64 { transmute(vclt_s64(transmute(a), transmute(b))) } - #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"] #[doc = "## Safety"] @@ -2572,7 +2388,6 @@ pub unsafe fn vcltd_s64(a: i64, b: i64) -> u64 { pub unsafe fn vclts_f32(a: f32, b: f32) -> u32 { simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } - #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"] #[doc = "## Safety"] @@ -2584,7 +2399,6 @@ pub unsafe fn vclts_f32(a: f32, b: f32) -> u32 { pub unsafe fn vcltd_f64(a: f64, b: f64) -> u64 { simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } - #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"] #[doc = "## Safety"] @@ -2597,7 +2411,6 @@ pub unsafe fn vcltz_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); simd_lt(a, transmute(b)) } - #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"] #[doc = "## Safety"] @@ -2610,7 +2423,6 @@ pub unsafe fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); simd_lt(a, transmute(b)) } - #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"] #[doc = "## Safety"] @@ -2623,7 +2435,6 @@ pub unsafe fn vcltz_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; simd_lt(a, transmute(b)) } - #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"] #[doc = "## Safety"] @@ -2636,7 +2447,6 @@ pub unsafe fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"] #[doc = "## Safety"] @@ -2649,7 +2459,6 @@ pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"] #[doc = "## Safety"] @@ -2662,7 +2471,6 @@ pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"] #[doc = "## Safety"] @@ -2675,7 +2483,6 @@ pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"] #[doc = "## Safety"] @@ -2688,7 +2495,6 @@ pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"] #[doc = "## Safety"] @@ -2701,7 +2507,6 @@ pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"] #[doc = "## Safety"] @@ -2714,7 +2519,6 @@ pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"] #[doc = "## Safety"] @@ -2727,7 +2531,6 @@ pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); simd_lt(a, transmute(b)) } - #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"] #[doc = "## Safety"] @@ -2740,7 +2543,6 @@ pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); simd_lt(a, transmute(b)) } - #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"] #[doc = "## Safety"] @@ -2752,7 +2554,6 @@ pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { pub unsafe fn vcltzd_f64(a: f64) -> u64 { simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) } - #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"] #[doc = "## Safety"] @@ -2764,7 +2565,6 @@ pub unsafe fn vcltzd_f64(a: f64) -> u64 { pub unsafe fn vcltzs_f32(a: f32) -> u32 { simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) } - #[doc = "Compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"] #[doc = "## Safety"] @@ -2776,7 +2576,6 @@ pub unsafe fn vcltzs_f32(a: f32) -> u32 { pub unsafe fn vcltzd_s64(a: i64) -> u64 { transmute(vcltz_s64(transmute(a))) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] #[doc = "## Safety"] @@ -2795,7 +2594,6 @@ pub unsafe fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float } _vcmla_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] #[doc = "## Safety"] @@ -2814,7 +2612,6 @@ pub unsafe fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa } _vcmlaq_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] #[doc = "## Safety"] @@ -2833,7 +2630,6 @@ pub unsafe fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa } _vcmlaq_f64(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"] #[doc = "## Safety"] @@ -2852,7 +2648,6 @@ pub unsafe fn vcmla_lane_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"] #[doc = "## Safety"] @@ -2880,7 +2675,6 @@ pub unsafe fn vcmlaq_lane_f32( ); vcmlaq_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"] #[doc = "## Safety"] @@ -2899,7 +2693,6 @@ pub unsafe fn vcmla_laneq_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"] #[doc = "## Safety"] @@ -2927,7 +2720,6 @@ pub unsafe fn vcmlaq_laneq_f32( ); vcmlaq_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] #[doc = "## Safety"] @@ -2946,7 +2738,6 @@ pub unsafe fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) - } _vcmla_rot180_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] #[doc = "## Safety"] @@ -2965,7 +2756,6 @@ pub unsafe fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) } _vcmlaq_rot180_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] #[doc = "## Safety"] @@ -2984,7 +2774,6 @@ pub unsafe fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) } _vcmlaq_rot180_f64(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"] #[doc = "## Safety"] @@ -3003,7 +2792,6 @@ pub unsafe fn vcmla_rot180_lane_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_rot180_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"] #[doc = "## Safety"] @@ -3031,7 +2819,6 @@ pub unsafe fn vcmlaq_rot180_lane_f32( ); vcmlaq_rot180_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"] #[doc = "## Safety"] @@ -3050,7 +2837,6 @@ pub unsafe fn vcmla_rot180_laneq_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_rot180_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"] #[doc = "## Safety"] @@ -3078,7 +2864,6 @@ pub unsafe fn vcmlaq_rot180_laneq_f32( ); vcmlaq_rot180_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] #[doc = "## Safety"] @@ -3097,7 +2882,6 @@ pub unsafe fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) - } _vcmla_rot270_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] #[doc = "## Safety"] @@ -3116,7 +2900,6 @@ pub unsafe fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) } _vcmlaq_rot270_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] #[doc = "## Safety"] @@ -3135,7 +2918,6 @@ pub unsafe fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) } _vcmlaq_rot270_f64(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"] #[doc = "## Safety"] @@ -3154,7 +2936,6 @@ pub unsafe fn vcmla_rot270_lane_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_rot270_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"] #[doc = "## Safety"] @@ -3182,7 +2963,6 @@ pub unsafe fn vcmlaq_rot270_lane_f32( ); vcmlaq_rot270_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"] #[doc = "## Safety"] @@ -3201,7 +2981,6 @@ pub unsafe fn vcmla_rot270_laneq_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_rot270_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"] #[doc = "## Safety"] @@ -3229,7 +3008,6 @@ pub unsafe fn vcmlaq_rot270_laneq_f32( ); vcmlaq_rot270_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] #[doc = "## Safety"] @@ -3248,7 +3026,6 @@ pub unsafe fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> } _vcmla_rot90_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] #[doc = "## Safety"] @@ -3267,7 +3044,6 @@ pub unsafe fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) - } _vcmlaq_rot90_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] #[doc = "## Safety"] @@ -3286,7 +3062,6 @@ pub unsafe fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) - } _vcmlaq_rot90_f64(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"] #[doc = "## Safety"] @@ -3305,7 +3080,6 @@ pub unsafe fn vcmla_rot90_lane_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_rot90_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"] #[doc = "## Safety"] @@ -3333,7 +3107,6 @@ pub unsafe fn vcmlaq_rot90_lane_f32( ); vcmlaq_rot90_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"] #[doc = "## Safety"] @@ -3352,7 +3125,6 @@ pub unsafe fn vcmla_rot90_laneq_f32( let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); vcmla_rot90_f32(a, b, c) } - #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"] #[doc = "## Safety"] @@ -3380,7 +3152,6 @@ pub unsafe fn vcmlaq_rot90_laneq_f32( ); vcmlaq_rot90_f32(a, b, c) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] #[doc = "## Safety"] @@ -3402,7 +3173,6 @@ pub unsafe fn vcopy_lane_f32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] #[doc = "## Safety"] @@ -3430,7 +3200,6 @@ pub unsafe fn vcopy_lane_s8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] #[doc = "## Safety"] @@ -3803,7 +3572,6 @@ pub unsafe fn vcopyq_lane_s8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] #[doc = "## Safety"] @@ -3827,7 +3595,6 @@ pub unsafe fn vcopy_lane_s16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] #[doc = "## Safety"] @@ -3856,7 +3623,6 @@ pub unsafe fn vcopyq_lane_s16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] #[doc = "## Safety"] @@ -3878,7 +3644,6 @@ pub unsafe fn vcopy_lane_s32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] #[doc = "## Safety"] @@ -3903,7 +3668,6 @@ pub unsafe fn vcopyq_lane_s32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] #[doc = "## Safety"] @@ -3931,7 +3695,6 @@ pub unsafe fn vcopy_lane_u8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] #[doc = "## Safety"] @@ -4304,7 +4067,6 @@ pub unsafe fn vcopyq_lane_u8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] #[doc = "## Safety"] @@ -4328,7 +4090,6 @@ pub unsafe fn vcopy_lane_u16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] #[doc = "## Safety"] @@ -4357,7 +4118,6 @@ pub unsafe fn vcopyq_lane_u16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] #[doc = "## Safety"] @@ -4379,7 +4139,6 @@ pub unsafe fn vcopy_lane_u32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] #[doc = "## Safety"] @@ -4404,7 +4163,6 @@ pub unsafe fn vcopyq_lane_u32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] #[doc = "## Safety"] @@ -4432,7 +4190,6 @@ pub unsafe fn vcopy_lane_p8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] #[doc = "## Safety"] @@ -4805,7 +4562,6 @@ pub unsafe fn vcopyq_lane_p8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] #[doc = "## Safety"] @@ -4829,7 +4585,6 @@ pub unsafe fn vcopy_lane_p16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] #[doc = "## Safety"] @@ -4858,7 +4613,6 @@ pub unsafe fn vcopyq_lane_p16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] #[doc = "## Safety"] @@ -4881,7 +4635,6 @@ pub unsafe fn vcopy_laneq_f32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] #[doc = "## Safety"] @@ -4905,7 +4658,6 @@ pub unsafe fn vcopyq_laneq_f32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] #[doc = "## Safety"] @@ -4927,7 +4679,6 @@ pub unsafe fn vcopyq_laneq_f64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] #[doc = "## Safety"] @@ -4956,7 +4707,6 @@ pub unsafe fn vcopy_laneq_s8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] #[doc = "## Safety"] @@ -5328,7 +5078,6 @@ pub unsafe fn vcopyq_laneq_s8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] #[doc = "## Safety"] @@ -5353,7 +5102,6 @@ pub unsafe fn vcopy_laneq_s16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] #[doc = "## Safety"] @@ -5381,7 +5129,6 @@ pub unsafe fn vcopyq_laneq_s16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] #[doc = "## Safety"] @@ -5404,7 +5151,6 @@ pub unsafe fn vcopy_laneq_s32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] #[doc = "## Safety"] @@ -5428,7 +5174,6 @@ pub unsafe fn vcopyq_laneq_s32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] #[doc = "## Safety"] @@ -5450,7 +5195,6 @@ pub unsafe fn vcopyq_laneq_s64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] #[doc = "## Safety"] @@ -5479,7 +5223,6 @@ pub unsafe fn vcopy_laneq_u8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] #[doc = "## Safety"] @@ -5851,7 +5594,6 @@ pub unsafe fn vcopyq_laneq_u8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] #[doc = "## Safety"] @@ -5876,7 +5618,6 @@ pub unsafe fn vcopy_laneq_u16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] #[doc = "## Safety"] @@ -5904,7 +5645,6 @@ pub unsafe fn vcopyq_laneq_u16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] #[doc = "## Safety"] @@ -5927,7 +5667,6 @@ pub unsafe fn vcopy_laneq_u32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] #[doc = "## Safety"] @@ -5951,7 +5690,6 @@ pub unsafe fn vcopyq_laneq_u32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] #[doc = "## Safety"] @@ -5973,7 +5711,6 @@ pub unsafe fn vcopyq_laneq_u64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] #[doc = "## Safety"] @@ -6002,7 +5739,6 @@ pub unsafe fn vcopy_laneq_p8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] #[doc = "## Safety"] @@ -6374,7 +6110,6 @@ pub unsafe fn vcopyq_laneq_p8( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] #[doc = "## Safety"] @@ -6399,7 +6134,6 @@ pub unsafe fn vcopy_laneq_p16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] #[doc = "## Safety"] @@ -6427,7 +6161,6 @@ pub unsafe fn vcopyq_laneq_p16( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] #[doc = "## Safety"] @@ -6449,7 +6182,6 @@ pub unsafe fn vcopyq_laneq_p64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"] #[doc = "## Safety"] @@ -6474,7 +6206,6 @@ pub unsafe fn vcopyq_lane_f32( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"] #[doc = "## Safety"] @@ -6497,7 +6228,6 @@ pub unsafe fn vcopyq_lane_f64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"] #[doc = "## Safety"] @@ -6520,7 +6250,6 @@ pub unsafe fn vcopyq_lane_s64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"] #[doc = "## Safety"] @@ -6543,7 +6272,6 @@ pub unsafe fn vcopyq_lane_u64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] #[doc = "## Safety"] @@ -6566,7 +6294,6 @@ pub unsafe fn vcopyq_lane_p64( _ => unreachable_unchecked(), } } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"] #[doc = "## Safety"] @@ -6578,7 +6305,6 @@ pub unsafe fn vcopyq_lane_p64( pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { transmute(a) } - #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"] #[doc = "## Safety"] @@ -6590,7 +6316,6 @@ pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { simd_cast(a) } - #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"] #[doc = "## Safety"] @@ -6602,7 +6327,6 @@ pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"] #[doc = "## Safety"] @@ -6614,7 +6338,6 @@ pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"] #[doc = "## Safety"] @@ -6626,7 +6349,6 @@ pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"] #[doc = "## Safety"] @@ -6638,7 +6360,6 @@ pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"] #[doc = "## Safety"] @@ -6650,7 +6371,6 @@ pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { simd_cast(a) } - #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"] #[doc = "## Safety"] @@ -6662,7 +6382,6 @@ pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { pub unsafe fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) } - #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"] #[doc = "## Safety"] @@ -6675,7 +6394,6 @@ pub unsafe fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); simd_cast(b) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"] #[doc = "## Safety"] @@ -6696,7 +6414,6 @@ pub unsafe fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { } _vcvt_n_f64_s64(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"] #[doc = "## Safety"] @@ -6717,7 +6434,6 @@ pub unsafe fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { } _vcvtq_n_f64_s64(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"] #[doc = "## Safety"] @@ -6738,7 +6454,6 @@ pub unsafe fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { } _vcvt_n_f64_u64(a.as_signed(), N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"] #[doc = "## Safety"] @@ -6759,7 +6474,6 @@ pub unsafe fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { } _vcvtq_n_f64_u64(a.as_signed(), N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"] #[doc = "## Safety"] @@ -6780,7 +6494,6 @@ pub unsafe fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { } _vcvt_n_s64_f64(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"] #[doc = "## Safety"] @@ -6801,7 +6514,6 @@ pub unsafe fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { } _vcvtq_n_s64_f64(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"] #[doc = "## Safety"] @@ -6822,7 +6534,6 @@ pub unsafe fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { } _vcvt_n_u64_f64(a, N).as_unsigned() } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"] #[doc = "## Safety"] @@ -6843,7 +6554,6 @@ pub unsafe fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { } _vcvtq_n_u64_f64(a, N).as_unsigned() } - #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"] #[doc = "## Safety"] @@ -6862,7 +6572,6 @@ pub unsafe fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { } _vcvt_s64_f64(a) } - #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"] #[doc = "## Safety"] @@ -6881,7 +6590,6 @@ pub unsafe fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { } _vcvtq_s64_f64(a) } - #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"] #[doc = "## Safety"] @@ -6900,7 +6608,6 @@ pub unsafe fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { } _vcvt_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"] #[doc = "## Safety"] @@ -6919,7 +6626,6 @@ pub unsafe fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { } _vcvtq_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"] #[doc = "## Safety"] @@ -6938,7 +6644,6 @@ pub unsafe fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvta_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"] #[doc = "## Safety"] @@ -6957,7 +6662,6 @@ pub unsafe fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtaq_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"] #[doc = "## Safety"] @@ -6976,7 +6680,6 @@ pub unsafe fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { } _vcvta_s64_f64(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"] #[doc = "## Safety"] @@ -6995,7 +6698,6 @@ pub unsafe fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { } _vcvtaq_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"] #[doc = "## Safety"] @@ -7014,7 +6716,6 @@ pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvta_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"] #[doc = "## Safety"] @@ -7033,7 +6734,6 @@ pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtaq_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"] #[doc = "## Safety"] @@ -7052,7 +6752,6 @@ pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { } _vcvta_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"] #[doc = "## Safety"] @@ -7071,7 +6770,6 @@ pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { } _vcvtaq_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"] #[doc = "## Safety"] @@ -7090,7 +6788,6 @@ pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { } _vcvtas_s32_f32(a) } - #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"] #[doc = "## Safety"] @@ -7109,7 +6806,6 @@ pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { } _vcvtad_s64_f64(a) } - #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"] #[doc = "## Safety"] @@ -7128,7 +6824,6 @@ pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { } _vcvtas_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"] #[doc = "## Safety"] @@ -7147,7 +6842,6 @@ pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { } _vcvtad_u64_f64(a).as_unsigned() } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"] #[doc = "## Safety"] @@ -7159,7 +6853,6 @@ pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { a as f64 } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"] #[doc = "## Safety"] @@ -7171,7 +6864,6 @@ pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { pub unsafe fn vcvts_f32_s32(a: i32) -> f32 { a as f32 } - #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"] #[doc = "## Safety"] @@ -7190,7 +6882,6 @@ pub unsafe fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvtm_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"] #[doc = "## Safety"] @@ -7209,7 +6900,6 @@ pub unsafe fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtmq_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"] #[doc = "## Safety"] @@ -7228,7 +6918,6 @@ pub unsafe fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { } _vcvtm_s64_f64(a) } - #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"] #[doc = "## Safety"] @@ -7247,7 +6936,6 @@ pub unsafe fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { } _vcvtmq_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"] #[doc = "## Safety"] @@ -7266,7 +6954,6 @@ pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvtm_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"] #[doc = "## Safety"] @@ -7285,7 +6972,6 @@ pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtmq_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"] #[doc = "## Safety"] @@ -7304,7 +6990,6 @@ pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { } _vcvtm_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"] #[doc = "## Safety"] @@ -7323,7 +7008,6 @@ pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { } _vcvtmq_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"] #[doc = "## Safety"] @@ -7342,7 +7026,6 @@ pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { } _vcvtms_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"] #[doc = "## Safety"] @@ -7361,7 +7044,6 @@ pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { } _vcvtmd_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"] #[doc = "## Safety"] @@ -7380,7 +7062,6 @@ pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { } _vcvtms_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"] #[doc = "## Safety"] @@ -7399,7 +7080,6 @@ pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { } _vcvtmd_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"] #[doc = "## Safety"] @@ -7418,7 +7098,6 @@ pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvtn_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"] #[doc = "## Safety"] @@ -7437,7 +7116,6 @@ pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtnq_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"] #[doc = "## Safety"] @@ -7456,7 +7134,6 @@ pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { } _vcvtn_s64_f64(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"] #[doc = "## Safety"] @@ -7475,7 +7152,6 @@ pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { } _vcvtnq_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"] #[doc = "## Safety"] @@ -7494,7 +7170,6 @@ pub unsafe fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvtn_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"] #[doc = "## Safety"] @@ -7513,7 +7188,6 @@ pub unsafe fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtnq_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"] #[doc = "## Safety"] @@ -7532,7 +7206,6 @@ pub unsafe fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { } _vcvtn_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"] #[doc = "## Safety"] @@ -7551,7 +7224,6 @@ pub unsafe fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { } _vcvtnq_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"] #[doc = "## Safety"] @@ -7570,7 +7242,6 @@ pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { } _vcvtns_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"] #[doc = "## Safety"] @@ -7589,7 +7260,6 @@ pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { } _vcvtnd_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"] #[doc = "## Safety"] @@ -7608,7 +7278,6 @@ pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { } _vcvtns_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"] #[doc = "## Safety"] @@ -7627,7 +7296,6 @@ pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { } _vcvtnd_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"] #[doc = "## Safety"] @@ -7646,7 +7314,6 @@ pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvtp_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"] #[doc = "## Safety"] @@ -7665,7 +7332,6 @@ pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtpq_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"] #[doc = "## Safety"] @@ -7684,7 +7350,6 @@ pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { } _vcvtp_s64_f64(a) } - #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"] #[doc = "## Safety"] @@ -7703,7 +7368,6 @@ pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { } _vcvtpq_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"] #[doc = "## Safety"] @@ -7722,7 +7386,6 @@ pub unsafe fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvtp_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"] #[doc = "## Safety"] @@ -7741,7 +7404,6 @@ pub unsafe fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtpq_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"] #[doc = "## Safety"] @@ -7760,7 +7422,6 @@ pub unsafe fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { } _vcvtp_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"] #[doc = "## Safety"] @@ -7779,7 +7440,6 @@ pub unsafe fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { } _vcvtpq_u64_f64(a).as_unsigned() } - #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"] #[doc = "## Safety"] @@ -7798,7 +7458,6 @@ pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { } _vcvtps_s32_f32(a) } - #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"] #[doc = "## Safety"] @@ -7817,7 +7476,6 @@ pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { } _vcvtpd_s64_f64(a) } - #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"] #[doc = "## Safety"] @@ -7836,7 +7494,6 @@ pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { } _vcvtps_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"] #[doc = "## Safety"] @@ -7855,7 +7512,6 @@ pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { } _vcvtpd_u64_f64(a).as_unsigned() } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"] #[doc = "## Safety"] @@ -7867,7 +7523,6 @@ pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { a as f32 } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"] #[doc = "## Safety"] @@ -7879,7 +7534,6 @@ pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { pub unsafe fn vcvtd_f64_u64(a: u64) -> f64 { a as f64 } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"] #[doc = "## Safety"] @@ -7900,7 +7554,6 @@ pub unsafe fn vcvts_n_f32_s32(a: i32) -> f32 { } _vcvts_n_f32_s32(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"] #[doc = "## Safety"] @@ -7921,7 +7574,6 @@ pub unsafe fn vcvtd_n_f64_s64(a: i64) -> f64 { } _vcvtd_n_f64_s64(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"] #[doc = "## Safety"] @@ -7942,7 +7594,6 @@ pub unsafe fn vcvts_n_f32_u32(a: u32) -> f32 { } _vcvts_n_f32_u32(a.as_signed(), N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"] #[doc = "## Safety"] @@ -7963,7 +7614,6 @@ pub unsafe fn vcvtd_n_f64_u64(a: u64) -> f64 { } _vcvtd_n_f64_u64(a.as_signed(), N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"] #[doc = "## Safety"] @@ -7984,7 +7634,6 @@ pub unsafe fn vcvts_n_s32_f32(a: f32) -> i32 { } _vcvts_n_s32_f32(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"] #[doc = "## Safety"] @@ -8005,7 +7654,6 @@ pub unsafe fn vcvtd_n_s64_f64(a: f64) -> i64 { } _vcvtd_n_s64_f64(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"] #[doc = "## Safety"] @@ -8026,7 +7674,6 @@ pub unsafe fn vcvts_n_u32_f32(a: f32) -> u32 { } _vcvts_n_u32_f32(a, N).as_unsigned() } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"] #[doc = "## Safety"] @@ -8047,7 +7694,6 @@ pub unsafe fn vcvtd_n_u64_f64(a: f64) -> u64 { } _vcvtd_n_u64_f64(a, N).as_unsigned() } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"] #[doc = "## Safety"] @@ -8059,7 +7705,6 @@ pub unsafe fn vcvtd_n_u64_f64(a: f64) -> u64 { pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { a as i32 } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"] #[doc = "## Safety"] @@ -8071,7 +7716,6 @@ pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { a as i64 } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"] #[doc = "## Safety"] @@ -8083,7 +7727,6 @@ pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { a as u32 } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"] #[doc = "## Safety"] @@ -8095,7 +7738,6 @@ pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { pub unsafe fn vcvtd_u64_f64(a: f64) -> u64 { a as u64 } - #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"] #[doc = "## Safety"] @@ -8114,7 +7756,6 @@ pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { } _vcvtx_f32_f64(a) } - #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"] #[doc = "## Safety"] @@ -8126,7 +7767,6 @@ pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) } - #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"] #[doc = "## Safety"] @@ -8138,7 +7778,6 @@ pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t pub unsafe fn vcvtxd_f32_f64(a: f64) -> f32 { simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) } - #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"] #[doc = "## Safety"] @@ -8150,7 +7789,6 @@ pub unsafe fn vcvtxd_f32_f64(a: f64) -> f32 { pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_div(a, b) } - #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"] #[doc = "## Safety"] @@ -8162,7 +7800,6 @@ pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_div(a, b) } - #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"] #[doc = "## Safety"] @@ -8174,7 +7811,6 @@ pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { simd_div(a, b) } - #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"] #[doc = "## Safety"] @@ -8186,7 +7822,6 @@ pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_div(a, b) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] #[doc = "## Safety"] @@ -8206,7 +7841,6 @@ pub unsafe fn vdot_laneq_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vdot_s32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] #[doc = "## Safety"] @@ -8226,7 +7860,6 @@ pub unsafe fn vdotq_laneq_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vdotq_s32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] #[doc = "## Safety"] @@ -8246,7 +7879,6 @@ pub unsafe fn vdot_laneq_u32( let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vdot_u32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] #[doc = "## Safety"] @@ -8266,7 +7898,6 @@ pub unsafe fn vdotq_laneq_u32( let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vdotq_u32(a, b, transmute(c)) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] #[doc = "## Safety"] @@ -8280,7 +7911,6 @@ pub unsafe fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { static_assert!(N == 0); a } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"] #[doc = "## Safety"] @@ -8294,7 +7924,6 @@ pub unsafe fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { static_assert!(N == 0); a } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"] #[doc = "## Safety"] @@ -8308,7 +7937,6 @@ pub unsafe fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(N, 1); transmute::(simd_extract!(a, N as u32)) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"] #[doc = "## Safety"] @@ -8322,7 +7950,6 @@ pub unsafe fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { static_assert_uimm_bits!(N, 1); transmute::(simd_extract!(a, N as u32)) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"] #[doc = "## Safety"] @@ -8336,7 +7963,6 @@ pub unsafe fn vdupb_lane_s8(a: int8x8_t) -> i8 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"] #[doc = "## Safety"] @@ -8350,7 +7976,6 @@ pub unsafe fn vduph_laneq_s16(a: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"] #[doc = "## Safety"] @@ -8364,7 +7989,6 @@ pub unsafe fn vdupb_lane_u8(a: uint8x8_t) -> u8 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"] #[doc = "## Safety"] @@ -8378,7 +8002,6 @@ pub unsafe fn vduph_laneq_u16(a: uint16x8_t) -> u16 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"] #[doc = "## Safety"] @@ -8392,7 +8015,6 @@ pub unsafe fn vdupb_lane_p8(a: poly8x8_t) -> p8 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"] #[doc = "## Safety"] @@ -8406,7 +8028,6 @@ pub unsafe fn vduph_laneq_p16(a: poly16x8_t) -> p16 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"] #[doc = "## Safety"] @@ -8420,7 +8041,6 @@ pub unsafe fn vdupb_laneq_s8(a: int8x16_t) -> i8 { static_assert_uimm_bits!(N, 4); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"] #[doc = "## Safety"] @@ -8434,7 +8054,6 @@ pub unsafe fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { static_assert_uimm_bits!(N, 4); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"] #[doc = "## Safety"] @@ -8448,7 +8067,6 @@ pub unsafe fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { static_assert_uimm_bits!(N, 4); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"] #[doc = "## Safety"] @@ -8462,7 +8080,6 @@ pub unsafe fn vdupd_lane_f64(a: float64x1_t) -> f64 { static_assert!(N == 0); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"] #[doc = "## Safety"] @@ -8476,7 +8093,6 @@ pub unsafe fn vdupd_lane_s64(a: int64x1_t) -> i64 { static_assert!(N == 0); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"] #[doc = "## Safety"] @@ -8490,7 +8106,6 @@ pub unsafe fn vdupd_lane_u64(a: uint64x1_t) -> u64 { static_assert!(N == 0); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] #[doc = "## Safety"] @@ -8504,7 +8119,6 @@ pub unsafe fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { static_assert!(N == 0); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] #[doc = "## Safety"] @@ -8518,7 +8132,6 @@ pub unsafe fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { static_assert!(N == 0); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] #[doc = "## Safety"] @@ -8532,7 +8145,6 @@ pub unsafe fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] #[doc = "## Safety"] @@ -8546,7 +8158,6 @@ pub unsafe fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] #[doc = "## Safety"] @@ -8560,7 +8171,6 @@ pub unsafe fn vdups_lane_f32(a: float32x2_t) -> f32 { static_assert_uimm_bits!(N, 1); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] #[doc = "## Safety"] @@ -8574,7 +8184,6 @@ pub unsafe fn vdupd_laneq_f64(a: float64x2_t) -> f64 { static_assert_uimm_bits!(N, 1); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"] #[doc = "## Safety"] @@ -8588,7 +8197,6 @@ pub unsafe fn vdups_lane_s32(a: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"] #[doc = "## Safety"] @@ -8602,7 +8210,6 @@ pub unsafe fn vdupd_laneq_s64(a: int64x2_t) -> i64 { static_assert_uimm_bits!(N, 1); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"] #[doc = "## Safety"] @@ -8616,7 +8223,6 @@ pub unsafe fn vdups_lane_u32(a: uint32x2_t) -> u32 { static_assert_uimm_bits!(N, 1); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"] #[doc = "## Safety"] @@ -8630,7 +8236,6 @@ pub unsafe fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { static_assert_uimm_bits!(N, 1); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"] #[doc = "## Safety"] @@ -8644,7 +8249,6 @@ pub unsafe fn vdups_laneq_f32(a: float32x4_t) -> f32 { static_assert_uimm_bits!(N, 2); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"] #[doc = "## Safety"] @@ -8658,7 +8262,6 @@ pub unsafe fn vduph_lane_s16(a: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"] #[doc = "## Safety"] @@ -8672,7 +8275,6 @@ pub unsafe fn vdups_laneq_s32(a: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"] #[doc = "## Safety"] @@ -8686,7 +8288,6 @@ pub unsafe fn vduph_lane_u16(a: uint16x4_t) -> u16 { static_assert_uimm_bits!(N, 2); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"] #[doc = "## Safety"] @@ -8700,7 +8301,6 @@ pub unsafe fn vdups_laneq_u32(a: uint32x4_t) -> u32 { static_assert_uimm_bits!(N, 2); simd_extract!(a, N as u32) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"] #[doc = "## Safety"] @@ -8714,7 +8314,6 @@ pub unsafe fn vduph_lane_p16(a: poly16x4_t) -> p16 { static_assert_uimm_bits!(N, 2); simd_extract!(a, N as u32) } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"] #[doc = "## Safety"] @@ -8733,7 +8332,6 @@ pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } _veor3q_s8(a, b, c) } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"] #[doc = "## Safety"] @@ -8752,7 +8350,6 @@ pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t } _veor3q_s16(a, b, c) } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"] #[doc = "## Safety"] @@ -8771,7 +8368,6 @@ pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t } _veor3q_s32(a, b, c) } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"] #[doc = "## Safety"] @@ -8790,7 +8386,6 @@ pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t } _veor3q_s64(a, b, c) } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"] #[doc = "## Safety"] @@ -8809,7 +8404,6 @@ pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16 } _veor3q_u8(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"] #[doc = "## Safety"] @@ -8828,7 +8422,6 @@ pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x } _veor3q_u16(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"] #[doc = "## Safety"] @@ -8847,7 +8440,6 @@ pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x } _veor3q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"] #[doc = "## Safety"] @@ -8866,7 +8458,6 @@ pub unsafe fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x } _veor3q_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] #[doc = "## Safety"] @@ -8884,7 +8475,6 @@ pub unsafe fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64 _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] #[doc = "## Safety"] @@ -8902,7 +8492,6 @@ pub unsafe fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_ _ => unreachable_unchecked(), } } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"] #[doc = "## Safety"] @@ -8921,7 +8510,6 @@ pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float6 } _vfma_f64(b, c, a) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"] #[doc = "## Safety"] @@ -8939,7 +8527,6 @@ pub unsafe fn vfma_lane_f32( static_assert_uimm_bits!(LANE, 1); vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"] #[doc = "## Safety"] @@ -8957,7 +8544,6 @@ pub unsafe fn vfma_laneq_f32( static_assert_uimm_bits!(LANE, 2); vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"] #[doc = "## Safety"] @@ -8975,7 +8561,6 @@ pub unsafe fn vfmaq_lane_f32( static_assert_uimm_bits!(LANE, 1); vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"] #[doc = "## Safety"] @@ -8993,7 +8578,6 @@ pub unsafe fn vfmaq_laneq_f32( static_assert_uimm_bits!(LANE, 2); vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"] #[doc = "## Safety"] @@ -9011,7 +8595,6 @@ pub unsafe fn vfmaq_laneq_f64( static_assert_uimm_bits!(LANE, 1); vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"] #[doc = "## Safety"] @@ -9029,7 +8612,6 @@ pub unsafe fn vfma_lane_f64( static_assert!(LANE == 0); vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"] #[doc = "## Safety"] @@ -9047,7 +8629,6 @@ pub unsafe fn vfma_laneq_f64( static_assert_uimm_bits!(LANE, 1); vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"] #[doc = "## Safety"] @@ -9059,7 +8640,6 @@ pub unsafe fn vfma_laneq_f64( pub unsafe fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { vfma_f64(a, b, vdup_n_f64(c)) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"] #[doc = "## Safety"] @@ -9081,7 +8661,6 @@ pub unsafe fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> let c: f64 = simd_extract!(c, LANE as u32); _vfmad_lane_f64(b, c, a) } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"] #[doc = "## Safety"] @@ -9100,7 +8679,6 @@ pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float } _vfmaq_f64(b, c, a) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"] #[doc = "## Safety"] @@ -9118,7 +8696,6 @@ pub unsafe fn vfmaq_lane_f64( static_assert!(LANE == 0); vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"] #[doc = "## Safety"] @@ -9130,7 +8707,6 @@ pub unsafe fn vfmaq_lane_f64( pub unsafe fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { vfmaq_f64(a, b, vdupq_n_f64(c)) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"] #[doc = "## Safety"] @@ -9152,7 +8728,6 @@ pub unsafe fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> let c: f32 = simd_extract!(c, LANE as u32); _vfmas_lane_f32(b, c, a) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"] #[doc = "## Safety"] @@ -9174,7 +8749,6 @@ pub unsafe fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) - let c: f32 = simd_extract!(c, LANE as u32); _vfmas_laneq_f32(b, c, a) } - #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"] #[doc = "## Safety"] @@ -9196,7 +8770,6 @@ pub unsafe fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) - let c: f64 = simd_extract!(c, LANE as u32); _vfmad_laneq_f64(b, c, a) } - #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"] #[doc = "## Safety"] @@ -9209,7 +8782,6 @@ pub unsafe fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float6 let b: float64x1_t = simd_neg(b); vfma_f64(a, b, c) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"] #[doc = "## Safety"] @@ -9227,7 +8799,6 @@ pub unsafe fn vfms_lane_f32( static_assert_uimm_bits!(LANE, 1); vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"] #[doc = "## Safety"] @@ -9245,7 +8816,6 @@ pub unsafe fn vfms_laneq_f32( static_assert_uimm_bits!(LANE, 2); vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"] #[doc = "## Safety"] @@ -9263,7 +8833,6 @@ pub unsafe fn vfmsq_lane_f32( static_assert_uimm_bits!(LANE, 1); vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"] #[doc = "## Safety"] @@ -9281,7 +8850,6 @@ pub unsafe fn vfmsq_laneq_f32( static_assert_uimm_bits!(LANE, 2); vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"] #[doc = "## Safety"] @@ -9299,7 +8867,6 @@ pub unsafe fn vfmsq_laneq_f64( static_assert_uimm_bits!(LANE, 1); vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"] #[doc = "## Safety"] @@ -9317,7 +8884,6 @@ pub unsafe fn vfms_lane_f64( static_assert!(LANE == 0); vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"] #[doc = "## Safety"] @@ -9335,7 +8901,6 @@ pub unsafe fn vfms_laneq_f64( static_assert_uimm_bits!(LANE, 1); vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"] #[doc = "## Safety"] @@ -9347,7 +8912,6 @@ pub unsafe fn vfms_laneq_f64( pub unsafe fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { vfms_f64(a, b, vdup_n_f64(c)) } - #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"] #[doc = "## Safety"] @@ -9360,7 +8924,6 @@ pub unsafe fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float let b: float64x2_t = simd_neg(b); vfmaq_f64(a, b, c) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"] #[doc = "## Safety"] @@ -9378,7 +8941,6 @@ pub unsafe fn vfmsq_lane_f64( static_assert!(LANE == 0); vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } - #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"] #[doc = "## Safety"] @@ -9390,7 +8952,6 @@ pub unsafe fn vfmsq_lane_f64( pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { vfmsq_f64(a, b, vdupq_n_f64(c)) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"] #[doc = "## Safety"] @@ -9403,7 +8964,6 @@ pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t pub unsafe fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { vfmas_lane_f32::(a, -b, c) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"] #[doc = "## Safety"] @@ -9416,7 +8976,6 @@ pub unsafe fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> pub unsafe fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { vfmas_laneq_f32::(a, -b, c) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"] #[doc = "## Safety"] @@ -9429,7 +8988,6 @@ pub unsafe fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) - pub unsafe fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { vfmad_lane_f64::(a, -b, c) } - #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"] #[doc = "## Safety"] @@ -9442,7 +9000,6 @@ pub unsafe fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> pub unsafe fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { vfmad_laneq_f64::(a, -b, c) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"] #[doc = "## Safety"] @@ -9461,7 +9018,6 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { } _vld1_f64_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] #[doc = "## Safety"] @@ -9480,7 +9036,6 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { } _vld1_f64_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] #[doc = "## Safety"] @@ -9499,7 +9054,6 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { } _vld1_f64_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] #[doc = "## Safety"] @@ -9518,7 +9072,6 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { } _vld1q_f64_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] #[doc = "## Safety"] @@ -9537,7 +9090,6 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { } _vld1q_f64_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] #[doc = "## Safety"] @@ -9556,7 +9108,6 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { } _vld1q_f64_x4(a) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] #[doc = "## Safety"] @@ -9575,7 +9126,6 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { } _vld2_dup_f64(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"] #[doc = "## Safety"] @@ -9594,7 +9144,6 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { } _vld2q_dup_f64(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"] #[doc = "## Safety"] @@ -9613,7 +9162,6 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { } _vld2q_dup_s64(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"] #[doc = "## Safety"] @@ -9632,7 +9180,6 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { } _vld2_f64(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] #[doc = "## Safety"] @@ -9653,7 +9200,6 @@ pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> } _vld2_lane_f64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"] #[doc = "## Safety"] @@ -9674,7 +9220,6 @@ pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> i } _vld2_lane_s64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"] #[doc = "## Safety"] @@ -9688,7 +9233,6 @@ pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> static_assert!(LANE == 0); transmute(vld2_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"] #[doc = "## Safety"] @@ -9702,7 +9246,6 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> static_assert!(LANE == 0); transmute(vld2_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] @@ -9714,7 +9257,6 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { transmute(vld2q_dup_s64(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] @@ -9726,7 +9268,6 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_dup_s64(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"] #[doc = "## Safety"] @@ -9745,7 +9286,6 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { } _vld2q_f64(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"] #[doc = "## Safety"] @@ -9764,7 +9304,6 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { } _vld2q_s64(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"] #[doc = "## Safety"] @@ -9786,7 +9325,6 @@ pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) - } _vld2q_lane_f64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"] #[doc = "## Safety"] @@ -9807,7 +9345,6 @@ pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> in } _vld2q_lane_s8(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"] #[doc = "## Safety"] @@ -9828,7 +9365,6 @@ pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> } _vld2q_lane_s64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"] #[doc = "## Safety"] @@ -9842,7 +9378,6 @@ pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld2q_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"] #[doc = "## Safety"] @@ -9856,7 +9391,6 @@ pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> u static_assert_uimm_bits!(LANE, 4); transmute(vld2q_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"] #[doc = "## Safety"] @@ -9870,7 +9404,6 @@ pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld2q_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"] #[doc = "## Safety"] @@ -9884,7 +9417,6 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p static_assert_uimm_bits!(LANE, 4); transmute(vld2q_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] @@ -9896,7 +9428,6 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { transmute(vld2q_s64(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] @@ -9908,7 +9439,6 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_s64(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] @@ -9927,7 +9457,6 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { } _vld3_dup_f64(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"] #[doc = "## Safety"] @@ -9946,7 +9475,6 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { } _vld3q_dup_f64(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"] #[doc = "## Safety"] @@ -9965,7 +9493,6 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { } _vld3q_dup_s64(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"] #[doc = "## Safety"] @@ -9984,7 +9511,6 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { } _vld3_f64(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] #[doc = "## Safety"] @@ -10011,7 +9537,6 @@ pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> } _vld3_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"] #[doc = "## Safety"] @@ -10025,7 +9550,6 @@ pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> static_assert!(LANE == 0); transmute(vld3_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"] #[doc = "## Safety"] @@ -10052,7 +9576,6 @@ pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> i } _vld3_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"] #[doc = "## Safety"] @@ -10066,7 +9589,6 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> static_assert!(LANE == 0); transmute(vld3_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] @@ -10078,7 +9600,6 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { transmute(vld3q_dup_s64(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] @@ -10090,7 +9611,6 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_dup_s64(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"] #[doc = "## Safety"] @@ -10109,7 +9629,6 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { } _vld3q_f64(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] #[doc = "## Safety"] @@ -10128,7 +9647,6 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { } _vld3q_s64(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] #[doc = "## Safety"] @@ -10155,7 +9673,6 @@ pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) - } _vld3q_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"] #[doc = "## Safety"] @@ -10169,7 +9686,6 @@ pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld3q_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"] #[doc = "## Safety"] @@ -10196,7 +9712,6 @@ pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> in } _vld3q_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"] #[doc = "## Safety"] @@ -10223,7 +9738,6 @@ pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> } _vld3q_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"] #[doc = "## Safety"] @@ -10237,7 +9751,6 @@ pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> u static_assert_uimm_bits!(LANE, 4); transmute(vld3q_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"] #[doc = "## Safety"] @@ -10251,7 +9764,6 @@ pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld3q_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"] #[doc = "## Safety"] @@ -10265,7 +9777,6 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p static_assert_uimm_bits!(LANE, 4); transmute(vld3q_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] @@ -10277,7 +9788,6 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { transmute(vld3q_s64(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] @@ -10289,7 +9799,6 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_s64(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] @@ -10308,7 +9817,6 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { } _vld4_dup_f64(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"] #[doc = "## Safety"] @@ -10327,7 +9835,6 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { } _vld4q_dup_f64(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"] #[doc = "## Safety"] @@ -10346,7 +9853,6 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { } _vld4q_dup_s64(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"] #[doc = "## Safety"] @@ -10365,7 +9871,6 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { } _vld4_f64(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] #[doc = "## Safety"] @@ -10393,7 +9898,6 @@ pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> } _vld4_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"] #[doc = "## Safety"] @@ -10421,7 +9925,6 @@ pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> i } _vld4_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"] #[doc = "## Safety"] @@ -10435,7 +9938,6 @@ pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> static_assert!(LANE == 0); transmute(vld4_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"] #[doc = "## Safety"] @@ -10449,7 +9951,6 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> static_assert!(LANE == 0); transmute(vld4_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] @@ -10461,7 +9962,6 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_dup_s64(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] @@ -10473,7 +9973,6 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_dup_s64(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"] #[doc = "## Safety"] @@ -10492,7 +9991,6 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { } _vld4q_f64(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] #[doc = "## Safety"] @@ -10511,7 +10009,6 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { } _vld4q_s64(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] #[doc = "## Safety"] @@ -10539,7 +10036,6 @@ pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) - } _vld4q_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"] #[doc = "## Safety"] @@ -10567,7 +10063,6 @@ pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> in } _vld4q_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"] #[doc = "## Safety"] @@ -10595,7 +10090,6 @@ pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> } _vld4q_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"] #[doc = "## Safety"] @@ -10609,7 +10103,6 @@ pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld4q_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"] #[doc = "## Safety"] @@ -10623,7 +10116,6 @@ pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> u static_assert_uimm_bits!(LANE, 4); transmute(vld4q_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"] #[doc = "## Safety"] @@ -10637,7 +10129,6 @@ pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld4q_lane_s64::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"] #[doc = "## Safety"] @@ -10651,7 +10142,6 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p static_assert_uimm_bits!(LANE, 4); transmute(vld4q_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] @@ -10663,7 +10153,6 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_s64(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] @@ -10675,7 +10164,6 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_s64(transmute(a))) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"] #[doc = "## Safety"] @@ -10694,7 +10182,6 @@ pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vmax_f64(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"] #[doc = "## Safety"] @@ -10713,7 +10200,6 @@ pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vmaxq_f64(a, b) } - #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"] #[doc = "## Safety"] @@ -10732,7 +10218,6 @@ pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vmaxnm_f64(a, b) } - #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] #[doc = "## Safety"] @@ -10751,7 +10236,6 @@ pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vmaxnmq_f64(a, b) } - #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] #[doc = "## Safety"] @@ -10770,7 +10254,6 @@ pub unsafe fn vmaxnmv_f32(a: float32x2_t) -> f32 { } _vmaxnmv_f32(a) } - #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] #[doc = "## Safety"] @@ -10789,7 +10272,6 @@ pub unsafe fn vmaxnmvq_f64(a: float64x2_t) -> f64 { } _vmaxnmvq_f64(a) } - #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] #[doc = "## Safety"] @@ -10808,7 +10290,6 @@ pub unsafe fn vmaxnmvq_f32(a: float32x4_t) -> f32 { } _vmaxnmvq_f32(a) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"] #[doc = "## Safety"] @@ -10827,7 +10308,6 @@ pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vmin_f64(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"] #[doc = "## Safety"] @@ -10846,7 +10326,6 @@ pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vminq_f64(a, b) } - #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"] #[doc = "## Safety"] @@ -10865,7 +10344,6 @@ pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vminnm_f64(a, b) } - #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] #[doc = "## Safety"] @@ -10884,7 +10362,6 @@ pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vminnmq_f64(a, b) } - #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] #[doc = "## Safety"] @@ -10903,7 +10380,6 @@ pub unsafe fn vminnmv_f32(a: float32x2_t) -> f32 { } _vminnmv_f32(a) } - #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] #[doc = "## Safety"] @@ -10922,7 +10398,6 @@ pub unsafe fn vminnmvq_f64(a: float64x2_t) -> f64 { } _vminnmvq_f64(a) } - #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] #[doc = "## Safety"] @@ -10941,7 +10416,6 @@ pub unsafe fn vminnmvq_f32(a: float32x4_t) -> f32 { } _vminnmvq_f32(a) } - #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"] #[doc = "## Safety"] @@ -10953,7 +10427,6 @@ pub unsafe fn vminnmvq_f32(a: float32x4_t) -> f32 { pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"] #[doc = "## Safety"] @@ -10965,7 +10438,6 @@ pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float6 pub unsafe fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"] #[doc = "## Safety"] @@ -11000,7 +10472,6 @@ pub unsafe fn vmlal_high_lane_s16( ), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"] #[doc = "## Safety"] @@ -11035,7 +10506,6 @@ pub unsafe fn vmlal_high_laneq_s16( ), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"] #[doc = "## Safety"] @@ -11057,7 +10527,6 @@ pub unsafe fn vmlal_high_lane_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"] #[doc = "## Safety"] @@ -11079,7 +10548,6 @@ pub unsafe fn vmlal_high_laneq_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"] #[doc = "## Safety"] @@ -11114,7 +10582,6 @@ pub unsafe fn vmlal_high_lane_u16( ), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"] #[doc = "## Safety"] @@ -11149,7 +10616,6 @@ pub unsafe fn vmlal_high_laneq_u16( ), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"] #[doc = "## Safety"] @@ -11171,7 +10637,6 @@ pub unsafe fn vmlal_high_lane_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"] #[doc = "## Safety"] @@ -11193,7 +10658,6 @@ pub unsafe fn vmlal_high_laneq_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"] #[doc = "## Safety"] @@ -11205,7 +10669,6 @@ pub unsafe fn vmlal_high_laneq_u32( pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlal_high_s16(a, b, vdupq_n_s16(c)) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"] #[doc = "## Safety"] @@ -11217,7 +10680,6 @@ pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlal_high_s32(a, b, vdupq_n_s32(c)) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"] #[doc = "## Safety"] @@ -11229,7 +10691,6 @@ pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlal_high_u16(a, b, vdupq_n_u16(c)) } - #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"] #[doc = "## Safety"] @@ -11241,7 +10702,6 @@ pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4 pub unsafe fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlal_high_u32(a, b, vdupq_n_u32(c)) } - #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"] #[doc = "## Safety"] @@ -11255,7 +10715,6 @@ pub unsafe fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8 let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); vmlal_s8(a, b, c) } - #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"] #[doc = "## Safety"] @@ -11269,7 +10728,6 @@ pub unsafe fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); vmlal_s16(a, b, c) } - #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"] #[doc = "## Safety"] @@ -11283,7 +10741,6 @@ pub unsafe fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); vmlal_s32(a, b, c) } - #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"] #[doc = "## Safety"] @@ -11297,7 +10754,6 @@ pub unsafe fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); vmlal_u8(a, b, c) } - #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"] #[doc = "## Safety"] @@ -11311,7 +10767,6 @@ pub unsafe fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uin let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); vmlal_u16(a, b, c) } - #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"] #[doc = "## Safety"] @@ -11325,7 +10780,6 @@ pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uin let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); vmlal_u32(a, b, c) } - #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"] #[doc = "## Safety"] @@ -11337,7 +10791,6 @@ pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uin pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"] #[doc = "## Safety"] @@ -11349,7 +10802,6 @@ pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float6 pub unsafe fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"] #[doc = "## Safety"] @@ -11384,7 +10836,6 @@ pub unsafe fn vmlsl_high_lane_s16( ), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"] #[doc = "## Safety"] @@ -11419,7 +10870,6 @@ pub unsafe fn vmlsl_high_laneq_s16( ), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"] #[doc = "## Safety"] @@ -11441,7 +10891,6 @@ pub unsafe fn vmlsl_high_lane_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"] #[doc = "## Safety"] @@ -11463,7 +10912,6 @@ pub unsafe fn vmlsl_high_laneq_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"] #[doc = "## Safety"] @@ -11498,7 +10946,6 @@ pub unsafe fn vmlsl_high_lane_u16( ), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"] #[doc = "## Safety"] @@ -11533,7 +10980,6 @@ pub unsafe fn vmlsl_high_laneq_u16( ), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"] #[doc = "## Safety"] @@ -11555,7 +11001,6 @@ pub unsafe fn vmlsl_high_lane_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"] #[doc = "## Safety"] @@ -11577,7 +11022,6 @@ pub unsafe fn vmlsl_high_laneq_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"] #[doc = "## Safety"] @@ -11589,7 +11033,6 @@ pub unsafe fn vmlsl_high_laneq_u32( pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlsl_high_s16(a, b, vdupq_n_s16(c)) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"] #[doc = "## Safety"] @@ -11601,7 +11044,6 @@ pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlsl_high_s32(a, b, vdupq_n_s32(c)) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"] #[doc = "## Safety"] @@ -11613,7 +11055,6 @@ pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlsl_high_u16(a, b, vdupq_n_u16(c)) } - #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"] #[doc = "## Safety"] @@ -11625,7 +11066,6 @@ pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4 pub unsafe fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlsl_high_u32(a, b, vdupq_n_u32(c)) } - #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"] #[doc = "## Safety"] @@ -11639,7 +11079,6 @@ pub unsafe fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8 let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); vmlsl_s8(a, b, c) } - #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"] #[doc = "## Safety"] @@ -11653,7 +11092,6 @@ pub unsafe fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); vmlsl_s16(a, b, c) } - #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"] #[doc = "## Safety"] @@ -11667,7 +11105,6 @@ pub unsafe fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); vmlsl_s32(a, b, c) } - #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"] #[doc = "## Safety"] @@ -11681,7 +11118,6 @@ pub unsafe fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); vmlsl_u8(a, b, c) } - #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"] #[doc = "## Safety"] @@ -11695,7 +11131,6 @@ pub unsafe fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uin let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); vmlsl_u16(a, b, c) } - #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"] #[doc = "## Safety"] @@ -11709,7 +11144,6 @@ pub unsafe fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uin let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); vmlsl_u32(a, b, c) } - #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"] #[doc = "## Safety"] @@ -11722,7 +11156,6 @@ pub unsafe fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); vmovl_s8(a) } - #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"] #[doc = "## Safety"] @@ -11735,7 +11168,6 @@ pub unsafe fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); vmovl_s16(a) } - #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"] #[doc = "## Safety"] @@ -11748,7 +11180,6 @@ pub unsafe fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); vmovl_s32(a) } - #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"] #[doc = "## Safety"] @@ -11761,7 +11192,6 @@ pub unsafe fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); vmovl_u8(a) } - #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"] #[doc = "## Safety"] @@ -11774,7 +11204,6 @@ pub unsafe fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); vmovl_u16(a) } - #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"] #[doc = "## Safety"] @@ -11787,7 +11216,6 @@ pub unsafe fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); vmovl_u32(a) } - #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"] #[doc = "## Safety"] @@ -11800,7 +11228,6 @@ pub unsafe fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { let c: int8x8_t = simd_cast(b); simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } - #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"] #[doc = "## Safety"] @@ -11813,7 +11240,6 @@ pub unsafe fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { let c: int16x4_t = simd_cast(b); simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"] #[doc = "## Safety"] @@ -11826,7 +11252,6 @@ pub unsafe fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { let c: int32x2_t = simd_cast(b); simd_shuffle!(a, c, [0, 1, 2, 3]) } - #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"] #[doc = "## Safety"] @@ -11839,7 +11264,6 @@ pub unsafe fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { let c: uint8x8_t = simd_cast(b); simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } - #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"] #[doc = "## Safety"] @@ -11852,7 +11276,6 @@ pub unsafe fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { let c: uint16x4_t = simd_cast(b); simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"] #[doc = "## Safety"] @@ -11865,7 +11288,6 @@ pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { let c: uint32x2_t = simd_cast(b); simd_shuffle!(a, c, [0, 1, 2, 3]) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"] #[doc = "## Safety"] @@ -11877,7 +11299,6 @@ pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"] #[doc = "## Safety"] @@ -11889,7 +11310,6 @@ pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_mul(a, b) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"] #[doc = "## Safety"] @@ -11903,7 +11323,6 @@ pub unsafe fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> static_assert!(LANE == 0); simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"] #[doc = "## Safety"] @@ -11917,7 +11336,6 @@ pub unsafe fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> static_assert_uimm_bits!(LANE, 1); simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"] #[doc = "## Safety"] @@ -11929,7 +11347,6 @@ pub unsafe fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { simd_mul(a, vdup_n_f64(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"] #[doc = "## Safety"] @@ -11941,7 +11358,6 @@ pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { pub unsafe fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { simd_mul(a, vdupq_n_f64(b)) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"] #[doc = "## Safety"] @@ -11956,7 +11372,6 @@ pub unsafe fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { let b: f64 = simd_extract!(b, LANE as u32); a * b } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"] #[doc = "## Safety"] @@ -11986,7 +11401,6 @@ pub unsafe fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) - ), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"] #[doc = "## Safety"] @@ -12016,7 +11430,6 @@ pub unsafe fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) ), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"] #[doc = "## Safety"] @@ -12033,7 +11446,6 @@ pub unsafe fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"] #[doc = "## Safety"] @@ -12050,7 +11462,6 @@ pub unsafe fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"] #[doc = "## Safety"] @@ -12080,7 +11491,6 @@ pub unsafe fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) ), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"] #[doc = "## Safety"] @@ -12110,7 +11520,6 @@ pub unsafe fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t ), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"] #[doc = "## Safety"] @@ -12127,7 +11536,6 @@ pub unsafe fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"] #[doc = "## Safety"] @@ -12144,7 +11552,6 @@ pub unsafe fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"] #[doc = "## Safety"] @@ -12156,7 +11563,6 @@ pub unsafe fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { vmull_high_s16(a, vdupq_n_s16(b)) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"] #[doc = "## Safety"] @@ -12168,7 +11574,6 @@ pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { vmull_high_s32(a, vdupq_n_s32(b)) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"] #[doc = "## Safety"] @@ -12180,7 +11585,6 @@ pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { vmull_high_u16(a, vdupq_n_u16(b)) } - #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"] #[doc = "## Safety"] @@ -12192,7 +11596,6 @@ pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { vmull_high_u32(a, vdupq_n_u32(b)) } - #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"] #[doc = "## Safety"] @@ -12204,7 +11607,6 @@ pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) } - #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"] #[doc = "## Safety"] @@ -12218,7 +11620,6 @@ pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); vmull_p8(a, b) } - #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"] #[doc = "## Safety"] @@ -12232,7 +11633,6 @@ pub unsafe fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); vmull_s8(a, b) } - #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"] #[doc = "## Safety"] @@ -12246,7 +11646,6 @@ pub unsafe fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); vmull_s16(a, b) } - #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"] #[doc = "## Safety"] @@ -12260,7 +11659,6 @@ pub unsafe fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); vmull_s32(a, b) } - #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"] #[doc = "## Safety"] @@ -12274,7 +11672,6 @@ pub unsafe fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); vmull_u8(a, b) } - #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"] #[doc = "## Safety"] @@ -12288,7 +11685,6 @@ pub unsafe fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); vmull_u16(a, b) } - #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"] #[doc = "## Safety"] @@ -12302,7 +11698,6 @@ pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); vmull_u32(a, b) } - #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"] #[doc = "## Safety"] @@ -12321,7 +11716,6 @@ pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { } transmute(_vmull_p64(a, b)) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"] #[doc = "## Safety"] @@ -12335,7 +11729,6 @@ pub unsafe fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> static_assert!(LANE == 0); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"] #[doc = "## Safety"] @@ -12349,7 +11742,6 @@ pub unsafe fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) - static_assert_uimm_bits!(LANE, 1); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"] #[doc = "## Safety"] @@ -12364,7 +11756,6 @@ pub unsafe fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { let b: f32 = simd_extract!(b, LANE as u32); a * b } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"] #[doc = "## Safety"] @@ -12379,7 +11770,6 @@ pub unsafe fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { let b: f32 = simd_extract!(b, LANE as u32); a * b } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"] #[doc = "## Safety"] @@ -12394,7 +11784,6 @@ pub unsafe fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { let b: f64 = simd_extract!(b, LANE as u32); a * b } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"] #[doc = "## Safety"] @@ -12413,7 +11802,6 @@ pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vmulx_f32(a, b) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"] #[doc = "## Safety"] @@ -12432,7 +11820,6 @@ pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vmulxq_f32(a, b) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"] #[doc = "## Safety"] @@ -12451,7 +11838,6 @@ pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vmulx_f64(a, b) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"] #[doc = "## Safety"] @@ -12470,7 +11856,6 @@ pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vmulxq_f64(a, b) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"] #[doc = "## Safety"] @@ -12484,7 +11869,6 @@ pub unsafe fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> static_assert_uimm_bits!(LANE, 1); vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"] #[doc = "## Safety"] @@ -12498,7 +11882,6 @@ pub unsafe fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) - static_assert_uimm_bits!(LANE, 2); vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"] #[doc = "## Safety"] @@ -12515,7 +11898,6 @@ pub unsafe fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"] #[doc = "## Safety"] @@ -12532,7 +11914,6 @@ pub unsafe fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"] #[doc = "## Safety"] @@ -12546,7 +11927,6 @@ pub unsafe fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) static_assert_uimm_bits!(LANE, 1); vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"] #[doc = "## Safety"] @@ -12560,7 +11940,6 @@ pub unsafe fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> static_assert!(LANE == 0); vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"] #[doc = "## Safety"] @@ -12574,7 +11953,6 @@ pub unsafe fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) - static_assert_uimm_bits!(LANE, 1); vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"] #[doc = "## Safety"] @@ -12593,7 +11971,6 @@ pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { } _vmulxd_f64(a, b) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"] #[doc = "## Safety"] @@ -12612,7 +11989,6 @@ pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { } _vmulxs_f32(a, b) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"] #[doc = "## Safety"] @@ -12626,7 +12002,6 @@ pub unsafe fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); vmulxd_f64(a, simd_extract!(b, LANE as u32)) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"] #[doc = "## Safety"] @@ -12640,7 +12015,6 @@ pub unsafe fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); vmulxd_f64(a, simd_extract!(b, LANE as u32)) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"] #[doc = "## Safety"] @@ -12654,7 +12028,6 @@ pub unsafe fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); vmulxs_f32(a, simd_extract!(b, LANE as u32)) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"] #[doc = "## Safety"] @@ -12668,7 +12041,6 @@ pub unsafe fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); vmulxs_f32(a, simd_extract!(b, LANE as u32)) } - #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"] #[doc = "## Safety"] @@ -12682,7 +12054,6 @@ pub unsafe fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) - static_assert!(LANE == 0); vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"] #[doc = "## Safety"] @@ -12694,7 +12065,6 @@ pub unsafe fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) - pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"] #[doc = "## Safety"] @@ -12706,7 +12076,6 @@ pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"] #[doc = "## Safety"] @@ -12718,7 +12087,6 @@ pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"] #[doc = "## Safety"] @@ -12730,7 +12098,6 @@ pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"] #[doc = "## Safety"] @@ -12742,7 +12109,6 @@ pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { pub unsafe fn vnegd_s64(a: i64) -> i64 { a.wrapping_neg() } - #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"] #[doc = "## Safety"] @@ -12756,7 +12122,6 @@ pub unsafe fn vpaddd_f64(a: float64x2_t) -> f64 { let a2: f64 = simd_extract!(a, 1); a1 + a2 } - #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"] #[doc = "## Safety"] @@ -12770,7 +12135,6 @@ pub unsafe fn vpadds_f32(a: float32x2_t) -> f32 { let a2: f32 = simd_extract!(a, 1); a1 + a2 } - #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] #[doc = "## Safety"] @@ -12789,7 +12153,6 @@ pub unsafe fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vpaddq_f32(a, b) } - #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] #[doc = "## Safety"] @@ -12808,7 +12171,6 @@ pub unsafe fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vpaddq_f64(a, b) } - #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] #[doc = "## Safety"] @@ -12827,7 +12189,6 @@ pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vpmaxnm_f32(a, b) } - #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] #[doc = "## Safety"] @@ -12846,7 +12207,6 @@ pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vpmaxnmq_f32(a, b) } - #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] #[doc = "## Safety"] @@ -12865,7 +12225,6 @@ pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vpmaxnmq_f64(a, b) } - #[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] #[doc = "## Safety"] @@ -12884,7 +12243,6 @@ pub unsafe fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { } _vpmaxnmqd_f64(a) } - #[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] #[doc = "## Safety"] @@ -12903,7 +12261,6 @@ pub unsafe fn vpmaxnms_f32(a: float32x2_t) -> f32 { } _vpmaxnms_f32(a) } - #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"] #[doc = "## Safety"] @@ -12922,7 +12279,6 @@ pub unsafe fn vpmaxqd_f64(a: float64x2_t) -> f64 { } _vpmaxqd_f64(a) } - #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"] #[doc = "## Safety"] @@ -12941,7 +12297,6 @@ pub unsafe fn vpmaxs_f32(a: float32x2_t) -> f32 { } _vpmaxs_f32(a) } - #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] #[doc = "## Safety"] @@ -12960,7 +12315,6 @@ pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vpminnm_f32(a, b) } - #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] #[doc = "## Safety"] @@ -12979,7 +12333,6 @@ pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vpminnmq_f32(a, b) } - #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] #[doc = "## Safety"] @@ -12998,7 +12351,6 @@ pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vpminnmq_f64(a, b) } - #[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] #[doc = "## Safety"] @@ -13017,7 +12369,6 @@ pub unsafe fn vpminnmqd_f64(a: float64x2_t) -> f64 { } _vpminnmqd_f64(a) } - #[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] #[doc = "## Safety"] @@ -13036,7 +12387,6 @@ pub unsafe fn vpminnms_f32(a: float32x2_t) -> f32 { } _vpminnms_f32(a) } - #[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] #[doc = "## Safety"] @@ -13055,7 +12405,6 @@ pub unsafe fn vpminqd_f64(a: float64x2_t) -> f64 { } _vpminqd_f64(a) } - #[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] #[doc = "## Safety"] @@ -13074,7 +12423,6 @@ pub unsafe fn vpmins_f32(a: float32x2_t) -> f32 { } _vpmins_f32(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"] #[doc = "## Safety"] @@ -13093,7 +12441,6 @@ pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { } _vqabs_s64(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"] #[doc = "## Safety"] @@ -13112,7 +12459,6 @@ pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { } _vqabsq_s64(a) } - #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"] #[doc = "## Safety"] @@ -13124,7 +12470,6 @@ pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { pub unsafe fn vqabsb_s8(a: i8) -> i8 { simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) } - #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"] #[doc = "## Safety"] @@ -13136,7 +12481,6 @@ pub unsafe fn vqabsb_s8(a: i8) -> i8 { pub unsafe fn vqabsh_s16(a: i16) -> i16 { simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) } - #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"] #[doc = "## Safety"] @@ -13155,7 +12499,6 @@ pub unsafe fn vqabss_s32(a: i32) -> i32 { } _vqabss_s32(a) } - #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"] #[doc = "## Safety"] @@ -13174,7 +12517,6 @@ pub unsafe fn vqabsd_s64(a: i64) -> i64 { } _vqabsd_s64(a) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"] #[doc = "## Safety"] @@ -13188,7 +12530,6 @@ pub unsafe fn vqaddb_s8(a: i8, b: i8) -> i8 { let b: int8x8_t = vdup_n_s8(b); simd_extract!(vqadd_s8(a, b), 0) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"] #[doc = "## Safety"] @@ -13202,7 +12543,6 @@ pub unsafe fn vqaddh_s16(a: i16, b: i16) -> i16 { let b: int16x4_t = vdup_n_s16(b); simd_extract!(vqadd_s16(a, b), 0) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"] #[doc = "## Safety"] @@ -13216,7 +12556,6 @@ pub unsafe fn vqaddb_u8(a: u8, b: u8) -> u8 { let b: uint8x8_t = vdup_n_u8(b); simd_extract!(vqadd_u8(a, b), 0) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"] #[doc = "## Safety"] @@ -13230,7 +12569,6 @@ pub unsafe fn vqaddh_u16(a: u16, b: u16) -> u16 { let b: uint16x4_t = vdup_n_u16(b); simd_extract!(vqadd_u16(a, b), 0) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"] #[doc = "## Safety"] @@ -13249,7 +12587,6 @@ pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { } _vqadds_s32(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"] #[doc = "## Safety"] @@ -13268,7 +12605,6 @@ pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { } _vqaddd_s64(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"] #[doc = "## Safety"] @@ -13287,7 +12623,6 @@ pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { } _vqadds_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"] #[doc = "## Safety"] @@ -13306,7 +12641,6 @@ pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { } _vqaddd_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"] #[doc = "## Safety"] @@ -13324,7 +12658,6 @@ pub unsafe fn vqdmlal_high_lane_s16( static_assert_uimm_bits!(N, 2); vqaddq_s32(a, vqdmull_high_lane_s16::(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"] #[doc = "## Safety"] @@ -13342,7 +12675,6 @@ pub unsafe fn vqdmlal_high_laneq_s16( static_assert_uimm_bits!(N, 3); vqaddq_s32(a, vqdmull_high_laneq_s16::(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"] #[doc = "## Safety"] @@ -13360,7 +12692,6 @@ pub unsafe fn vqdmlal_high_lane_s32( static_assert_uimm_bits!(N, 1); vqaddq_s64(a, vqdmull_high_lane_s32::(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"] #[doc = "## Safety"] @@ -13378,7 +12709,6 @@ pub unsafe fn vqdmlal_high_laneq_s32( static_assert_uimm_bits!(N, 2); vqaddq_s64(a, vqdmull_high_laneq_s32::(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"] #[doc = "## Safety"] @@ -13390,7 +12720,6 @@ pub unsafe fn vqdmlal_high_laneq_s32( pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqaddq_s32(a, vqdmull_high_n_s16(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"] #[doc = "## Safety"] @@ -13402,7 +12731,6 @@ pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_ pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqaddq_s32(a, vqdmull_high_s16(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"] #[doc = "## Safety"] @@ -13414,7 +12742,6 @@ pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int3 pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqaddq_s64(a, vqdmull_high_n_s32(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"] #[doc = "## Safety"] @@ -13426,7 +12753,6 @@ pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_ pub unsafe fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqaddq_s64(a, vqdmull_high_s32(b, c)) } - #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"] #[doc = "## Safety"] @@ -13444,7 +12770,6 @@ pub unsafe fn vqdmlal_laneq_s16( static_assert_uimm_bits!(N, 3); vqaddq_s32(a, vqdmull_laneq_s16::(b, c)) } - #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"] #[doc = "## Safety"] @@ -13462,7 +12787,6 @@ pub unsafe fn vqdmlal_laneq_s32( static_assert_uimm_bits!(N, 2); vqaddq_s64(a, vqdmull_laneq_s32::(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"] #[doc = "## Safety"] @@ -13476,7 +12800,6 @@ pub unsafe fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) - static_assert_uimm_bits!(LANE, 2); vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"] #[doc = "## Safety"] @@ -13490,7 +12813,6 @@ pub unsafe fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) static_assert_uimm_bits!(LANE, 3); vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"] #[doc = "## Safety"] @@ -13504,7 +12826,6 @@ pub unsafe fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) - static_assert_uimm_bits!(LANE, 1); vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"] #[doc = "## Safety"] @@ -13518,7 +12839,6 @@ pub unsafe fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) static_assert_uimm_bits!(LANE, 2); vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"] #[doc = "## Safety"] @@ -13531,7 +12851,6 @@ pub unsafe fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); vqadds_s32(a, simd_extract!(x, 0)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"] #[doc = "## Safety"] @@ -13544,7 +12863,6 @@ pub unsafe fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c)); x as i64 } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"] #[doc = "## Safety"] @@ -13562,7 +12880,6 @@ pub unsafe fn vqdmlsl_high_lane_s16( static_assert_uimm_bits!(N, 2); vqsubq_s32(a, vqdmull_high_lane_s16::(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"] #[doc = "## Safety"] @@ -13580,7 +12897,6 @@ pub unsafe fn vqdmlsl_high_laneq_s16( static_assert_uimm_bits!(N, 3); vqsubq_s32(a, vqdmull_high_laneq_s16::(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"] #[doc = "## Safety"] @@ -13598,7 +12914,6 @@ pub unsafe fn vqdmlsl_high_lane_s32( static_assert_uimm_bits!(N, 1); vqsubq_s64(a, vqdmull_high_lane_s32::(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"] #[doc = "## Safety"] @@ -13616,7 +12931,6 @@ pub unsafe fn vqdmlsl_high_laneq_s32( static_assert_uimm_bits!(N, 2); vqsubq_s64(a, vqdmull_high_laneq_s32::(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"] #[doc = "## Safety"] @@ -13628,7 +12942,6 @@ pub unsafe fn vqdmlsl_high_laneq_s32( pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqsubq_s32(a, vqdmull_high_n_s16(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"] #[doc = "## Safety"] @@ -13640,7 +12953,6 @@ pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_ pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqsubq_s32(a, vqdmull_high_s16(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"] #[doc = "## Safety"] @@ -13652,7 +12964,6 @@ pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int3 pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqsubq_s64(a, vqdmull_high_n_s32(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"] #[doc = "## Safety"] @@ -13664,7 +12975,6 @@ pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_ pub unsafe fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqsubq_s64(a, vqdmull_high_s32(b, c)) } - #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"] #[doc = "## Safety"] @@ -13682,7 +12992,6 @@ pub unsafe fn vqdmlsl_laneq_s16( static_assert_uimm_bits!(N, 3); vqsubq_s32(a, vqdmull_laneq_s16::(b, c)) } - #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"] #[doc = "## Safety"] @@ -13700,7 +13009,6 @@ pub unsafe fn vqdmlsl_laneq_s32( static_assert_uimm_bits!(N, 2); vqsubq_s64(a, vqdmull_laneq_s32::(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"] #[doc = "## Safety"] @@ -13714,7 +13022,6 @@ pub unsafe fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) - static_assert_uimm_bits!(LANE, 2); vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"] #[doc = "## Safety"] @@ -13728,7 +13035,6 @@ pub unsafe fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) static_assert_uimm_bits!(LANE, 3); vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"] #[doc = "## Safety"] @@ -13742,7 +13048,6 @@ pub unsafe fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) - static_assert_uimm_bits!(LANE, 1); vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"] #[doc = "## Safety"] @@ -13756,7 +13061,6 @@ pub unsafe fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) static_assert_uimm_bits!(LANE, 2); vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"] #[doc = "## Safety"] @@ -13769,7 +13073,6 @@ pub unsafe fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); vqsubs_s32(a, simd_extract!(x, 0)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"] #[doc = "## Safety"] @@ -13782,7 +13085,6 @@ pub unsafe fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c)); x as i64 } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"] #[doc = "## Safety"] @@ -13796,7 +13098,6 @@ pub unsafe fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> i static_assert_uimm_bits!(LANE, 2); vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"] #[doc = "## Safety"] @@ -13810,7 +13111,6 @@ pub unsafe fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> static_assert_uimm_bits!(LANE, 2); vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"] #[doc = "## Safety"] @@ -13824,7 +13124,6 @@ pub unsafe fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> i static_assert_uimm_bits!(LANE, 1); vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"] #[doc = "## Safety"] @@ -13838,7 +13137,6 @@ pub unsafe fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> static_assert_uimm_bits!(LANE, 1); vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"] #[doc = "## Safety"] @@ -13853,7 +13151,6 @@ pub unsafe fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { let b: i16 = simd_extract!(b, N as u32); vqdmulhh_s16(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"] #[doc = "## Safety"] @@ -13868,7 +13165,6 @@ pub unsafe fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { let b: i16 = simd_extract!(b, N as u32); vqdmulhh_s16(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"] #[doc = "## Safety"] @@ -13882,7 +13178,6 @@ pub unsafe fn vqdmulhh_s16(a: i16, b: i16) -> i16 { let b: int16x4_t = vdup_n_s16(b); simd_extract!(vqdmulh_s16(a, b), 0) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"] #[doc = "## Safety"] @@ -13896,7 +13191,6 @@ pub unsafe fn vqdmulhs_s32(a: i32, b: i32) -> i32 { let b: int32x2_t = vdup_n_s32(b); simd_extract!(vqdmulh_s32(a, b), 0) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"] #[doc = "## Safety"] @@ -13911,7 +13205,6 @@ pub unsafe fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { let b: i32 = simd_extract!(b, N as u32); vqdmulhs_s32(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"] #[doc = "## Safety"] @@ -13926,7 +13219,6 @@ pub unsafe fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { let b: i32 = simd_extract!(b, N as u32); vqdmulhs_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"] #[doc = "## Safety"] @@ -13942,7 +13234,6 @@ pub unsafe fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); vqdmull_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"] #[doc = "## Safety"] @@ -13958,7 +13249,6 @@ pub unsafe fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); vqdmull_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"] #[doc = "## Safety"] @@ -13974,7 +13264,6 @@ pub unsafe fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); vqdmull_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"] #[doc = "## Safety"] @@ -13990,7 +13279,6 @@ pub unsafe fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); vqdmull_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"] #[doc = "## Safety"] @@ -14004,7 +13292,6 @@ pub unsafe fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { let b: int16x4_t = vdup_n_s16(b); vqdmull_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"] #[doc = "## Safety"] @@ -14018,7 +13305,6 @@ pub unsafe fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { let b: int32x2_t = vdup_n_s32(b); vqdmull_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"] #[doc = "## Safety"] @@ -14032,7 +13318,6 @@ pub unsafe fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); vqdmull_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"] #[doc = "## Safety"] @@ -14046,7 +13331,6 @@ pub unsafe fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); vqdmull_s32(a, b) } - #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"] #[doc = "## Safety"] @@ -14061,7 +13345,6 @@ pub unsafe fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); vqdmull_s16(a, b) } - #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"] #[doc = "## Safety"] @@ -14076,7 +13359,6 @@ pub unsafe fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); vqdmull_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"] #[doc = "## Safety"] @@ -14091,7 +13373,6 @@ pub unsafe fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { let b: i16 = simd_extract!(b, N as u32); vqdmullh_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"] #[doc = "## Safety"] @@ -14106,7 +13387,6 @@ pub unsafe fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { let b: i32 = simd_extract!(b, N as u32); vqdmulls_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"] #[doc = "## Safety"] @@ -14121,7 +13401,6 @@ pub unsafe fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { let b: i16 = simd_extract!(b, N as u32); vqdmullh_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"] #[doc = "## Safety"] @@ -14135,7 +13414,6 @@ pub unsafe fn vqdmullh_s16(a: i16, b: i16) -> i32 { let b: int16x4_t = vdup_n_s16(b); simd_extract!(vqdmull_s16(a, b), 0) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"] #[doc = "## Safety"] @@ -14150,7 +13428,6 @@ pub unsafe fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { let b: i32 = simd_extract!(b, N as u32); vqdmulls_s32(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"] #[doc = "## Safety"] @@ -14169,7 +13446,6 @@ pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { } _vqdmulls_s32(a, b) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"] #[doc = "## Safety"] @@ -14185,7 +13461,6 @@ pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"] #[doc = "## Safety"] @@ -14197,7 +13472,6 @@ pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"] #[doc = "## Safety"] @@ -14209,7 +13483,6 @@ pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { pub unsafe fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"] #[doc = "## Safety"] @@ -14225,7 +13498,6 @@ pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"] #[doc = "## Safety"] @@ -14237,7 +13509,6 @@ pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"] #[doc = "## Safety"] @@ -14249,7 +13520,6 @@ pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { pub unsafe fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) } - #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"] #[doc = "## Safety"] @@ -14268,7 +13538,6 @@ pub unsafe fn vqmovnd_s64(a: i64) -> i32 { } _vqmovnd_s64(a) } - #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"] #[doc = "## Safety"] @@ -14287,7 +13556,6 @@ pub unsafe fn vqmovnd_u64(a: u64) -> u32 { } _vqmovnd_u64(a.as_signed()).as_unsigned() } - #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"] #[doc = "## Safety"] @@ -14299,7 +13567,6 @@ pub unsafe fn vqmovnd_u64(a: u64) -> u32 { pub unsafe fn vqmovnh_s16(a: i16) -> i8 { simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) } - #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"] #[doc = "## Safety"] @@ -14311,7 +13578,6 @@ pub unsafe fn vqmovnh_s16(a: i16) -> i8 { pub unsafe fn vqmovns_s32(a: i32) -> i16 { simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) } - #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"] #[doc = "## Safety"] @@ -14323,7 +13589,6 @@ pub unsafe fn vqmovns_s32(a: i32) -> i16 { pub unsafe fn vqmovnh_u16(a: u16) -> u8 { simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) } - #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"] #[doc = "## Safety"] @@ -14335,7 +13600,6 @@ pub unsafe fn vqmovnh_u16(a: u16) -> u8 { pub unsafe fn vqmovns_u32(a: u32) -> u16 { simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"] #[doc = "## Safety"] @@ -14351,7 +13615,6 @@ pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"] #[doc = "## Safety"] @@ -14363,7 +13626,6 @@ pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"] #[doc = "## Safety"] @@ -14375,7 +13637,6 @@ pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"] #[doc = "## Safety"] @@ -14387,7 +13648,6 @@ pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { pub unsafe fn vqmovunh_s16(a: i16) -> u8 { simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"] #[doc = "## Safety"] @@ -14399,7 +13659,6 @@ pub unsafe fn vqmovunh_s16(a: i16) -> u8 { pub unsafe fn vqmovuns_s32(a: i32) -> u16 { simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"] #[doc = "## Safety"] @@ -14411,7 +13670,6 @@ pub unsafe fn vqmovuns_s32(a: i32) -> u16 { pub unsafe fn vqmovund_s64(a: i64) -> u32 { simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"] #[doc = "## Safety"] @@ -14430,7 +13688,6 @@ pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { } _vqneg_s64(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"] #[doc = "## Safety"] @@ -14449,7 +13706,6 @@ pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { } _vqnegq_s64(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"] #[doc = "## Safety"] @@ -14461,7 +13717,6 @@ pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { pub unsafe fn vqnegb_s8(a: i8) -> i8 { simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"] #[doc = "## Safety"] @@ -14473,7 +13728,6 @@ pub unsafe fn vqnegb_s8(a: i8) -> i8 { pub unsafe fn vqnegh_s16(a: i16) -> i16 { simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"] #[doc = "## Safety"] @@ -14485,7 +13739,6 @@ pub unsafe fn vqnegh_s16(a: i16) -> i16 { pub unsafe fn vqnegs_s32(a: i32) -> i32 { simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"] #[doc = "## Safety"] @@ -14497,7 +13750,6 @@ pub unsafe fn vqnegs_s32(a: i32) -> i32 { pub unsafe fn vqnegd_s64(a: i64) -> i64 { simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"] #[doc = "## Safety"] @@ -14516,7 +13768,6 @@ pub unsafe fn vqrdmlah_lane_s16( let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlah_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"] #[doc = "## Safety"] @@ -14535,7 +13786,6 @@ pub unsafe fn vqrdmlah_lane_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vqrdmlah_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"] #[doc = "## Safety"] @@ -14554,7 +13804,6 @@ pub unsafe fn vqrdmlah_laneq_s16( let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlah_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"] #[doc = "## Safety"] @@ -14573,7 +13822,6 @@ pub unsafe fn vqrdmlah_laneq_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vqrdmlah_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"] #[doc = "## Safety"] @@ -14605,7 +13853,6 @@ pub unsafe fn vqrdmlahq_lane_s16( ); vqrdmlahq_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"] #[doc = "## Safety"] @@ -14624,7 +13871,6 @@ pub unsafe fn vqrdmlahq_lane_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlahq_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"] #[doc = "## Safety"] @@ -14656,7 +13902,6 @@ pub unsafe fn vqrdmlahq_laneq_s16( ); vqrdmlahq_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"] #[doc = "## Safety"] @@ -14675,7 +13920,6 @@ pub unsafe fn vqrdmlahq_laneq_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlahq_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"] #[doc = "## Safety"] @@ -14694,7 +13938,6 @@ pub unsafe fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_ } _vqrdmlah_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"] #[doc = "## Safety"] @@ -14713,7 +13956,6 @@ pub unsafe fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8 } _vqrdmlahq_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"] #[doc = "## Safety"] @@ -14732,7 +13974,6 @@ pub unsafe fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_ } _vqrdmlah_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"] #[doc = "## Safety"] @@ -14751,7 +13992,6 @@ pub unsafe fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4 } _vqrdmlahq_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"] #[doc = "## Safety"] @@ -14765,7 +14005,6 @@ pub unsafe fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) static_assert_uimm_bits!(LANE, 2); vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"] #[doc = "## Safety"] @@ -14779,7 +14018,6 @@ pub unsafe fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) static_assert_uimm_bits!(LANE, 3); vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"] #[doc = "## Safety"] @@ -14793,7 +14031,6 @@ pub unsafe fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) static_assert_uimm_bits!(LANE, 1); vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"] #[doc = "## Safety"] @@ -14807,7 +14044,6 @@ pub unsafe fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) static_assert_uimm_bits!(LANE, 2); vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"] #[doc = "## Safety"] @@ -14822,7 +14058,6 @@ pub unsafe fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { let c: int16x4_t = vdup_n_s16(c); simd_extract!(vqrdmlah_s16(a, b, c), 0) } - #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"] #[doc = "## Safety"] @@ -14837,7 +14072,6 @@ pub unsafe fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { let c: int32x2_t = vdup_n_s32(c); simd_extract!(vqrdmlah_s32(a, b, c), 0) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"] #[doc = "## Safety"] @@ -14856,7 +14090,6 @@ pub unsafe fn vqrdmlsh_lane_s16( let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlsh_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"] #[doc = "## Safety"] @@ -14875,7 +14108,6 @@ pub unsafe fn vqrdmlsh_lane_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vqrdmlsh_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"] #[doc = "## Safety"] @@ -14894,7 +14126,6 @@ pub unsafe fn vqrdmlsh_laneq_s16( let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlsh_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"] #[doc = "## Safety"] @@ -14913,7 +14144,6 @@ pub unsafe fn vqrdmlsh_laneq_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vqrdmlsh_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"] #[doc = "## Safety"] @@ -14945,7 +14175,6 @@ pub unsafe fn vqrdmlshq_lane_s16( ); vqrdmlshq_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"] #[doc = "## Safety"] @@ -14964,7 +14193,6 @@ pub unsafe fn vqrdmlshq_lane_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlshq_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"] #[doc = "## Safety"] @@ -14996,7 +14224,6 @@ pub unsafe fn vqrdmlshq_laneq_s16( ); vqrdmlshq_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"] #[doc = "## Safety"] @@ -15015,7 +14242,6 @@ pub unsafe fn vqrdmlshq_laneq_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmlshq_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"] #[doc = "## Safety"] @@ -15034,7 +14260,6 @@ pub unsafe fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_ } _vqrdmlsh_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"] #[doc = "## Safety"] @@ -15053,7 +14278,6 @@ pub unsafe fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8 } _vqrdmlshq_s16(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"] #[doc = "## Safety"] @@ -15072,7 +14296,6 @@ pub unsafe fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_ } _vqrdmlsh_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"] #[doc = "## Safety"] @@ -15091,7 +14314,6 @@ pub unsafe fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4 } _vqrdmlshq_s32(a, b, c) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"] #[doc = "## Safety"] @@ -15105,7 +14327,6 @@ pub unsafe fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) static_assert_uimm_bits!(LANE, 2); vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"] #[doc = "## Safety"] @@ -15119,7 +14340,6 @@ pub unsafe fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) static_assert_uimm_bits!(LANE, 3); vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"] #[doc = "## Safety"] @@ -15133,7 +14353,6 @@ pub unsafe fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) static_assert_uimm_bits!(LANE, 1); vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"] #[doc = "## Safety"] @@ -15147,7 +14366,6 @@ pub unsafe fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) static_assert_uimm_bits!(LANE, 2); vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"] #[doc = "## Safety"] @@ -15162,7 +14380,6 @@ pub unsafe fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { let c: int16x4_t = vdup_n_s16(c); simd_extract!(vqrdmlsh_s16(a, b, c), 0) } - #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"] #[doc = "## Safety"] @@ -15177,7 +14394,6 @@ pub unsafe fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { let c: int32x2_t = vdup_n_s32(c); simd_extract!(vqrdmlsh_s32(a, b, c), 0) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"] #[doc = "## Safety"] @@ -15191,7 +14407,6 @@ pub unsafe fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"] #[doc = "## Safety"] @@ -15205,7 +14420,6 @@ pub unsafe fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 static_assert_uimm_bits!(LANE, 3); vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"] #[doc = "## Safety"] @@ -15219,7 +14433,6 @@ pub unsafe fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"] #[doc = "## Safety"] @@ -15233,7 +14446,6 @@ pub unsafe fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 static_assert_uimm_bits!(LANE, 2); vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"] #[doc = "## Safety"] @@ -15245,7 +14457,6 @@ pub unsafe fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"] #[doc = "## Safety"] @@ -15257,7 +14468,6 @@ pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { pub unsafe fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"] #[doc = "## Safety"] @@ -15271,7 +14481,6 @@ pub unsafe fn vqrshlb_s8(a: i8, b: i8) -> i8 { let b: int8x8_t = vdup_n_s8(b); simd_extract!(vqrshl_s8(a, b), 0) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"] #[doc = "## Safety"] @@ -15285,7 +14494,6 @@ pub unsafe fn vqrshlh_s16(a: i16, b: i16) -> i16 { let b: int16x4_t = vdup_n_s16(b); simd_extract!(vqrshl_s16(a, b), 0) } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"] #[doc = "## Safety"] @@ -15299,7 +14507,6 @@ pub unsafe fn vqrshlb_u8(a: u8, b: i8) -> u8 { let b: int8x8_t = vdup_n_s8(b); simd_extract!(vqrshl_u8(a, b), 0) } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"] #[doc = "## Safety"] @@ -15313,7 +14520,6 @@ pub unsafe fn vqrshlh_u16(a: u16, b: i16) -> u16 { let b: int16x4_t = vdup_n_s16(b); simd_extract!(vqrshl_u16(a, b), 0) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"] #[doc = "## Safety"] @@ -15332,7 +14538,6 @@ pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { } _vqrshld_s64(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"] #[doc = "## Safety"] @@ -15351,7 +14556,6 @@ pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { } _vqrshls_s32(a, b) } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"] #[doc = "## Safety"] @@ -15370,7 +14574,6 @@ pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { } _vqrshls_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"] #[doc = "## Safety"] @@ -15389,7 +14592,6 @@ pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { } _vqrshld_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"] #[doc = "## Safety"] @@ -15407,7 +14609,6 @@ pub unsafe fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"] #[doc = "## Safety"] @@ -15421,7 +14622,6 @@ pub unsafe fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> in static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"] #[doc = "## Safety"] @@ -15435,7 +14635,6 @@ pub unsafe fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> in static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) } - #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"] #[doc = "## Safety"] @@ -15453,7 +14652,6 @@ pub unsafe fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> u [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"] #[doc = "## Safety"] @@ -15467,7 +14665,6 @@ pub unsafe fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"] #[doc = "## Safety"] @@ -15481,7 +14678,6 @@ pub unsafe fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) } - #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"] #[doc = "## Safety"] @@ -15496,7 +14692,6 @@ pub unsafe fn vqrshrnd_n_u64(a: u64) -> u32 { let a: uint64x2_t = vdupq_n_u64(a); simd_extract!(vqrshrn_n_u64::(a), 0) } - #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"] #[doc = "## Safety"] @@ -15511,7 +14706,6 @@ pub unsafe fn vqrshrnh_n_u16(a: u16) -> u8 { let a: uint16x8_t = vdupq_n_u16(a); simd_extract!(vqrshrn_n_u16::(a), 0) } - #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"] #[doc = "## Safety"] @@ -15526,7 +14720,6 @@ pub unsafe fn vqrshrns_n_u32(a: u32) -> u16 { let a: uint32x4_t = vdupq_n_u32(a); simd_extract!(vqrshrn_n_u32::(a), 0) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"] #[doc = "## Safety"] @@ -15541,7 +14734,6 @@ pub unsafe fn vqrshrnh_n_s16(a: i16) -> i8 { let a: int16x8_t = vdupq_n_s16(a); simd_extract!(vqrshrn_n_s16::(a), 0) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"] #[doc = "## Safety"] @@ -15556,7 +14748,6 @@ pub unsafe fn vqrshrns_n_s32(a: i32) -> i16 { let a: int32x4_t = vdupq_n_s32(a); simd_extract!(vqrshrn_n_s32::(a), 0) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"] #[doc = "## Safety"] @@ -15571,7 +14762,6 @@ pub unsafe fn vqrshrnd_n_s64(a: i64) -> i32 { let a: int64x2_t = vdupq_n_s64(a); simd_extract!(vqrshrn_n_s64::(a), 0) } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"] #[doc = "## Safety"] @@ -15589,7 +14779,6 @@ pub unsafe fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> u [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"] #[doc = "## Safety"] @@ -15603,7 +14792,6 @@ pub unsafe fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"] #[doc = "## Safety"] @@ -15617,7 +14805,6 @@ pub unsafe fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"] #[doc = "## Safety"] @@ -15632,7 +14819,6 @@ pub unsafe fn vqrshrund_n_s64(a: i64) -> u32 { let a: int64x2_t = vdupq_n_s64(a); simd_extract!(vqrshrun_n_s64::(a), 0) } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"] #[doc = "## Safety"] @@ -15647,7 +14833,6 @@ pub unsafe fn vqrshrunh_n_s16(a: i16) -> u8 { let a: int16x8_t = vdupq_n_s16(a); simd_extract!(vqrshrun_n_s16::(a), 0) } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"] #[doc = "## Safety"] @@ -15662,7 +14847,6 @@ pub unsafe fn vqrshruns_n_s32(a: i32) -> u16 { let a: int32x4_t = vdupq_n_s32(a); simd_extract!(vqrshrun_n_s32::(a), 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"] #[doc = "## Safety"] @@ -15676,7 +14860,6 @@ pub unsafe fn vqshlb_n_s8(a: i8) -> i8 { static_assert_uimm_bits!(N, 3); simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"] #[doc = "## Safety"] @@ -15690,7 +14873,6 @@ pub unsafe fn vqshld_n_s64(a: i64) -> i64 { static_assert_uimm_bits!(N, 6); simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"] #[doc = "## Safety"] @@ -15704,7 +14886,6 @@ pub unsafe fn vqshlh_n_s16(a: i16) -> i16 { static_assert_uimm_bits!(N, 4); simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"] #[doc = "## Safety"] @@ -15718,7 +14899,6 @@ pub unsafe fn vqshls_n_s32(a: i32) -> i32 { static_assert_uimm_bits!(N, 5); simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"] #[doc = "## Safety"] @@ -15732,7 +14912,6 @@ pub unsafe fn vqshlb_n_u8(a: u8) -> u8 { static_assert_uimm_bits!(N, 3); simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"] #[doc = "## Safety"] @@ -15746,7 +14925,6 @@ pub unsafe fn vqshld_n_u64(a: u64) -> u64 { static_assert_uimm_bits!(N, 6); simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"] #[doc = "## Safety"] @@ -15760,7 +14938,6 @@ pub unsafe fn vqshlh_n_u16(a: u16) -> u16 { static_assert_uimm_bits!(N, 4); simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"] #[doc = "## Safety"] @@ -15774,7 +14951,6 @@ pub unsafe fn vqshls_n_u32(a: u32) -> u32 { static_assert_uimm_bits!(N, 5); simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"] #[doc = "## Safety"] @@ -15787,7 +14963,6 @@ pub unsafe fn vqshlb_s8(a: i8, b: i8) -> i8 { let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); simd_extract!(c, 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"] #[doc = "## Safety"] @@ -15800,7 +14975,6 @@ pub unsafe fn vqshlh_s16(a: i16, b: i16) -> i16 { let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); simd_extract!(c, 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"] #[doc = "## Safety"] @@ -15813,7 +14987,6 @@ pub unsafe fn vqshls_s32(a: i32, b: i32) -> i32 { let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); simd_extract!(c, 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"] #[doc = "## Safety"] @@ -15826,7 +14999,6 @@ pub unsafe fn vqshlb_u8(a: u8, b: i8) -> u8 { let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); simd_extract!(c, 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"] #[doc = "## Safety"] @@ -15839,7 +15011,6 @@ pub unsafe fn vqshlh_u16(a: u16, b: i16) -> u16 { let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); simd_extract!(c, 0) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"] #[doc = "## Safety"] @@ -15852,7 +15023,6 @@ pub unsafe fn vqshls_u32(a: u32, b: i32) -> u32 { let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); simd_extract!(c, 0) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"] #[doc = "## Safety"] @@ -15871,7 +15041,6 @@ pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { } _vqshld_s64(a, b) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"] #[doc = "## Safety"] @@ -15890,7 +15059,6 @@ pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { } _vqshld_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"] #[doc = "## Safety"] @@ -15904,7 +15072,6 @@ pub unsafe fn vqshlub_n_s8(a: i8) -> u8 { static_assert_uimm_bits!(N, 3); simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"] #[doc = "## Safety"] @@ -15918,7 +15085,6 @@ pub unsafe fn vqshlud_n_s64(a: i64) -> u64 { static_assert_uimm_bits!(N, 6); simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"] #[doc = "## Safety"] @@ -15932,7 +15098,6 @@ pub unsafe fn vqshluh_n_s16(a: i16) -> u16 { static_assert_uimm_bits!(N, 4); simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"] #[doc = "## Safety"] @@ -15946,7 +15111,6 @@ pub unsafe fn vqshlus_n_s32(a: i32) -> u32 { static_assert_uimm_bits!(N, 5); simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"] #[doc = "## Safety"] @@ -15964,7 +15128,6 @@ pub unsafe fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"] #[doc = "## Safety"] @@ -15978,7 +15141,6 @@ pub unsafe fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"] #[doc = "## Safety"] @@ -15992,7 +15154,6 @@ pub unsafe fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"] #[doc = "## Safety"] @@ -16010,7 +15171,6 @@ pub unsafe fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> ui [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"] #[doc = "## Safety"] @@ -16024,7 +15184,6 @@ pub unsafe fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> u static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"] #[doc = "## Safety"] @@ -16038,7 +15197,6 @@ pub unsafe fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> u static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"] #[doc = "## Safety"] @@ -16059,7 +15217,6 @@ pub unsafe fn vqshrnd_n_s64(a: i64) -> i32 { } _vqshrnd_n_s64(a, N) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"] #[doc = "## Safety"] @@ -16080,7 +15237,6 @@ pub unsafe fn vqshrnd_n_u64(a: u64) -> u32 { } _vqshrnd_n_u64(a.as_signed(), N).as_unsigned() } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"] #[doc = "## Safety"] @@ -16094,7 +15250,6 @@ pub unsafe fn vqshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"] #[doc = "## Safety"] @@ -16108,7 +15263,6 @@ pub unsafe fn vqshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"] #[doc = "## Safety"] @@ -16122,7 +15276,6 @@ pub unsafe fn vqshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"] #[doc = "## Safety"] @@ -16136,7 +15289,6 @@ pub unsafe fn vqshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"] #[doc = "## Safety"] @@ -16154,7 +15306,6 @@ pub unsafe fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> ui [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"] #[doc = "## Safety"] @@ -16168,7 +15319,6 @@ pub unsafe fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> u static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"] #[doc = "## Safety"] @@ -16182,7 +15332,6 @@ pub unsafe fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> u static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"] #[doc = "## Safety"] @@ -16196,7 +15345,6 @@ pub unsafe fn vqshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"] #[doc = "## Safety"] @@ -16210,7 +15358,6 @@ pub unsafe fn vqshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"] #[doc = "## Safety"] @@ -16224,7 +15371,6 @@ pub unsafe fn vqshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"] #[doc = "## Safety"] @@ -16238,7 +15384,6 @@ pub unsafe fn vqsubb_s8(a: i8, b: i8) -> i8 { let b: int8x8_t = vdup_n_s8(b); simd_extract!(vqsub_s8(a, b), 0) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"] #[doc = "## Safety"] @@ -16252,7 +15397,6 @@ pub unsafe fn vqsubh_s16(a: i16, b: i16) -> i16 { let b: int16x4_t = vdup_n_s16(b); simd_extract!(vqsub_s16(a, b), 0) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"] #[doc = "## Safety"] @@ -16266,7 +15410,6 @@ pub unsafe fn vqsubb_u8(a: u8, b: u8) -> u8 { let b: uint8x8_t = vdup_n_u8(b); simd_extract!(vqsub_u8(a, b), 0) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"] #[doc = "## Safety"] @@ -16280,7 +15423,6 @@ pub unsafe fn vqsubh_u16(a: u16, b: u16) -> u16 { let b: uint16x4_t = vdup_n_u16(b); simd_extract!(vqsub_u16(a, b), 0) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"] #[doc = "## Safety"] @@ -16299,7 +15441,6 @@ pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { } _vqsubs_s32(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"] #[doc = "## Safety"] @@ -16318,7 +15459,6 @@ pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { } _vqsubd_s64(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"] #[doc = "## Safety"] @@ -16337,7 +15477,6 @@ pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { } _vqsubs_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"] #[doc = "## Safety"] @@ -16356,7 +15495,6 @@ pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { } _vqsubd_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Rotate and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] #[doc = "## Safety"] @@ -16375,7 +15513,6 @@ pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } _vrax1q_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"] #[doc = "## Safety"] @@ -16394,7 +15531,6 @@ pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { } _vrbit_s8(a) } - #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"] #[doc = "## Safety"] @@ -16413,7 +15549,6 @@ pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { } _vrbitq_s8(a) } - #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] #[doc = "## Safety"] @@ -16425,7 +15560,6 @@ pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { transmute(vrbit_s8(transmute(a))) } - #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] #[doc = "## Safety"] @@ -16437,7 +15571,6 @@ pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { transmute(vrbitq_s8(transmute(a))) } - #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] #[doc = "## Safety"] @@ -16449,7 +15582,6 @@ pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { transmute(vrbit_s8(transmute(a))) } - #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] #[doc = "## Safety"] @@ -16461,7 +15593,6 @@ pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { transmute(vrbitq_s8(transmute(a))) } - #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"] #[doc = "## Safety"] @@ -16480,7 +15611,6 @@ pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { } _vrecpe_f64(a) } - #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"] #[doc = "## Safety"] @@ -16499,7 +15629,6 @@ pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { } _vrecpeq_f64(a) } - #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"] #[doc = "## Safety"] @@ -16518,7 +15647,6 @@ pub unsafe fn vrecped_f64(a: f64) -> f64 { } _vrecped_f64(a) } - #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"] #[doc = "## Safety"] @@ -16537,7 +15665,6 @@ pub unsafe fn vrecpes_f32(a: f32) -> f32 { } _vrecpes_f32(a) } - #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"] #[doc = "## Safety"] @@ -16556,7 +15683,6 @@ pub unsafe fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vrecps_f64(a, b) } - #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"] #[doc = "## Safety"] @@ -16575,7 +15701,6 @@ pub unsafe fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vrecpsq_f64(a, b) } - #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"] #[doc = "## Safety"] @@ -16594,7 +15719,6 @@ pub unsafe fn vrecpsd_f64(a: f64, b: f64) -> f64 { } _vrecpsd_f64(a, b) } - #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"] #[doc = "## Safety"] @@ -16613,7 +15737,6 @@ pub unsafe fn vrecpss_f32(a: f32, b: f32) -> f32 { } _vrecpss_f32(a, b) } - #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"] #[doc = "## Safety"] @@ -16632,7 +15755,6 @@ pub unsafe fn vrecpxd_f64(a: f64) -> f64 { } _vrecpxd_f64(a) } - #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"] #[doc = "## Safety"] @@ -16651,7 +15773,6 @@ pub unsafe fn vrecpxs_f32(a: f32) -> f32 { } _vrecpxs_f32(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] #[doc = "## Safety"] @@ -16663,7 +15784,6 @@ pub unsafe fn vrecpxs_f32(a: f32) -> f32 { pub unsafe fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] #[doc = "## Safety"] @@ -16675,7 +15795,6 @@ pub unsafe fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] #[doc = "## Safety"] @@ -16687,7 +15806,6 @@ pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] #[doc = "## Safety"] @@ -16699,7 +15817,6 @@ pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] #[doc = "## Safety"] @@ -16711,7 +15828,6 @@ pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] #[doc = "## Safety"] @@ -16723,7 +15839,6 @@ pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] #[doc = "## Safety"] @@ -16735,7 +15850,6 @@ pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] #[doc = "## Safety"] @@ -16747,7 +15861,6 @@ pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] #[doc = "## Safety"] @@ -16759,7 +15872,6 @@ pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] #[doc = "## Safety"] @@ -16771,7 +15883,6 @@ pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] #[doc = "## Safety"] @@ -16783,7 +15894,6 @@ pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] #[doc = "## Safety"] @@ -16795,7 +15905,6 @@ pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] #[doc = "## Safety"] @@ -16807,7 +15916,6 @@ pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] #[doc = "## Safety"] @@ -16819,7 +15927,6 @@ pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] #[doc = "## Safety"] @@ -16831,7 +15938,6 @@ pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] #[doc = "## Safety"] @@ -16843,7 +15949,6 @@ pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] #[doc = "## Safety"] @@ -16855,7 +15960,6 @@ pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] #[doc = "## Safety"] @@ -16867,7 +15971,6 @@ pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] #[doc = "## Safety"] @@ -16879,7 +15982,6 @@ pub unsafe fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] #[doc = "## Safety"] @@ -16891,7 +15993,6 @@ pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] #[doc = "## Safety"] @@ -16903,7 +16004,6 @@ pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] #[doc = "## Safety"] @@ -16915,7 +16015,6 @@ pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] #[doc = "## Safety"] @@ -16927,7 +16026,6 @@ pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] #[doc = "## Safety"] @@ -16939,7 +16037,6 @@ pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] #[doc = "## Safety"] @@ -16951,7 +16048,6 @@ pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] #[doc = "## Safety"] @@ -16963,7 +16059,6 @@ pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] #[doc = "## Safety"] @@ -16975,7 +16070,6 @@ pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] #[doc = "## Safety"] @@ -16987,7 +16081,6 @@ pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] #[doc = "## Safety"] @@ -16999,7 +16092,6 @@ pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] #[doc = "## Safety"] @@ -17011,7 +16103,6 @@ pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] #[doc = "## Safety"] @@ -17023,7 +16114,6 @@ pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] #[doc = "## Safety"] @@ -17035,7 +16125,6 @@ pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] #[doc = "## Safety"] @@ -17047,7 +16136,6 @@ pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] #[doc = "## Safety"] @@ -17059,7 +16147,6 @@ pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] #[doc = "## Safety"] @@ -17071,7 +16158,6 @@ pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] #[doc = "## Safety"] @@ -17083,7 +16169,6 @@ pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] #[doc = "## Safety"] @@ -17095,7 +16180,6 @@ pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] #[doc = "## Safety"] @@ -17107,7 +16191,6 @@ pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] #[doc = "## Safety"] @@ -17119,7 +16202,6 @@ pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] #[doc = "## Safety"] @@ -17131,7 +16213,6 @@ pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] #[doc = "## Safety"] @@ -17143,7 +16224,6 @@ pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] #[doc = "## Safety"] @@ -17155,7 +16235,6 @@ pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] #[doc = "## Safety"] @@ -17167,7 +16246,6 @@ pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] #[doc = "## Safety"] @@ -17179,7 +16257,6 @@ pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] #[doc = "## Safety"] @@ -17191,7 +16268,6 @@ pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] #[doc = "## Safety"] @@ -17203,7 +16279,6 @@ pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] #[doc = "## Safety"] @@ -17215,7 +16290,6 @@ pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] #[doc = "## Safety"] @@ -17227,7 +16301,6 @@ pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] #[doc = "## Safety"] @@ -17239,7 +16312,6 @@ pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] #[doc = "## Safety"] @@ -17251,7 +16323,6 @@ pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] #[doc = "## Safety"] @@ -17263,7 +16334,6 @@ pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] #[doc = "## Safety"] @@ -17275,7 +16345,6 @@ pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] #[doc = "## Safety"] @@ -17287,7 +16356,6 @@ pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] #[doc = "## Safety"] @@ -17299,7 +16367,6 @@ pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] #[doc = "## Safety"] @@ -17311,7 +16378,6 @@ pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] #[doc = "## Safety"] @@ -17323,7 +16389,6 @@ pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] #[doc = "## Safety"] @@ -17335,7 +16400,6 @@ pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] #[doc = "## Safety"] @@ -17347,7 +16411,6 @@ pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] #[doc = "## Safety"] @@ -17359,7 +16422,6 @@ pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] #[doc = "## Safety"] @@ -17371,7 +16433,6 @@ pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] #[doc = "## Safety"] @@ -17383,7 +16444,6 @@ pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] #[doc = "## Safety"] @@ -17395,7 +16455,6 @@ pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { transmute(a) } - #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"] #[doc = "## Safety"] @@ -17414,7 +16473,6 @@ pub unsafe fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { } _vrnd32x_f32(a) } - #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"] #[doc = "## Safety"] @@ -17433,7 +16491,6 @@ pub unsafe fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { } _vrnd32xq_f32(a) } - #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"] #[doc = "## Safety"] @@ -17452,7 +16509,6 @@ pub unsafe fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { } _vrnd32xq_f64(a) } - #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"] #[doc = "## Safety"] @@ -17471,7 +16527,6 @@ pub unsafe fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { } transmute(_vrnd32x_f64(simd_extract!(a, 0))) } - #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"] #[doc = "## Safety"] @@ -17490,7 +16545,6 @@ pub unsafe fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { } _vrnd32z_f32(a) } - #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"] #[doc = "## Safety"] @@ -17509,7 +16563,6 @@ pub unsafe fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { } _vrnd32zq_f32(a) } - #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"] #[doc = "## Safety"] @@ -17528,7 +16581,6 @@ pub unsafe fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { } _vrnd32zq_f64(a) } - #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"] #[doc = "## Safety"] @@ -17547,7 +16599,6 @@ pub unsafe fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { } transmute(_vrnd32z_f64(simd_extract!(a, 0))) } - #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"] #[doc = "## Safety"] @@ -17566,7 +16617,6 @@ pub unsafe fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { } _vrnd64x_f32(a) } - #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"] #[doc = "## Safety"] @@ -17585,7 +16635,6 @@ pub unsafe fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { } _vrnd64xq_f32(a) } - #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"] #[doc = "## Safety"] @@ -17604,7 +16653,6 @@ pub unsafe fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { } _vrnd64xq_f64(a) } - #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"] #[doc = "## Safety"] @@ -17623,7 +16671,6 @@ pub unsafe fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { } transmute(_vrnd64x_f64(simd_extract!(a, 0))) } - #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"] #[doc = "## Safety"] @@ -17642,7 +16689,6 @@ pub unsafe fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { } _vrnd64z_f32(a) } - #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"] #[doc = "## Safety"] @@ -17661,7 +16707,6 @@ pub unsafe fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { } _vrnd64zq_f32(a) } - #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"] #[doc = "## Safety"] @@ -17680,7 +16725,6 @@ pub unsafe fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { } _vrnd64zq_f64(a) } - #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"] #[doc = "## Safety"] @@ -17699,7 +16743,6 @@ pub unsafe fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { } transmute(_vrnd64z_f64(simd_extract!(a, 0))) } - #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"] #[doc = "## Safety"] @@ -17718,7 +16761,6 @@ pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { } _vrnd_f32(a) } - #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"] #[doc = "## Safety"] @@ -17737,7 +16779,6 @@ pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { } _vrndq_f32(a) } - #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"] #[doc = "## Safety"] @@ -17756,7 +16797,6 @@ pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { } _vrnd_f64(a) } - #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"] #[doc = "## Safety"] @@ -17775,7 +16815,6 @@ pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { } _vrndq_f64(a) } - #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"] #[doc = "## Safety"] @@ -17794,7 +16833,6 @@ pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { } _vrnda_f32(a) } - #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"] #[doc = "## Safety"] @@ -17813,7 +16851,6 @@ pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { } _vrndaq_f32(a) } - #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"] #[doc = "## Safety"] @@ -17832,7 +16869,6 @@ pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { } _vrnda_f64(a) } - #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"] #[doc = "## Safety"] @@ -17851,7 +16887,6 @@ pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { } _vrndaq_f64(a) } - #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"] #[doc = "## Safety"] @@ -17870,7 +16905,6 @@ pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { } _vrndi_f32(a) } - #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"] #[doc = "## Safety"] @@ -17889,7 +16923,6 @@ pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { } _vrndiq_f32(a) } - #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"] #[doc = "## Safety"] @@ -17908,7 +16941,6 @@ pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { } _vrndi_f64(a) } - #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"] #[doc = "## Safety"] @@ -17927,7 +16959,6 @@ pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { } _vrndiq_f64(a) } - #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"] #[doc = "## Safety"] @@ -17946,7 +16977,6 @@ pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { } _vrndm_f32(a) } - #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"] #[doc = "## Safety"] @@ -17965,7 +16995,6 @@ pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { } _vrndmq_f32(a) } - #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"] #[doc = "## Safety"] @@ -17984,7 +17013,6 @@ pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { } _vrndm_f64(a) } - #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"] #[doc = "## Safety"] @@ -18003,7 +17031,6 @@ pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { } _vrndmq_f64(a) } - #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"] #[doc = "## Safety"] @@ -18022,7 +17049,6 @@ pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { } _vrndn_f64(a) } - #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"] #[doc = "## Safety"] @@ -18041,7 +17067,6 @@ pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { } _vrndnq_f64(a) } - #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"] #[doc = "## Safety"] @@ -18060,7 +17085,6 @@ pub unsafe fn vrndns_f32(a: f32) -> f32 { } _vrndns_f32(a) } - #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"] #[doc = "## Safety"] @@ -18079,7 +17103,6 @@ pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { } _vrndp_f32(a) } - #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"] #[doc = "## Safety"] @@ -18098,7 +17121,6 @@ pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { } _vrndpq_f32(a) } - #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"] #[doc = "## Safety"] @@ -18117,7 +17139,6 @@ pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { } _vrndp_f64(a) } - #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"] #[doc = "## Safety"] @@ -18136,7 +17157,6 @@ pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { } _vrndpq_f64(a) } - #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"] #[doc = "## Safety"] @@ -18155,7 +17175,6 @@ pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { } _vrndx_f32(a) } - #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"] #[doc = "## Safety"] @@ -18174,7 +17193,6 @@ pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { } _vrndxq_f32(a) } - #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"] #[doc = "## Safety"] @@ -18193,7 +17211,6 @@ pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { } _vrndx_f64(a) } - #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"] #[doc = "## Safety"] @@ -18212,7 +17229,6 @@ pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { } _vrndxq_f64(a) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"] #[doc = "## Safety"] @@ -18231,7 +17247,6 @@ pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { } _vrshld_s64(a, b) } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"] #[doc = "## Safety"] @@ -18250,7 +17265,6 @@ pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { } _vrshld_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"] #[doc = "## Safety"] @@ -18264,7 +17278,6 @@ pub unsafe fn vrshrd_n_s64(a: i64) -> i64 { static_assert!(N >= 1 && N <= 64); vrshld_s64(a, -N as i64) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"] #[doc = "## Safety"] @@ -18278,7 +17291,6 @@ pub unsafe fn vrshrd_n_u64(a: u64) -> u64 { static_assert!(N >= 1 && N <= 64); vrshld_u64(a, -N as i64) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"] #[doc = "## Safety"] @@ -18296,7 +17308,6 @@ pub unsafe fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"] #[doc = "## Safety"] @@ -18310,7 +17321,6 @@ pub unsafe fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"] #[doc = "## Safety"] @@ -18324,7 +17334,6 @@ pub unsafe fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"] #[doc = "## Safety"] @@ -18342,7 +17351,6 @@ pub unsafe fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> ui [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"] #[doc = "## Safety"] @@ -18356,7 +17364,6 @@ pub unsafe fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> u static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"] #[doc = "## Safety"] @@ -18370,7 +17377,6 @@ pub unsafe fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> u static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) } - #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"] #[doc = "## Safety"] @@ -18389,7 +17395,6 @@ pub unsafe fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { } _vrsqrte_f64(a) } - #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"] #[doc = "## Safety"] @@ -18408,7 +17413,6 @@ pub unsafe fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { } _vrsqrteq_f64(a) } - #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"] #[doc = "## Safety"] @@ -18427,7 +17431,6 @@ pub unsafe fn vrsqrted_f64(a: f64) -> f64 { } _vrsqrted_f64(a) } - #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"] #[doc = "## Safety"] @@ -18446,7 +17449,6 @@ pub unsafe fn vrsqrtes_f32(a: f32) -> f32 { } _vrsqrtes_f32(a) } - #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"] #[doc = "## Safety"] @@ -18465,7 +17467,6 @@ pub unsafe fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } _vrsqrts_f64(a, b) } - #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"] #[doc = "## Safety"] @@ -18484,7 +17485,6 @@ pub unsafe fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } _vrsqrtsq_f64(a, b) } - #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"] #[doc = "## Safety"] @@ -18503,7 +17503,6 @@ pub unsafe fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { } _vrsqrtsd_f64(a, b) } - #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"] #[doc = "## Safety"] @@ -18522,7 +17521,6 @@ pub unsafe fn vrsqrtss_f32(a: f32, b: f32) -> f32 { } _vrsqrtss_f32(a, b) } - #[doc = "Signed rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"] #[doc = "## Safety"] @@ -18537,7 +17535,6 @@ pub unsafe fn vrsrad_n_s64(a: i64, b: i64) -> i64 { let b: i64 = vrshrd_n_s64::(b); a.wrapping_add(b) } - #[doc = "Unsigned rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"] #[doc = "## Safety"] @@ -18552,7 +17549,6 @@ pub unsafe fn vrsrad_n_u64(a: u64, b: u64) -> u64 { let b: u64 = vrshrd_n_u64::(b); a.wrapping_add(b) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] #[doc = "## Safety"] @@ -18565,7 +17561,6 @@ pub unsafe fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x let x: int8x8_t = vrsubhn_s16(b, c); simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] #[doc = "## Safety"] @@ -18578,7 +17573,6 @@ pub unsafe fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int1 let x: int16x4_t = vrsubhn_s32(b, c); simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] #[doc = "## Safety"] @@ -18591,7 +17585,6 @@ pub unsafe fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int3 let x: int32x2_t = vrsubhn_s64(b, c); simd_shuffle!(a, x, [0, 1, 2, 3]) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] #[doc = "## Safety"] @@ -18604,7 +17597,6 @@ pub unsafe fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> ui let x: uint8x8_t = vrsubhn_u16(b, c); simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] #[doc = "## Safety"] @@ -18617,7 +17609,6 @@ pub unsafe fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> u let x: uint16x4_t = vrsubhn_u32(b, c); simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] #[doc = "## Safety"] @@ -18630,7 +17621,6 @@ pub unsafe fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> u let x: uint32x2_t = vrsubhn_u64(b, c); simd_shuffle!(a, x, [0, 1, 2, 3]) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] #[doc = "## Safety"] @@ -18644,7 +17634,6 @@ pub unsafe fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x static_assert!(LANE == 0); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] #[doc = "## Safety"] @@ -18658,7 +17647,6 @@ pub unsafe fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64 static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "SHA512 hash update part 2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] #[doc = "## Safety"] @@ -18677,7 +17665,6 @@ pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uin } _vsha512h2q_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "SHA512 hash update part 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] #[doc = "## Safety"] @@ -18696,7 +17683,6 @@ pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint } _vsha512hq_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "SHA512 schedule update 0"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] #[doc = "## Safety"] @@ -18715,7 +17701,6 @@ pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } _vsha512su0q_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "SHA512 schedule update 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] #[doc = "## Safety"] @@ -18734,7 +17719,6 @@ pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> ui } _vsha512su1q_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"] #[doc = "## Safety"] @@ -18746,7 +17730,6 @@ pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> ui pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { transmute(vshl_s64(transmute(a), transmute(b))) } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"] #[doc = "## Safety"] @@ -18758,7 +17741,6 @@ pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { pub unsafe fn vshld_u64(a: u64, b: i64) -> u64 { transmute(vshl_u64(transmute(a), transmute(b))) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"] #[doc = "## Safety"] @@ -18773,7 +17755,6 @@ pub unsafe fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); vshll_n_s8::(b) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"] #[doc = "## Safety"] @@ -18788,7 +17769,6 @@ pub unsafe fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); vshll_n_s16::(b) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"] #[doc = "## Safety"] @@ -18803,7 +17783,6 @@ pub unsafe fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); vshll_n_s32::(b) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"] #[doc = "## Safety"] @@ -18818,7 +17797,6 @@ pub unsafe fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); vshll_n_u8::(b) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"] #[doc = "## Safety"] @@ -18833,7 +17811,6 @@ pub unsafe fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); vshll_n_u16::(b) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"] #[doc = "## Safety"] @@ -18848,7 +17825,6 @@ pub unsafe fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); vshll_n_u32::(b) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"] #[doc = "## Safety"] @@ -18866,7 +17842,6 @@ pub unsafe fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"] #[doc = "## Safety"] @@ -18880,7 +17855,6 @@ pub unsafe fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int1 static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"] #[doc = "## Safety"] @@ -18894,7 +17868,6 @@ pub unsafe fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int3 static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"] #[doc = "## Safety"] @@ -18912,7 +17885,6 @@ pub unsafe fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uin [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"] #[doc = "## Safety"] @@ -18926,7 +17898,6 @@ pub unsafe fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> ui static_assert!(N >= 1 && N <= 16); simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"] #[doc = "## Safety"] @@ -18940,7 +17911,6 @@ pub unsafe fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> ui static_assert!(N >= 1 && N <= 32); simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) } - #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"] #[doc = "## Safety"] @@ -18954,7 +17924,6 @@ pub unsafe fn vslid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 0 && N <= 63); transmute(vsli_n_s64::(transmute(a), transmute(b))) } - #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"] #[doc = "## Safety"] @@ -18968,7 +17937,6 @@ pub unsafe fn vslid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 0 && N <= 63); transmute(vsli_n_u64::(transmute(a), transmute(b))) } - #[doc = "SM3PARTW1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] #[doc = "## Safety"] @@ -18987,7 +17955,6 @@ pub unsafe fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> ui } _vsm3partw1q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "SM3PARTW2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] #[doc = "## Safety"] @@ -19006,7 +17973,6 @@ pub unsafe fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> ui } _vsm3partw2q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "SM3SS1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] #[doc = "## Safety"] @@ -19025,7 +17991,6 @@ pub unsafe fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint3 } _vsm3ss1q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "SM4 key"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] #[doc = "## Safety"] @@ -19044,7 +18009,6 @@ pub unsafe fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vsm4ekeyq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "SM4 encode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] #[doc = "## Safety"] @@ -19063,7 +18027,6 @@ pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vsm4eq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"] #[doc = "## Safety"] @@ -19075,7 +18038,6 @@ pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vsqaddb_u8(a: u8, b: i8) -> u8 { simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) } - #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"] #[doc = "## Safety"] @@ -19087,7 +18049,6 @@ pub unsafe fn vsqaddb_u8(a: u8, b: i8) -> u8 { pub unsafe fn vsqaddh_u16(a: u16, b: i16) -> u16 { simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) } - #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"] #[doc = "## Safety"] @@ -19106,7 +18067,6 @@ pub unsafe fn vsqaddd_u64(a: u64, b: i64) -> u64 { } _vsqaddd_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"] #[doc = "## Safety"] @@ -19125,7 +18085,6 @@ pub unsafe fn vsqadds_u32(a: u32, b: i32) -> u32 { } _vsqadds_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"] #[doc = "## Safety"] @@ -19137,7 +18096,6 @@ pub unsafe fn vsqadds_u32(a: u32, b: i32) -> u32 { pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { simd_fsqrt(a) } - #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"] #[doc = "## Safety"] @@ -19149,7 +18107,6 @@ pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { simd_fsqrt(a) } - #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"] #[doc = "## Safety"] @@ -19161,7 +18118,6 @@ pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { simd_fsqrt(a) } - #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"] #[doc = "## Safety"] @@ -19173,7 +18129,6 @@ pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { pub unsafe fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { simd_fsqrt(a) } - #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"] #[doc = "## Safety"] @@ -19187,7 +18142,6 @@ pub unsafe fn vsrid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); transmute(vsri_n_s64::(transmute(a), transmute(b))) } - #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"] #[doc = "## Safety"] @@ -19201,7 +18155,6 @@ pub unsafe fn vsrid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); transmute(vsri_n_u64::(transmute(a), transmute(b))) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"] #[doc = "## Safety"] @@ -19220,7 +18173,6 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { } _vst1_f64_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"] #[doc = "## Safety"] @@ -19239,7 +18191,6 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { } _vst1q_f64_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"] #[doc = "## Safety"] @@ -19258,7 +18209,6 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { } _vst1_f64_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"] #[doc = "## Safety"] @@ -19277,7 +18227,6 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { } _vst1q_f64_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"] #[doc = "## Safety"] @@ -19302,7 +18251,6 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { } _vst1_f64_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"] #[doc = "## Safety"] @@ -19327,7 +18275,6 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { } _vst1q_f64_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"] #[doc = "## Safety"] @@ -19341,7 +18288,6 @@ pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { static_assert!(LANE == 0); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"] #[doc = "## Safety"] @@ -19355,7 +18301,6 @@ pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"] #[doc = "## Safety"] @@ -19374,7 +18319,6 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { } _vst2_f64(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] #[doc = "## Safety"] @@ -19395,7 +18339,6 @@ pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { } _vst2_lane_f64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"] #[doc = "## Safety"] @@ -19416,7 +18359,6 @@ pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { } _vst2_lane_s64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"] #[doc = "## Safety"] @@ -19430,7 +18372,6 @@ pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { static_assert!(LANE == 0); vst2_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"] #[doc = "## Safety"] @@ -19444,7 +18385,6 @@ pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { static_assert!(LANE == 0); vst2_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"] #[doc = "## Safety"] @@ -19463,7 +18403,6 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { } _vst2q_f64(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] #[doc = "## Safety"] @@ -19482,7 +18421,6 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { } _vst2q_s64(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] #[doc = "## Safety"] @@ -19503,7 +18441,6 @@ pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { } _vst2q_lane_f64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"] #[doc = "## Safety"] @@ -19524,7 +18461,6 @@ pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { } _vst2q_lane_s8(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"] #[doc = "## Safety"] @@ -19545,7 +18481,6 @@ pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { } _vst2q_lane_s64(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"] #[doc = "## Safety"] @@ -19559,7 +18494,6 @@ pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { static_assert_uimm_bits!(LANE, 1); vst2q_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"] #[doc = "## Safety"] @@ -19573,7 +18507,6 @@ pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { static_assert_uimm_bits!(LANE, 4); vst2q_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"] #[doc = "## Safety"] @@ -19587,7 +18520,6 @@ pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { static_assert_uimm_bits!(LANE, 1); vst2q_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"] #[doc = "## Safety"] @@ -19601,7 +18533,6 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { static_assert_uimm_bits!(LANE, 4); vst2q_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"] #[doc = "## Safety"] @@ -19613,7 +18544,6 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { vst2q_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"] #[doc = "## Safety"] @@ -19625,7 +18555,6 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { vst2q_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"] #[doc = "## Safety"] @@ -19644,7 +18573,6 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { } _vst3_f64(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] #[doc = "## Safety"] @@ -19665,7 +18593,6 @@ pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { } _vst3_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"] #[doc = "## Safety"] @@ -19686,7 +18613,6 @@ pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { } _vst3_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"] #[doc = "## Safety"] @@ -19700,7 +18626,6 @@ pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { static_assert!(LANE == 0); vst3_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"] #[doc = "## Safety"] @@ -19714,7 +18639,6 @@ pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { static_assert!(LANE == 0); vst3_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"] #[doc = "## Safety"] @@ -19733,7 +18657,6 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { } _vst3q_f64(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] #[doc = "## Safety"] @@ -19752,7 +18675,6 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { } _vst3q_s64(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] #[doc = "## Safety"] @@ -19773,7 +18695,6 @@ pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { } _vst3q_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"] #[doc = "## Safety"] @@ -19794,7 +18715,6 @@ pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { } _vst3q_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"] #[doc = "## Safety"] @@ -19815,7 +18735,6 @@ pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { } _vst3q_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"] #[doc = "## Safety"] @@ -19829,7 +18748,6 @@ pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { static_assert_uimm_bits!(LANE, 1); vst3q_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"] #[doc = "## Safety"] @@ -19843,7 +18761,6 @@ pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { static_assert_uimm_bits!(LANE, 4); vst3q_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"] #[doc = "## Safety"] @@ -19857,7 +18774,6 @@ pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { static_assert_uimm_bits!(LANE, 1); vst3q_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"] #[doc = "## Safety"] @@ -19871,7 +18787,6 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { static_assert_uimm_bits!(LANE, 4); vst3q_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"] #[doc = "## Safety"] @@ -19883,7 +18798,6 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { vst3q_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"] #[doc = "## Safety"] @@ -19895,7 +18809,6 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { vst3q_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"] #[doc = "## Safety"] @@ -19914,7 +18827,6 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { } _vst4_f64(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] #[doc = "## Safety"] @@ -19942,7 +18854,6 @@ pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { } _vst4_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"] #[doc = "## Safety"] @@ -19970,7 +18881,6 @@ pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { } _vst4_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"] #[doc = "## Safety"] @@ -19984,7 +18894,6 @@ pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { static_assert!(LANE == 0); vst4_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"] #[doc = "## Safety"] @@ -19998,7 +18907,6 @@ pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { static_assert!(LANE == 0); vst4_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"] #[doc = "## Safety"] @@ -20017,7 +18925,6 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { } _vst4q_f64(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] #[doc = "## Safety"] @@ -20036,7 +18943,6 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { } _vst4q_s64(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] #[doc = "## Safety"] @@ -20064,7 +18970,6 @@ pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { } _vst4q_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"] #[doc = "## Safety"] @@ -20092,7 +18997,6 @@ pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { } _vst4q_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"] #[doc = "## Safety"] @@ -20120,7 +19024,6 @@ pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { } _vst4q_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"] #[doc = "## Safety"] @@ -20134,7 +19037,6 @@ pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { static_assert_uimm_bits!(LANE, 1); vst4q_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"] #[doc = "## Safety"] @@ -20148,7 +19050,6 @@ pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { static_assert_uimm_bits!(LANE, 4); vst4q_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"] #[doc = "## Safety"] @@ -20162,7 +19063,6 @@ pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { static_assert_uimm_bits!(LANE, 1); vst4q_lane_s64::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"] #[doc = "## Safety"] @@ -20176,7 +19076,6 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { static_assert_uimm_bits!(LANE, 4); vst4q_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"] #[doc = "## Safety"] @@ -20188,7 +19087,6 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { vst4q_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"] #[doc = "## Safety"] @@ -20200,7 +19098,6 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { vst4q_s64(transmute(a), transmute(b)) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] #[doc = "## Safety"] @@ -20212,7 +19109,6 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"] #[doc = "## Safety"] @@ -20224,7 +19120,6 @@ pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"] #[doc = "## Safety"] @@ -20236,7 +19131,6 @@ pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vsubd_s64(a: i64, b: i64) -> i64 { a.wrapping_sub(b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"] #[doc = "## Safety"] @@ -20248,7 +19142,6 @@ pub unsafe fn vsubd_s64(a: i64, b: i64) -> i64 { pub unsafe fn vsubd_u64(a: u64, b: u64) -> u64 { a.wrapping_sub(b) } - #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"] #[doc = "## Safety"] @@ -20264,7 +19157,6 @@ pub unsafe fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { let f: int16x8_t = simd_cast(e); simd_sub(d, f) } - #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"] #[doc = "## Safety"] @@ -20280,7 +19172,6 @@ pub unsafe fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { let f: int32x4_t = simd_cast(e); simd_sub(d, f) } - #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"] #[doc = "## Safety"] @@ -20296,7 +19187,6 @@ pub unsafe fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { let f: int64x2_t = simd_cast(e); simd_sub(d, f) } - #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"] #[doc = "## Safety"] @@ -20312,7 +19202,6 @@ pub unsafe fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { let f: uint16x8_t = simd_cast(e); simd_sub(d, f) } - #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"] #[doc = "## Safety"] @@ -20328,7 +19217,6 @@ pub unsafe fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { let f: uint32x4_t = simd_cast(e); simd_sub(d, f) } - #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"] #[doc = "## Safety"] @@ -20344,7 +19232,6 @@ pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { let f: uint64x2_t = simd_cast(e); simd_sub(d, f) } - #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"] #[doc = "## Safety"] @@ -20357,7 +19244,6 @@ pub unsafe fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); simd_sub(a, simd_cast(c)) } - #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"] #[doc = "## Safety"] @@ -20370,7 +19256,6 @@ pub unsafe fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); simd_sub(a, simd_cast(c)) } - #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"] #[doc = "## Safety"] @@ -20383,7 +19268,6 @@ pub unsafe fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); simd_sub(a, simd_cast(c)) } - #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"] #[doc = "## Safety"] @@ -20396,7 +19280,6 @@ pub unsafe fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); simd_sub(a, simd_cast(c)) } - #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"] #[doc = "## Safety"] @@ -20409,7 +19292,6 @@ pub unsafe fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); simd_sub(a, simd_cast(c)) } - #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"] #[doc = "## Safety"] @@ -20422,7 +19304,6 @@ pub unsafe fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); simd_sub(a, simd_cast(c)) } - #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] #[doc = "## Safety"] @@ -20442,7 +19323,6 @@ pub unsafe fn vsudot_laneq_s32( let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vusdot_s32(a, transmute(c), b) } - #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] #[doc = "## Safety"] @@ -20462,7 +19342,6 @@ pub unsafe fn vsudotq_laneq_s32( let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vusdotq_s32(a, transmute(c), b) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] #[doc = "## Safety"] @@ -20474,7 +19353,6 @@ pub unsafe fn vsudotq_laneq_s32( pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] #[doc = "## Safety"] @@ -20486,7 +19364,6 @@ pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] #[doc = "## Safety"] @@ -20498,7 +19375,6 @@ pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] #[doc = "## Safety"] @@ -20510,7 +19386,6 @@ pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] #[doc = "## Safety"] @@ -20522,7 +19397,6 @@ pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] #[doc = "## Safety"] @@ -20534,7 +19408,6 @@ pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] #[doc = "## Safety"] @@ -20546,7 +19419,6 @@ pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] #[doc = "## Safety"] @@ -20558,7 +19430,6 @@ pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] #[doc = "## Safety"] @@ -20570,7 +19441,6 @@ pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] #[doc = "## Safety"] @@ -20586,7 +19456,6 @@ pub unsafe fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] ) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] #[doc = "## Safety"] @@ -20598,7 +19467,6 @@ pub unsafe fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] #[doc = "## Safety"] @@ -20610,7 +19478,6 @@ pub unsafe fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] #[doc = "## Safety"] @@ -20622,7 +19489,6 @@ pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] #[doc = "## Safety"] @@ -20634,7 +19500,6 @@ pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] #[doc = "## Safety"] @@ -20650,7 +19515,6 @@ pub unsafe fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] ) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] #[doc = "## Safety"] @@ -20662,7 +19526,6 @@ pub unsafe fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] #[doc = "## Safety"] @@ -20674,7 +19537,6 @@ pub unsafe fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] #[doc = "## Safety"] @@ -20686,7 +19548,6 @@ pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] #[doc = "## Safety"] @@ -20698,7 +19559,6 @@ pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] #[doc = "## Safety"] @@ -20714,7 +19574,6 @@ pub unsafe fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] ) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] #[doc = "## Safety"] @@ -20726,7 +19585,6 @@ pub unsafe fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] #[doc = "## Safety"] @@ -20738,7 +19596,6 @@ pub unsafe fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] #[doc = "## Safety"] @@ -20750,7 +19607,6 @@ pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] #[doc = "## Safety"] @@ -20762,7 +19618,6 @@ pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] #[doc = "## Safety"] @@ -20774,7 +19629,6 @@ pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] #[doc = "## Safety"] @@ -20786,7 +19640,6 @@ pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] #[doc = "## Safety"] @@ -20798,7 +19651,6 @@ pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] #[doc = "## Safety"] @@ -20810,7 +19662,6 @@ pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] #[doc = "## Safety"] @@ -20822,7 +19673,6 @@ pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] #[doc = "## Safety"] @@ -20834,7 +19684,6 @@ pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] #[doc = "## Safety"] @@ -20846,7 +19695,6 @@ pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] #[doc = "## Safety"] @@ -20862,7 +19710,6 @@ pub unsafe fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] ) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] #[doc = "## Safety"] @@ -20874,7 +19721,6 @@ pub unsafe fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] #[doc = "## Safety"] @@ -20886,7 +19732,6 @@ pub unsafe fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] #[doc = "## Safety"] @@ -20898,7 +19743,6 @@ pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] #[doc = "## Safety"] @@ -20910,7 +19754,6 @@ pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] #[doc = "## Safety"] @@ -20926,7 +19769,6 @@ pub unsafe fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] ) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] #[doc = "## Safety"] @@ -20938,7 +19780,6 @@ pub unsafe fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] #[doc = "## Safety"] @@ -20950,7 +19791,6 @@ pub unsafe fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] #[doc = "## Safety"] @@ -20962,7 +19802,6 @@ pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] #[doc = "## Safety"] @@ -20974,7 +19813,6 @@ pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] #[doc = "## Safety"] @@ -20990,7 +19828,6 @@ pub unsafe fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] ) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] #[doc = "## Safety"] @@ -21002,7 +19839,6 @@ pub unsafe fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } - #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] #[doc = "## Safety"] @@ -21014,7 +19850,6 @@ pub unsafe fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"] #[doc = "## Safety"] @@ -21028,7 +19863,6 @@ pub unsafe fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { let d: i64x1 = i64x1::new(0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"] #[doc = "## Safety"] @@ -21042,7 +19876,6 @@ pub unsafe fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { let d: i64x2 = i64x2::new(0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"] #[doc = "## Safety"] @@ -21056,7 +19889,6 @@ pub unsafe fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { let d: i64x1 = i64x1::new(0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"] #[doc = "## Safety"] @@ -21070,7 +19902,6 @@ pub unsafe fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { let d: i64x2 = i64x2::new(0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"] #[doc = "## Safety"] @@ -21084,7 +19915,6 @@ pub unsafe fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { let d: u64x1 = u64x1::new(0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"] #[doc = "## Safety"] @@ -21098,7 +19928,6 @@ pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { let d: u64x2 = u64x2::new(0, 0); simd_ne(c, transmute(d)) } - #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"] #[doc = "## Safety"] @@ -21110,7 +19939,6 @@ pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vtstd_s64(a: i64, b: i64) -> u64 { transmute(vtst_s64(transmute(a), transmute(b))) } - #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"] #[doc = "## Safety"] @@ -21122,7 +19950,6 @@ pub unsafe fn vtstd_s64(a: i64, b: i64) -> u64 { pub unsafe fn vtstd_u64(a: u64, b: u64) -> u64 { transmute(vtst_u64(transmute(a), transmute(b))) } - #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"] #[doc = "## Safety"] @@ -21134,7 +19961,6 @@ pub unsafe fn vtstd_u64(a: u64, b: u64) -> u64 { pub unsafe fn vuqaddb_s8(a: i8, b: u8) -> i8 { simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) } - #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"] #[doc = "## Safety"] @@ -21146,7 +19972,6 @@ pub unsafe fn vuqaddb_s8(a: i8, b: u8) -> i8 { pub unsafe fn vuqaddh_s16(a: i16, b: u16) -> i16 { simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) } - #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"] #[doc = "## Safety"] @@ -21165,7 +19990,6 @@ pub unsafe fn vuqaddd_s64(a: i64, b: u64) -> i64 { } _vuqaddd_s64(a, b.as_signed()) } - #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"] #[doc = "## Safety"] @@ -21184,7 +20008,6 @@ pub unsafe fn vuqadds_s32(a: i32, b: u32) -> i32 { } _vuqadds_s32(a, b.as_signed()) } - #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] #[doc = "## Safety"] @@ -21204,7 +20027,6 @@ pub unsafe fn vusdot_laneq_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vusdot_s32(a, b, transmute(c)) } - #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] #[doc = "## Safety"] @@ -21224,7 +20046,6 @@ pub unsafe fn vusdotq_laneq_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vusdotq_s32(a, b, transmute(c)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] #[doc = "## Safety"] @@ -21236,7 +20057,6 @@ pub unsafe fn vusdotq_laneq_s32( pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] #[doc = "## Safety"] @@ -21248,7 +20068,6 @@ pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] #[doc = "## Safety"] @@ -21260,7 +20079,6 @@ pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] #[doc = "## Safety"] @@ -21272,7 +20090,6 @@ pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] #[doc = "## Safety"] @@ -21284,7 +20101,6 @@ pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] #[doc = "## Safety"] @@ -21296,7 +20112,6 @@ pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] #[doc = "## Safety"] @@ -21308,7 +20123,6 @@ pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] #[doc = "## Safety"] @@ -21320,7 +20134,6 @@ pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_shuffle!(a, b, [0, 2, 4, 6]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] #[doc = "## Safety"] @@ -21332,7 +20145,6 @@ pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] #[doc = "## Safety"] @@ -21348,7 +20160,6 @@ pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] ) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] #[doc = "## Safety"] @@ -21360,7 +20171,6 @@ pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [0, 2, 4, 6]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] #[doc = "## Safety"] @@ -21372,7 +20182,6 @@ pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] #[doc = "## Safety"] @@ -21384,7 +20193,6 @@ pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [0, 2, 4, 6]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] #[doc = "## Safety"] @@ -21396,7 +20204,6 @@ pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] #[doc = "## Safety"] @@ -21412,7 +20219,6 @@ pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] ) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] #[doc = "## Safety"] @@ -21424,7 +20230,6 @@ pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [0, 2, 4, 6]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] #[doc = "## Safety"] @@ -21436,7 +20241,6 @@ pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] #[doc = "## Safety"] @@ -21448,7 +20252,6 @@ pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [0, 2, 4, 6]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] #[doc = "## Safety"] @@ -21460,7 +20263,6 @@ pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] #[doc = "## Safety"] @@ -21476,7 +20278,6 @@ pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] ) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] #[doc = "## Safety"] @@ -21488,7 +20289,6 @@ pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [0, 2, 4, 6]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] #[doc = "## Safety"] @@ -21500,7 +20300,6 @@ pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] #[doc = "## Safety"] @@ -21512,7 +20311,6 @@ pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] #[doc = "## Safety"] @@ -21524,7 +20322,6 @@ pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] #[doc = "## Safety"] @@ -21536,7 +20333,6 @@ pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] #[doc = "## Safety"] @@ -21548,7 +20344,6 @@ pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] #[doc = "## Safety"] @@ -21560,7 +20355,6 @@ pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] #[doc = "## Safety"] @@ -21572,7 +20366,6 @@ pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] #[doc = "## Safety"] @@ -21584,7 +20377,6 @@ pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] #[doc = "## Safety"] @@ -21596,7 +20388,6 @@ pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_shuffle!(a, b, [1, 3, 5, 7]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] #[doc = "## Safety"] @@ -21608,7 +20399,6 @@ pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] #[doc = "## Safety"] @@ -21624,7 +20414,6 @@ pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] ) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] #[doc = "## Safety"] @@ -21636,7 +20425,6 @@ pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [1, 3, 5, 7]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] #[doc = "## Safety"] @@ -21648,7 +20436,6 @@ pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] #[doc = "## Safety"] @@ -21660,7 +20447,6 @@ pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [1, 3, 5, 7]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] #[doc = "## Safety"] @@ -21672,7 +20458,6 @@ pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] #[doc = "## Safety"] @@ -21688,7 +20473,6 @@ pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] ) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] #[doc = "## Safety"] @@ -21700,7 +20484,6 @@ pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [1, 3, 5, 7]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] #[doc = "## Safety"] @@ -21712,7 +20495,6 @@ pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] #[doc = "## Safety"] @@ -21724,7 +20506,6 @@ pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [1, 3, 5, 7]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] #[doc = "## Safety"] @@ -21736,7 +20517,6 @@ pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] #[doc = "## Safety"] @@ -21752,7 +20532,6 @@ pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] ) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] #[doc = "## Safety"] @@ -21764,7 +20543,6 @@ pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [1, 3, 5, 7]) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] #[doc = "## Safety"] @@ -21776,7 +20554,6 @@ pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] #[doc = "## Safety"] @@ -21788,7 +20565,6 @@ pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] #[doc = "## Safety"] @@ -21800,7 +20576,6 @@ pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_shuffle!(a, b, [0, 4, 1, 5]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] #[doc = "## Safety"] @@ -21812,7 +20587,6 @@ pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] #[doc = "## Safety"] @@ -21824,7 +20598,6 @@ pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] #[doc = "## Safety"] @@ -21840,7 +20613,6 @@ pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] ) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] #[doc = "## Safety"] @@ -21852,7 +20624,6 @@ pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [0, 4, 1, 5]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] #[doc = "## Safety"] @@ -21864,7 +20635,6 @@ pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] #[doc = "## Safety"] @@ -21876,7 +20646,6 @@ pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] #[doc = "## Safety"] @@ -21888,7 +20657,6 @@ pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [0, 4, 1, 5]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] #[doc = "## Safety"] @@ -21900,7 +20668,6 @@ pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] #[doc = "## Safety"] @@ -21912,7 +20679,6 @@ pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] #[doc = "## Safety"] @@ -21928,7 +20694,6 @@ pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] ) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] #[doc = "## Safety"] @@ -21940,7 +20705,6 @@ pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [0, 4, 1, 5]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] #[doc = "## Safety"] @@ -21952,7 +20716,6 @@ pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] #[doc = "## Safety"] @@ -21964,7 +20727,6 @@ pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] #[doc = "## Safety"] @@ -21976,7 +20738,6 @@ pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [0, 4, 1, 5]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] #[doc = "## Safety"] @@ -21988,7 +20749,6 @@ pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] #[doc = "## Safety"] @@ -22000,7 +20760,6 @@ pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] #[doc = "## Safety"] @@ -22016,7 +20775,6 @@ pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] ) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] #[doc = "## Safety"] @@ -22028,7 +20786,6 @@ pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [0, 4, 1, 5]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] #[doc = "## Safety"] @@ -22040,7 +20797,6 @@ pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] #[doc = "## Safety"] @@ -22052,7 +20808,6 @@ pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [0, 2]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] #[doc = "## Safety"] @@ -22064,7 +20819,6 @@ pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] #[doc = "## Safety"] @@ -22076,7 +20830,6 @@ pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_shuffle!(a, b, [2, 6, 3, 7]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] #[doc = "## Safety"] @@ -22088,7 +20841,6 @@ pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] #[doc = "## Safety"] @@ -22100,7 +20852,6 @@ pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub unsafe fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] #[doc = "## Safety"] @@ -22116,7 +20867,6 @@ pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] #[doc = "## Safety"] @@ -22128,7 +20878,6 @@ pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [2, 6, 3, 7]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] #[doc = "## Safety"] @@ -22140,7 +20889,6 @@ pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] #[doc = "## Safety"] @@ -22152,7 +20900,6 @@ pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] #[doc = "## Safety"] @@ -22164,7 +20911,6 @@ pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [2, 6, 3, 7]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] #[doc = "## Safety"] @@ -22176,7 +20922,6 @@ pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] #[doc = "## Safety"] @@ -22188,7 +20933,6 @@ pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] #[doc = "## Safety"] @@ -22204,7 +20948,6 @@ pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] #[doc = "## Safety"] @@ -22216,7 +20959,6 @@ pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [2, 6, 3, 7]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] #[doc = "## Safety"] @@ -22228,7 +20970,6 @@ pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] #[doc = "## Safety"] @@ -22240,7 +20981,6 @@ pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] #[doc = "## Safety"] @@ -22252,7 +20992,6 @@ pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [2, 6, 3, 7]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] #[doc = "## Safety"] @@ -22264,7 +21003,6 @@ pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_shuffle!(a, b, [1, 3]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] #[doc = "## Safety"] @@ -22276,7 +21014,6 @@ pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] #[doc = "## Safety"] @@ -22292,7 +21029,6 @@ pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] #[doc = "## Safety"] @@ -22304,7 +21040,6 @@ pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [2, 6, 3, 7]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] #[doc = "## Safety"] @@ -22316,7 +21051,6 @@ pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] #[doc = "## Safety"] diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs index 09be5282e9..aaddbff95c 100644 --- a/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/crates/core_arch/src/arm_shared/neon/generated.rs @@ -1,9 +1,9 @@ // This code is automatically generated. DO NOT MODIFY. // -// Instead, modify `crates/stdarch-gen2/spec/` and run the following command to re-generate this file: +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: // // ``` -// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec // ``` #![allow(improper_ctypes)] @@ -37,7 +37,6 @@ pub unsafe fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { let e: uint8x8_t = simd_cast(d); simd_add(a, simd_cast(e)) } - #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"] #[doc = "## Safety"] @@ -63,7 +62,6 @@ pub unsafe fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { let e: uint16x4_t = simd_cast(d); simd_add(a, simd_cast(e)) } - #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"] #[doc = "## Safety"] @@ -89,7 +87,6 @@ pub unsafe fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { let e: uint32x2_t = simd_cast(d); simd_add(a, simd_cast(e)) } - #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"] #[doc = "## Safety"] @@ -114,7 +111,6 @@ pub unsafe fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t let d: uint8x8_t = vabd_u8(b, c); simd_add(a, simd_cast(d)) } - #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"] #[doc = "## Safety"] @@ -139,7 +135,6 @@ pub unsafe fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4 let d: uint16x4_t = vabd_u16(b, c); simd_add(a, simd_cast(d)) } - #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"] #[doc = "## Safety"] @@ -164,7 +159,6 @@ pub unsafe fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2 let d: uint32x2_t = vabd_u32(b, c); simd_add(a, simd_cast(d)) } - #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"] #[doc = "## Safety"] @@ -196,7 +190,6 @@ pub unsafe fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vabd_f32(a, b) } - #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"] #[doc = "## Safety"] @@ -228,7 +221,6 @@ pub unsafe fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vabdq_f32(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"] #[doc = "## Safety"] @@ -260,7 +252,6 @@ pub unsafe fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vabd_s8(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"] #[doc = "## Safety"] @@ -292,7 +283,6 @@ pub unsafe fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vabdq_s8(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"] #[doc = "## Safety"] @@ -324,7 +314,6 @@ pub unsafe fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vabd_s16(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"] #[doc = "## Safety"] @@ -356,7 +345,6 @@ pub unsafe fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vabdq_s16(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"] #[doc = "## Safety"] @@ -388,7 +376,6 @@ pub unsafe fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vabd_s32(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"] #[doc = "## Safety"] @@ -420,7 +407,6 @@ pub unsafe fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vabdq_s32(a, b) } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"] #[doc = "## Safety"] @@ -452,7 +438,6 @@ pub unsafe fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vabd_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"] #[doc = "## Safety"] @@ -484,7 +469,6 @@ pub unsafe fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vabdq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"] #[doc = "## Safety"] @@ -516,7 +500,6 @@ pub unsafe fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vabd_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"] #[doc = "## Safety"] @@ -548,7 +531,6 @@ pub unsafe fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vabdq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"] #[doc = "## Safety"] @@ -580,7 +562,6 @@ pub unsafe fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vabd_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"] #[doc = "## Safety"] @@ -612,7 +593,6 @@ pub unsafe fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vabdq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"] #[doc = "## Safety"] @@ -637,7 +617,6 @@ pub unsafe fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { let c: uint8x8_t = simd_cast(vabd_s8(a, b)); simd_cast(c) } - #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"] #[doc = "## Safety"] @@ -662,7 +641,6 @@ pub unsafe fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { let c: uint16x4_t = simd_cast(vabd_s16(a, b)); simd_cast(c) } - #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"] #[doc = "## Safety"] @@ -687,7 +665,6 @@ pub unsafe fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { let c: uint32x2_t = simd_cast(vabd_s32(a, b)); simd_cast(c) } - #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"] #[doc = "## Safety"] @@ -711,7 +688,6 @@ pub unsafe fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { pub unsafe fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { simd_cast(vabd_u8(a, b)) } - #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"] #[doc = "## Safety"] @@ -735,7 +711,6 @@ pub unsafe fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { pub unsafe fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { simd_cast(vabd_u16(a, b)) } - #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"] #[doc = "## Safety"] @@ -759,7 +734,6 @@ pub unsafe fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { pub unsafe fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { simd_cast(vabd_u32(a, b)) } - #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"] #[doc = "## Safety"] @@ -783,7 +757,6 @@ pub unsafe fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { pub unsafe fn vabs_f32(a: float32x2_t) -> float32x2_t { simd_fabs(a) } - #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"] #[doc = "## Safety"] @@ -807,7 +780,6 @@ pub unsafe fn vabs_f32(a: float32x2_t) -> float32x2_t { pub unsafe fn vabsq_f32(a: float32x4_t) -> float32x4_t { simd_fabs(a) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"] #[doc = "## Safety"] @@ -831,7 +803,6 @@ pub unsafe fn vabsq_f32(a: float32x4_t) -> float32x4_t { pub unsafe fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_xor(a, b) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"] #[doc = "## Safety"] @@ -855,7 +826,6 @@ pub unsafe fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { pub unsafe fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { simd_xor(a, b) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"] #[doc = "## Safety"] @@ -879,7 +849,6 @@ pub unsafe fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_xor(a, b) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"] #[doc = "## Safety"] @@ -903,7 +872,6 @@ pub unsafe fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { pub unsafe fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_xor(a, b) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"] #[doc = "## Safety"] @@ -927,7 +895,6 @@ pub unsafe fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { pub unsafe fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { simd_xor(a, b) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"] #[doc = "## Safety"] @@ -951,7 +918,6 @@ pub unsafe fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { pub unsafe fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_xor(a, b) } - #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"] #[doc = "## Safety"] @@ -975,7 +941,6 @@ pub unsafe fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { pub unsafe fn vaddq_p128(a: p128, b: p128) -> p128 { a ^ b } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"] #[doc = "## Safety"] @@ -999,7 +964,6 @@ pub unsafe fn vaddq_p128(a: p128, b: p128) -> p128 { pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"] #[doc = "## Safety"] @@ -1023,7 +987,6 @@ pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"] #[doc = "## Safety"] @@ -1047,7 +1010,6 @@ pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"] #[doc = "## Safety"] @@ -1071,7 +1033,6 @@ pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"] #[doc = "## Safety"] @@ -1095,7 +1056,6 @@ pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"] #[doc = "## Safety"] @@ -1119,7 +1079,6 @@ pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"] #[doc = "## Safety"] @@ -1143,7 +1102,6 @@ pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"] #[doc = "## Safety"] @@ -1167,7 +1125,6 @@ pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"] #[doc = "## Safety"] @@ -1191,7 +1148,6 @@ pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"] #[doc = "## Safety"] @@ -1215,7 +1171,6 @@ pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"] #[doc = "## Safety"] @@ -1239,7 +1194,6 @@ pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"] #[doc = "## Safety"] @@ -1263,7 +1217,6 @@ pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"] #[doc = "## Safety"] @@ -1287,7 +1240,6 @@ pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"] #[doc = "## Safety"] @@ -1311,7 +1263,6 @@ pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"] #[doc = "## Safety"] @@ -1335,7 +1286,6 @@ pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_and(a, b) } - #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"] #[doc = "## Safety"] @@ -1359,7 +1309,6 @@ pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_and(a, b) } - #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"] #[doc = "## Safety"] @@ -1391,7 +1340,6 @@ pub unsafe fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } _vcage_f32(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"] #[doc = "## Safety"] @@ -1423,7 +1371,6 @@ pub unsafe fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } _vcageq_f32(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"] #[doc = "## Safety"] @@ -1455,7 +1402,6 @@ pub unsafe fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } _vcagt_f32(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"] #[doc = "## Safety"] @@ -1487,7 +1433,6 @@ pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } _vcagtq_f32(a, b).as_unsigned() } - #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"] #[doc = "## Safety"] @@ -1511,7 +1456,6 @@ pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { vcage_f32(b, a) } - #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"] #[doc = "## Safety"] @@ -1535,7 +1479,6 @@ pub unsafe fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { vcageq_f32(b, a) } - #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"] #[doc = "## Safety"] @@ -1559,7 +1502,6 @@ pub unsafe fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { vcagt_f32(b, a) } - #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"] #[doc = "## Safety"] @@ -1583,7 +1525,6 @@ pub unsafe fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { vcagtq_f32(b, a) } - #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"] #[doc = "## Safety"] @@ -1607,7 +1548,6 @@ pub unsafe fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { simd_eq(a, b) } - #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"] #[doc = "## Safety"] @@ -1631,7 +1571,6 @@ pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"] #[doc = "## Safety"] @@ -1655,7 +1594,6 @@ pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"] #[doc = "## Safety"] @@ -1679,7 +1617,6 @@ pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"] #[doc = "## Safety"] @@ -1703,7 +1640,6 @@ pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"] #[doc = "## Safety"] @@ -1727,7 +1663,6 @@ pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"] #[doc = "## Safety"] @@ -1751,7 +1686,6 @@ pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"] #[doc = "## Safety"] @@ -1775,7 +1709,6 @@ pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"] #[doc = "## Safety"] @@ -1799,7 +1732,6 @@ pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { pub unsafe fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"] #[doc = "## Safety"] @@ -1823,7 +1755,6 @@ pub unsafe fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"] #[doc = "## Safety"] @@ -1847,7 +1778,6 @@ pub unsafe fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"] #[doc = "## Safety"] @@ -1871,7 +1801,6 @@ pub unsafe fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"] #[doc = "## Safety"] @@ -1895,7 +1824,6 @@ pub unsafe fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"] #[doc = "## Safety"] @@ -1919,7 +1847,6 @@ pub unsafe fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"] #[doc = "## Safety"] @@ -1943,7 +1870,6 @@ pub unsafe fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { simd_eq(a, b) } - #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"] #[doc = "## Safety"] @@ -1967,7 +1893,6 @@ pub unsafe fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { pub unsafe fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { simd_eq(a, b) } - #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"] #[doc = "## Safety"] @@ -1991,7 +1916,6 @@ pub unsafe fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { simd_ge(a, b) } - #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"] #[doc = "## Safety"] @@ -2015,7 +1939,6 @@ pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"] #[doc = "## Safety"] @@ -2039,7 +1962,6 @@ pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"] #[doc = "## Safety"] @@ -2063,7 +1985,6 @@ pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"] #[doc = "## Safety"] @@ -2087,7 +2008,6 @@ pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"] #[doc = "## Safety"] @@ -2111,7 +2031,6 @@ pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"] #[doc = "## Safety"] @@ -2135,7 +2054,6 @@ pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { simd_ge(a, b) } - #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"] #[doc = "## Safety"] @@ -2159,7 +2077,6 @@ pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"] #[doc = "## Safety"] @@ -2183,7 +2100,6 @@ pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"] #[doc = "## Safety"] @@ -2207,7 +2123,6 @@ pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"] #[doc = "## Safety"] @@ -2231,7 +2146,6 @@ pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"] #[doc = "## Safety"] @@ -2255,7 +2169,6 @@ pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"] #[doc = "## Safety"] @@ -2279,7 +2192,6 @@ pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_ge(a, b) } - #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"] #[doc = "## Safety"] @@ -2303,7 +2215,6 @@ pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_ge(a, b) } - #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"] #[doc = "## Safety"] @@ -2327,7 +2238,6 @@ pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { simd_gt(a, b) } - #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"] #[doc = "## Safety"] @@ -2351,7 +2261,6 @@ pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"] #[doc = "## Safety"] @@ -2375,7 +2284,6 @@ pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"] #[doc = "## Safety"] @@ -2399,7 +2307,6 @@ pub unsafe fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { pub unsafe fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"] #[doc = "## Safety"] @@ -2423,7 +2330,6 @@ pub unsafe fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { pub unsafe fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"] #[doc = "## Safety"] @@ -2447,7 +2353,6 @@ pub unsafe fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { pub unsafe fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"] #[doc = "## Safety"] @@ -2471,7 +2376,6 @@ pub unsafe fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { pub unsafe fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { simd_gt(a, b) } - #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"] #[doc = "## Safety"] @@ -2495,7 +2399,6 @@ pub unsafe fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { pub unsafe fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"] #[doc = "## Safety"] @@ -2519,7 +2422,6 @@ pub unsafe fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { pub unsafe fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"] #[doc = "## Safety"] @@ -2543,7 +2445,6 @@ pub unsafe fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"] #[doc = "## Safety"] @@ -2567,7 +2468,6 @@ pub unsafe fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"] #[doc = "## Safety"] @@ -2591,7 +2491,6 @@ pub unsafe fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"] #[doc = "## Safety"] @@ -2615,7 +2514,6 @@ pub unsafe fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_gt(a, b) } - #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"] #[doc = "## Safety"] @@ -2639,7 +2537,6 @@ pub unsafe fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_gt(a, b) } - #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"] #[doc = "## Safety"] @@ -2663,7 +2560,6 @@ pub unsafe fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { simd_le(a, b) } - #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"] #[doc = "## Safety"] @@ -2687,7 +2583,6 @@ pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"] #[doc = "## Safety"] @@ -2711,7 +2606,6 @@ pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"] #[doc = "## Safety"] @@ -2735,7 +2629,6 @@ pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"] #[doc = "## Safety"] @@ -2759,7 +2652,6 @@ pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"] #[doc = "## Safety"] @@ -2783,7 +2675,6 @@ pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"] #[doc = "## Safety"] @@ -2807,7 +2698,6 @@ pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { simd_le(a, b) } - #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"] #[doc = "## Safety"] @@ -2831,7 +2721,6 @@ pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"] #[doc = "## Safety"] @@ -2855,7 +2744,6 @@ pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"] #[doc = "## Safety"] @@ -2879,7 +2767,6 @@ pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"] #[doc = "## Safety"] @@ -2903,7 +2790,6 @@ pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"] #[doc = "## Safety"] @@ -2927,7 +2813,6 @@ pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"] #[doc = "## Safety"] @@ -2951,7 +2836,6 @@ pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_le(a, b) } - #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"] #[doc = "## Safety"] @@ -2975,7 +2859,6 @@ pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_le(a, b) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"] #[doc = "## Safety"] @@ -3007,7 +2890,6 @@ pub unsafe fn vcls_s8(a: int8x8_t) -> int8x8_t { } _vcls_s8(a) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"] #[doc = "## Safety"] @@ -3039,7 +2921,6 @@ pub unsafe fn vclsq_s8(a: int8x16_t) -> int8x16_t { } _vclsq_s8(a) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"] #[doc = "## Safety"] @@ -3071,7 +2952,6 @@ pub unsafe fn vcls_s16(a: int16x4_t) -> int16x4_t { } _vcls_s16(a) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"] #[doc = "## Safety"] @@ -3103,7 +2983,6 @@ pub unsafe fn vclsq_s16(a: int16x8_t) -> int16x8_t { } _vclsq_s16(a) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"] #[doc = "## Safety"] @@ -3135,7 +3014,6 @@ pub unsafe fn vcls_s32(a: int32x2_t) -> int32x2_t { } _vcls_s32(a) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"] #[doc = "## Safety"] @@ -3167,7 +3045,6 @@ pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { } _vclsq_s32(a) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"] #[doc = "## Safety"] @@ -3191,7 +3068,6 @@ pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { pub unsafe fn vcls_u8(a: uint8x8_t) -> int8x8_t { vcls_s8(transmute(a)) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"] #[doc = "## Safety"] @@ -3215,7 +3091,6 @@ pub unsafe fn vcls_u8(a: uint8x8_t) -> int8x8_t { pub unsafe fn vclsq_u8(a: uint8x16_t) -> int8x16_t { vclsq_s8(transmute(a)) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"] #[doc = "## Safety"] @@ -3239,7 +3114,6 @@ pub unsafe fn vclsq_u8(a: uint8x16_t) -> int8x16_t { pub unsafe fn vcls_u16(a: uint16x4_t) -> int16x4_t { vcls_s16(transmute(a)) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"] #[doc = "## Safety"] @@ -3263,7 +3137,6 @@ pub unsafe fn vcls_u16(a: uint16x4_t) -> int16x4_t { pub unsafe fn vclsq_u16(a: uint16x8_t) -> int16x8_t { vclsq_s16(transmute(a)) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"] #[doc = "## Safety"] @@ -3287,7 +3160,6 @@ pub unsafe fn vclsq_u16(a: uint16x8_t) -> int16x8_t { pub unsafe fn vcls_u32(a: uint32x2_t) -> int32x2_t { vcls_s32(transmute(a)) } - #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"] #[doc = "## Safety"] @@ -3311,7 +3183,6 @@ pub unsafe fn vcls_u32(a: uint32x2_t) -> int32x2_t { pub unsafe fn vclsq_u32(a: uint32x4_t) -> int32x4_t { vclsq_s32(transmute(a)) } - #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"] #[doc = "## Safety"] @@ -3335,7 +3206,6 @@ pub unsafe fn vclsq_u32(a: uint32x4_t) -> int32x4_t { pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { simd_lt(a, b) } - #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"] #[doc = "## Safety"] @@ -3359,7 +3229,6 @@ pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"] #[doc = "## Safety"] @@ -3383,7 +3252,6 @@ pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"] #[doc = "## Safety"] @@ -3407,7 +3275,6 @@ pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"] #[doc = "## Safety"] @@ -3431,7 +3298,6 @@ pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"] #[doc = "## Safety"] @@ -3455,7 +3321,6 @@ pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"] #[doc = "## Safety"] @@ -3479,7 +3344,6 @@ pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { simd_lt(a, b) } - #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"] #[doc = "## Safety"] @@ -3503,7 +3367,6 @@ pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"] #[doc = "## Safety"] @@ -3527,7 +3390,6 @@ pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"] #[doc = "## Safety"] @@ -3551,7 +3413,6 @@ pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"] #[doc = "## Safety"] @@ -3575,7 +3436,6 @@ pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"] #[doc = "## Safety"] @@ -3599,7 +3459,6 @@ pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"] #[doc = "## Safety"] @@ -3623,7 +3482,6 @@ pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_lt(a, b) } - #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"] #[doc = "## Safety"] @@ -3647,7 +3505,6 @@ pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_lt(a, b) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"] #[doc = "## Safety"] @@ -3671,7 +3528,6 @@ pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { vclz_s16_(a) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"] #[doc = "## Safety"] @@ -3695,7 +3551,6 @@ pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { vclzq_s16_(a) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"] #[doc = "## Safety"] @@ -3719,7 +3574,6 @@ pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { vclz_s32_(a) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"] #[doc = "## Safety"] @@ -3743,7 +3597,6 @@ pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { vclzq_s32_(a) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"] #[doc = "## Safety"] @@ -3767,7 +3620,6 @@ pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { vclz_s8_(a) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"] #[doc = "## Safety"] @@ -3791,7 +3643,6 @@ pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { vclzq_s8_(a) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] #[doc = "## Safety"] @@ -3815,7 +3666,6 @@ pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { transmute(vclz_s16_(transmute(a))) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] #[doc = "## Safety"] @@ -3839,7 +3689,6 @@ pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { transmute(vclzq_s16_(transmute(a))) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] #[doc = "## Safety"] @@ -3863,7 +3712,6 @@ pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { transmute(vclz_s32_(transmute(a))) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] #[doc = "## Safety"] @@ -3887,7 +3735,6 @@ pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { transmute(vclzq_s32_(transmute(a))) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] #[doc = "## Safety"] @@ -3911,7 +3758,6 @@ pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { transmute(vclz_s8_(transmute(a))) } - #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] #[doc = "## Safety"] @@ -3935,7 +3781,6 @@ pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { transmute(vclzq_s8_(transmute(a))) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] #[doc = "## Safety"] @@ -3959,7 +3804,6 @@ pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] #[doc = "## Safety"] @@ -3983,7 +3827,6 @@ pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] #[doc = "## Safety"] @@ -4007,7 +3850,6 @@ pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] #[doc = "## Safety"] @@ -4031,7 +3873,6 @@ pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] #[doc = "## Safety"] @@ -4055,7 +3896,6 @@ pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { pub unsafe fn vcreate_s64(a: u64) -> int64x1_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] #[doc = "## Safety"] @@ -4079,7 +3919,6 @@ pub unsafe fn vcreate_s64(a: u64) -> int64x1_t { pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] #[doc = "## Safety"] @@ -4103,7 +3942,6 @@ pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] #[doc = "## Safety"] @@ -4127,7 +3965,6 @@ pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"] #[doc = "## Safety"] @@ -4151,7 +3988,6 @@ pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { pub unsafe fn vcreate_u64(a: u64) -> uint64x1_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] #[doc = "## Safety"] @@ -4175,7 +4011,6 @@ pub unsafe fn vcreate_u64(a: u64) -> uint64x1_t { pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] #[doc = "## Safety"] @@ -4199,7 +4034,6 @@ pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { transmute(a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"] #[doc = "## Safety"] @@ -4223,7 +4057,6 @@ pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { pub unsafe fn vcreate_p64(a: u64) -> poly64x1_t { transmute(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"] #[doc = "## Safety"] @@ -4247,7 +4080,6 @@ pub unsafe fn vcreate_p64(a: u64) -> poly64x1_t { pub unsafe fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"] #[doc = "## Safety"] @@ -4271,7 +4103,6 @@ pub unsafe fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { pub unsafe fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"] #[doc = "## Safety"] @@ -4295,7 +4126,6 @@ pub unsafe fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { pub unsafe fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"] #[doc = "## Safety"] @@ -4319,7 +4149,6 @@ pub unsafe fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { pub unsafe fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { simd_cast(a) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] #[doc = "## Safety"] @@ -4341,7 +4170,6 @@ pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { } _vcvt_n_f32_s32(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] #[doc = "## Safety"] @@ -4363,7 +4191,6 @@ pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { } _vcvtq_n_f32_s32(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] #[doc = "## Safety"] @@ -4385,7 +4212,6 @@ pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { } _vcvt_n_f32_s32(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] #[doc = "## Safety"] @@ -4407,7 +4233,6 @@ pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { } _vcvtq_n_f32_s32(a, N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] #[doc = "## Safety"] @@ -4429,7 +4254,6 @@ pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { } _vcvt_n_f32_u32(a.as_signed(), N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] #[doc = "## Safety"] @@ -4451,7 +4275,6 @@ pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { } _vcvtq_n_f32_u32(a.as_signed(), N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] #[doc = "## Safety"] @@ -4473,7 +4296,6 @@ pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { } _vcvt_n_f32_u32(a.as_signed(), N) } - #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] #[doc = "## Safety"] @@ -4495,7 +4317,6 @@ pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { } _vcvtq_n_f32_u32(a.as_signed(), N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] #[doc = "## Safety"] @@ -4517,7 +4338,6 @@ pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvt_n_s32_f32(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] #[doc = "## Safety"] @@ -4539,7 +4359,6 @@ pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtq_n_s32_f32(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] #[doc = "## Safety"] @@ -4561,7 +4380,6 @@ pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvt_n_s32_f32(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] #[doc = "## Safety"] @@ -4583,7 +4401,6 @@ pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtq_n_s32_f32(a, N) } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] #[doc = "## Safety"] @@ -4605,7 +4422,6 @@ pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvt_n_u32_f32(a, N).as_unsigned() } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] #[doc = "## Safety"] @@ -4627,7 +4443,6 @@ pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtq_n_u32_f32(a, N).as_unsigned() } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] #[doc = "## Safety"] @@ -4649,7 +4464,6 @@ pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvt_n_u32_f32(a, N).as_unsigned() } - #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] #[doc = "## Safety"] @@ -4671,7 +4485,6 @@ pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtq_n_u32_f32(a, N).as_unsigned() } - #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"] #[doc = "## Safety"] @@ -4703,7 +4516,6 @@ pub unsafe fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { } _vcvt_s32_f32(a) } - #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"] #[doc = "## Safety"] @@ -4735,7 +4547,6 @@ pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { } _vcvtq_s32_f32(a) } - #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"] #[doc = "## Safety"] @@ -4767,7 +4578,6 @@ pub unsafe fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { } _vcvt_u32_f32(a).as_unsigned() } - #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"] #[doc = "## Safety"] @@ -4799,7 +4609,6 @@ pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { } _vcvtq_u32_f32(a).as_unsigned() } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] #[doc = "## Safety"] @@ -4827,7 +4636,6 @@ pub unsafe fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vdot_s32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] #[doc = "## Safety"] @@ -4859,7 +4667,6 @@ pub unsafe fn vdotq_lane_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vdotq_s32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] #[doc = "## Safety"] @@ -4891,7 +4698,6 @@ pub unsafe fn vdot_lane_u32( let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vdot_u32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] #[doc = "## Safety"] @@ -4923,7 +4729,6 @@ pub unsafe fn vdotq_lane_u32( let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vdotq_u32(a, b, transmute(c)) } - #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] #[doc = "## Safety"] @@ -4955,7 +4760,6 @@ pub unsafe fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { } _vdot_s32(a, b, c) } - #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] #[doc = "## Safety"] @@ -4987,7 +4791,6 @@ pub unsafe fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { } _vdotq_s32(a, b, c) } - #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] #[doc = "## Safety"] @@ -5019,7 +4822,6 @@ pub unsafe fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t } _vdot_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] #[doc = "## Safety"] @@ -5051,7 +4853,6 @@ pub unsafe fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4 } _vdotq_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] #[doc = "## Safety"] @@ -5077,7 +4878,6 @@ pub unsafe fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] #[doc = "## Safety"] @@ -5103,7 +4903,6 @@ pub unsafe fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] #[doc = "## Safety"] @@ -5129,7 +4928,6 @@ pub unsafe fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] #[doc = "## Safety"] @@ -5155,7 +4953,6 @@ pub unsafe fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] #[doc = "## Safety"] @@ -5181,7 +4978,6 @@ pub unsafe fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] #[doc = "## Safety"] @@ -5207,7 +5003,6 @@ pub unsafe fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] #[doc = "## Safety"] @@ -5233,7 +5028,6 @@ pub unsafe fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] #[doc = "## Safety"] @@ -5259,7 +5053,6 @@ pub unsafe fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] #[doc = "## Safety"] @@ -5285,7 +5078,6 @@ pub unsafe fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] #[doc = "## Safety"] @@ -5315,7 +5107,6 @@ pub unsafe fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] #[doc = "## Safety"] @@ -5345,7 +5136,6 @@ pub unsafe fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] #[doc = "## Safety"] @@ -5375,7 +5165,6 @@ pub unsafe fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] #[doc = "## Safety"] @@ -5405,7 +5194,6 @@ pub unsafe fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] #[doc = "## Safety"] @@ -5435,7 +5223,6 @@ pub unsafe fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] #[doc = "## Safety"] @@ -5465,7 +5252,6 @@ pub unsafe fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] #[doc = "## Safety"] @@ -5498,7 +5284,6 @@ pub unsafe fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { ] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] #[doc = "## Safety"] @@ -5531,7 +5316,6 @@ pub unsafe fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { ] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] #[doc = "## Safety"] @@ -5564,7 +5348,6 @@ pub unsafe fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { ] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] #[doc = "## Safety"] @@ -5590,7 +5373,6 @@ pub unsafe fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { static_assert!(N == 0); a } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] #[doc = "## Safety"] @@ -5616,7 +5398,6 @@ pub unsafe fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { static_assert!(N == 0); a } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] #[doc = "## Safety"] @@ -5642,7 +5423,6 @@ pub unsafe fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] #[doc = "## Safety"] @@ -5668,7 +5448,6 @@ pub unsafe fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] #[doc = "## Safety"] @@ -5694,7 +5473,6 @@ pub unsafe fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] #[doc = "## Safety"] @@ -5720,7 +5498,6 @@ pub unsafe fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] #[doc = "## Safety"] @@ -5746,7 +5523,6 @@ pub unsafe fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] #[doc = "## Safety"] @@ -5772,7 +5548,6 @@ pub unsafe fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] #[doc = "## Safety"] @@ -5798,7 +5573,6 @@ pub unsafe fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { static_assert_uimm_bits!(N, 3); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] #[doc = "## Safety"] @@ -5824,7 +5598,6 @@ pub unsafe fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(N, 3); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] #[doc = "## Safety"] @@ -5850,7 +5623,6 @@ pub unsafe fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(N, 3); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] #[doc = "## Safety"] @@ -5880,7 +5652,6 @@ pub unsafe fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] #[doc = "## Safety"] @@ -5910,7 +5681,6 @@ pub unsafe fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] #[doc = "## Safety"] @@ -5940,7 +5710,6 @@ pub unsafe fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] #[doc = "## Safety"] @@ -5970,7 +5739,6 @@ pub unsafe fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] #[doc = "## Safety"] @@ -6000,7 +5768,6 @@ pub unsafe fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] #[doc = "## Safety"] @@ -6030,7 +5797,6 @@ pub unsafe fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] #[doc = "## Safety"] @@ -6063,7 +5829,6 @@ pub unsafe fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { ] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] #[doc = "## Safety"] @@ -6096,7 +5861,6 @@ pub unsafe fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { ] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] #[doc = "## Safety"] @@ -6129,7 +5893,6 @@ pub unsafe fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { ] ) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] #[doc = "## Safety"] @@ -6155,7 +5918,6 @@ pub unsafe fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { static_assert_uimm_bits!(N, 1); transmute::(simd_extract!(a, N as u32)) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] #[doc = "## Safety"] @@ -6181,7 +5943,6 @@ pub unsafe fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { static_assert_uimm_bits!(N, 1); transmute::(simd_extract!(a, N as u32)) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] #[doc = "## Safety"] @@ -6207,7 +5968,6 @@ pub unsafe fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { static_assert!(N == 0); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] #[doc = "## Safety"] @@ -6233,7 +5993,6 @@ pub unsafe fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { static_assert!(N == 0); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] #[doc = "## Safety"] @@ -6259,7 +6018,6 @@ pub unsafe fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] #[doc = "## Safety"] @@ -6285,7 +6043,6 @@ pub unsafe fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32]) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] #[doc = "## Safety"] @@ -6309,7 +6066,6 @@ pub unsafe fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] #[doc = "## Safety"] @@ -6333,7 +6089,6 @@ pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] #[doc = "## Safety"] @@ -6357,7 +6112,6 @@ pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] #[doc = "## Safety"] @@ -6381,7 +6135,6 @@ pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] #[doc = "## Safety"] @@ -6405,7 +6158,6 @@ pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] #[doc = "## Safety"] @@ -6429,7 +6181,6 @@ pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] #[doc = "## Safety"] @@ -6453,7 +6204,6 @@ pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] #[doc = "## Safety"] @@ -6477,7 +6227,6 @@ pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] #[doc = "## Safety"] @@ -6501,7 +6250,6 @@ pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] #[doc = "## Safety"] @@ -6525,7 +6273,6 @@ pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] #[doc = "## Safety"] @@ -6549,7 +6296,6 @@ pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] #[doc = "## Safety"] @@ -6573,7 +6319,6 @@ pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] #[doc = "## Safety"] @@ -6597,7 +6342,6 @@ pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] #[doc = "## Safety"] @@ -6621,7 +6365,6 @@ pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] #[doc = "## Safety"] @@ -6645,7 +6388,6 @@ pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_xor(a, b) } - #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] #[doc = "## Safety"] @@ -6669,7 +6411,6 @@ pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_xor(a, b) } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] #[doc = "## Safety"] @@ -6699,7 +6440,6 @@ pub unsafe fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] #[doc = "## Safety"] @@ -6729,7 +6469,6 @@ pub unsafe fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] #[doc = "## Safety"] @@ -6759,7 +6498,6 @@ pub unsafe fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] #[doc = "## Safety"] @@ -6795,7 +6533,6 @@ pub unsafe fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] #[doc = "## Safety"] @@ -6831,7 +6568,6 @@ pub unsafe fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] #[doc = "## Safety"] @@ -6867,7 +6603,6 @@ pub unsafe fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] #[doc = "## Safety"] @@ -6903,7 +6638,6 @@ pub unsafe fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_ _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] #[doc = "## Safety"] @@ -6939,7 +6673,6 @@ pub unsafe fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] #[doc = "## Safety"] @@ -6975,7 +6708,6 @@ pub unsafe fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_ _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] #[doc = "## Safety"] @@ -7007,7 +6739,6 @@ pub unsafe fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32 _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] #[doc = "## Safety"] @@ -7039,7 +6770,6 @@ pub unsafe fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] #[doc = "## Safety"] @@ -7071,7 +6801,6 @@ pub unsafe fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] #[doc = "## Safety"] @@ -7103,7 +6832,6 @@ pub unsafe fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] #[doc = "## Safety"] @@ -7135,7 +6863,6 @@ pub unsafe fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_ _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] #[doc = "## Safety"] @@ -7167,7 +6894,6 @@ pub unsafe fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] #[doc = "## Safety"] @@ -7197,7 +6923,6 @@ pub unsafe fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] #[doc = "## Safety"] @@ -7227,7 +6952,6 @@ pub unsafe fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_ _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] #[doc = "## Safety"] @@ -7331,7 +7055,6 @@ pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] #[doc = "## Safety"] @@ -7435,7 +7158,6 @@ pub unsafe fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t _ => unreachable_unchecked(), } } - #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] #[doc = "## Safety"] @@ -7539,7 +7261,6 @@ pub unsafe fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t _ => unreachable_unchecked(), } } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] #[doc = "## Safety"] @@ -7568,7 +7289,6 @@ pub unsafe fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 } _vfma_f32(b, c, a) } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] #[doc = "## Safety"] @@ -7597,7 +7317,6 @@ pub unsafe fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float } _vfmaq_f32(b, c, a) } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] #[doc = "## Safety"] @@ -7621,7 +7340,6 @@ pub unsafe fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float pub unsafe fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vfma_f32(a, b, vdup_n_f32_vfp4(c)) } - #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] #[doc = "## Safety"] @@ -7645,7 +7363,6 @@ pub unsafe fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t pub unsafe fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) } - #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] #[doc = "## Safety"] @@ -7670,7 +7387,6 @@ pub unsafe fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 let b: float32x2_t = simd_neg(b); vfma_f32(a, b, c) } - #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] #[doc = "## Safety"] @@ -7695,7 +7411,6 @@ pub unsafe fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float let b: float32x4_t = simd_neg(b); vfmaq_f32(a, b, c) } - #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] #[doc = "## Safety"] @@ -7719,7 +7434,6 @@ pub unsafe fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float pub unsafe fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vfms_f32(a, b, vdup_n_f32_vfp4(c)) } - #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] #[doc = "## Safety"] @@ -7743,7 +7457,6 @@ pub unsafe fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t pub unsafe fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] #[doc = "## Safety"] @@ -7775,7 +7488,6 @@ pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vhadd_s8(a, b) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] #[doc = "## Safety"] @@ -7807,7 +7519,6 @@ pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vhaddq_s8(a, b) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] #[doc = "## Safety"] @@ -7839,7 +7550,6 @@ pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vhadd_s16(a, b) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] #[doc = "## Safety"] @@ -7871,7 +7581,6 @@ pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vhaddq_s16(a, b) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] #[doc = "## Safety"] @@ -7903,7 +7612,6 @@ pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vhadd_s32(a, b) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] #[doc = "## Safety"] @@ -7935,7 +7643,6 @@ pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vhaddq_s32(a, b) } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] #[doc = "## Safety"] @@ -7967,7 +7674,6 @@ pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vhadd_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] #[doc = "## Safety"] @@ -7999,7 +7705,6 @@ pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vhaddq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] #[doc = "## Safety"] @@ -8031,7 +7736,6 @@ pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vhadd_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] #[doc = "## Safety"] @@ -8063,7 +7767,6 @@ pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vhaddq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] #[doc = "## Safety"] @@ -8095,7 +7798,6 @@ pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vhadd_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] #[doc = "## Safety"] @@ -8127,7 +7829,6 @@ pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vhaddq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] #[doc = "## Safety"] @@ -8159,7 +7860,6 @@ pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vhsub_s16(a, b) } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] #[doc = "## Safety"] @@ -8191,7 +7891,6 @@ pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vhsubq_s16(a, b) } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] #[doc = "## Safety"] @@ -8223,7 +7922,6 @@ pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vhsub_s32(a, b) } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] #[doc = "## Safety"] @@ -8255,7 +7953,6 @@ pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vhsubq_s32(a, b) } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] #[doc = "## Safety"] @@ -8287,7 +7984,6 @@ pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vhsub_s8(a, b) } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] #[doc = "## Safety"] @@ -8319,7 +8015,6 @@ pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vhsubq_s8(a, b) } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] #[doc = "## Safety"] @@ -8351,7 +8046,6 @@ pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vhsub_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] #[doc = "## Safety"] @@ -8383,7 +8077,6 @@ pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vhsubq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] #[doc = "## Safety"] @@ -8415,7 +8108,6 @@ pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vhsub_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] #[doc = "## Safety"] @@ -8447,7 +8139,6 @@ pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vhsubq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] #[doc = "## Safety"] @@ -8479,7 +8170,6 @@ pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vhsub_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] #[doc = "## Safety"] @@ -8511,7 +8201,6 @@ pub unsafe fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vhsubq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] #[doc = "## Safety"] @@ -8543,7 +8232,6 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { } _vld1_f32_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] #[doc = "## Safety"] @@ -8575,7 +8263,6 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { } _vld1_f32_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] #[doc = "## Safety"] @@ -8607,7 +8294,6 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { } _vld1_f32_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] #[doc = "## Safety"] @@ -8639,7 +8325,6 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { } _vld1q_f32_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] #[doc = "## Safety"] @@ -8671,7 +8356,6 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { } _vld1q_f32_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] #[doc = "## Safety"] @@ -8703,7 +8387,6 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { } _vld1q_f32_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] #[doc = "## Safety"] @@ -8727,7 +8410,6 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { transmute(vld1_s64_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] #[doc = "## Safety"] @@ -8751,7 +8433,6 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { transmute(vld1_s64_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] #[doc = "## Safety"] @@ -8775,7 +8456,6 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { transmute(vld1_s64_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] @@ -8799,7 +8479,6 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { transmute(vld1q_s64_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] @@ -8823,7 +8502,6 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { transmute(vld1q_s64_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] @@ -8847,7 +8525,6 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { transmute(vld1q_s64_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] #[doc = "## Safety"] @@ -8879,7 +8556,6 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { } _vld1_s8_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] #[doc = "## Safety"] @@ -8911,7 +8587,6 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { } _vld1_s8_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] #[doc = "## Safety"] @@ -8943,7 +8618,6 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { } _vld1_s8_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] #[doc = "## Safety"] @@ -8975,7 +8649,6 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { } _vld1q_s8_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] #[doc = "## Safety"] @@ -9007,7 +8680,6 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { } _vld1q_s8_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] #[doc = "## Safety"] @@ -9039,7 +8711,6 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { } _vld1q_s8_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] #[doc = "## Safety"] @@ -9071,7 +8742,6 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { } _vld1_s16_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] #[doc = "## Safety"] @@ -9103,7 +8773,6 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { } _vld1_s16_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] #[doc = "## Safety"] @@ -9135,7 +8804,6 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { } _vld1_s16_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] #[doc = "## Safety"] @@ -9167,7 +8835,6 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { } _vld1q_s16_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] #[doc = "## Safety"] @@ -9199,7 +8866,6 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { } _vld1q_s16_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] #[doc = "## Safety"] @@ -9231,7 +8897,6 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { } _vld1q_s16_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] #[doc = "## Safety"] @@ -9263,7 +8928,6 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { } _vld1_s32_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] #[doc = "## Safety"] @@ -9295,7 +8959,6 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { } _vld1_s32_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] #[doc = "## Safety"] @@ -9327,7 +8990,6 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { } _vld1_s32_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] #[doc = "## Safety"] @@ -9359,7 +9021,6 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { } _vld1q_s32_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] #[doc = "## Safety"] @@ -9391,7 +9052,6 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { } _vld1q_s32_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] #[doc = "## Safety"] @@ -9423,7 +9083,6 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { } _vld1q_s32_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] #[doc = "## Safety"] @@ -9455,7 +9114,6 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { } _vld1_s64_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] #[doc = "## Safety"] @@ -9487,7 +9145,6 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { } _vld1_s64_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] #[doc = "## Safety"] @@ -9519,7 +9176,6 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { } _vld1_s64_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] #[doc = "## Safety"] @@ -9551,7 +9207,6 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { } _vld1q_s64_x2(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] #[doc = "## Safety"] @@ -9583,7 +9238,6 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { } _vld1q_s64_x3(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] #[doc = "## Safety"] @@ -9615,7 +9269,6 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { } _vld1q_s64_x4(a) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] @@ -9639,7 +9292,6 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { transmute(vld1_s8_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] @@ -9663,7 +9315,6 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { transmute(vld1_s8_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] @@ -9687,7 +9338,6 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { transmute(vld1_s8_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] @@ -9711,7 +9361,6 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { transmute(vld1q_s8_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] @@ -9735,7 +9384,6 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { transmute(vld1q_s8_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] @@ -9759,7 +9407,6 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { transmute(vld1q_s8_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] @@ -9783,7 +9430,6 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { transmute(vld1_s16_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] @@ -9807,7 +9453,6 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { transmute(vld1_s16_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] @@ -9831,7 +9476,6 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { transmute(vld1_s16_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] @@ -9855,7 +9499,6 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { transmute(vld1q_s16_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] @@ -9879,7 +9522,6 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { transmute(vld1q_s16_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] @@ -9903,7 +9545,6 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { transmute(vld1q_s16_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] @@ -9927,7 +9568,6 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { transmute(vld1_s32_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] @@ -9951,7 +9591,6 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { transmute(vld1_s32_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] @@ -9975,7 +9614,6 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { transmute(vld1_s32_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] @@ -9999,7 +9637,6 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { transmute(vld1q_s32_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] @@ -10023,7 +9660,6 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { transmute(vld1q_s32_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] @@ -10047,7 +9683,6 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { transmute(vld1q_s32_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] @@ -10071,7 +9706,6 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { transmute(vld1_s64_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] @@ -10095,7 +9729,6 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { transmute(vld1_s64_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] @@ -10119,7 +9752,6 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { transmute(vld1_s64_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] @@ -10143,7 +9775,6 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { transmute(vld1q_s64_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] @@ -10167,7 +9798,6 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { transmute(vld1q_s64_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] @@ -10191,7 +9821,6 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { transmute(vld1q_s64_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] @@ -10215,7 +9844,6 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { transmute(vld1_s8_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] @@ -10239,7 +9867,6 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { transmute(vld1_s8_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] @@ -10263,7 +9890,6 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { transmute(vld1_s8_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] @@ -10287,7 +9913,6 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { transmute(vld1q_s8_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] @@ -10311,7 +9936,6 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { transmute(vld1q_s8_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] @@ -10335,7 +9959,6 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { transmute(vld1q_s8_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] @@ -10359,7 +9982,6 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { transmute(vld1_s16_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] @@ -10383,7 +10005,6 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { transmute(vld1_s16_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] @@ -10407,7 +10028,6 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { transmute(vld1_s16_x4(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] @@ -10431,7 +10051,6 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { transmute(vld1q_s16_x2(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] @@ -10455,7 +10074,6 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { transmute(vld1q_s16_x3(transmute(a))) } - #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] @@ -10479,7 +10097,6 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { transmute(vld1q_s16_x4(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] @@ -10496,7 +10113,6 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { } _vld2_dup_f32(a as *const i8, 4) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] @@ -10513,7 +10129,6 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { } _vld2q_dup_f32(a as *const i8, 4) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] @@ -10530,7 +10145,6 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { } _vld2_dup_s8(a as *const i8, 1) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] @@ -10547,7 +10161,6 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { } _vld2q_dup_s8(a as *const i8, 1) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] @@ -10564,7 +10177,6 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { } _vld2_dup_s16(a as *const i8, 2) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] @@ -10581,7 +10193,6 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { } _vld2q_dup_s16(a as *const i8, 2) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] @@ -10598,7 +10209,6 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { } _vld2_dup_s32(a as *const i8, 4) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] @@ -10615,7 +10225,6 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { } _vld2q_dup_s32(a as *const i8, 4) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] @@ -10635,7 +10244,6 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { } _vld2_dup_f32(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] @@ -10655,7 +10263,6 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { } _vld2q_dup_f32(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] @@ -10675,7 +10282,6 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { } _vld2_dup_s8(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] @@ -10695,7 +10301,6 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { } _vld2q_dup_s8(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] @@ -10715,7 +10320,6 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { } _vld2_dup_s16(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] @@ -10735,7 +10339,6 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { } _vld2q_dup_s16(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] @@ -10755,7 +10358,6 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { } _vld2_dup_s32(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] @@ -10775,7 +10377,6 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { } _vld2q_dup_s32(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] #[doc = "## Safety"] @@ -10799,7 +10400,6 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { transmute(vld2_dup_s64(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] @@ -10816,7 +10416,6 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { } _vld2_dup_s64(a as *const i8, 8) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] @@ -10836,7 +10435,6 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { } _vld2_dup_s64(a as _) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] #[doc = "## Safety"] @@ -10860,7 +10458,6 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { transmute(vld2_dup_s64(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] @@ -10884,7 +10481,6 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { transmute(vld2_dup_s8(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] @@ -10908,7 +10504,6 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { transmute(vld2q_dup_s8(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] @@ -10932,7 +10527,6 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { transmute(vld2_dup_s16(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] @@ -10956,7 +10550,6 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { transmute(vld2q_dup_s16(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] @@ -10980,7 +10573,6 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { transmute(vld2_dup_s32(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] @@ -11004,7 +10596,6 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { transmute(vld2q_dup_s32(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] @@ -11028,7 +10619,6 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { transmute(vld2_dup_s8(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] @@ -11052,7 +10642,6 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { transmute(vld2q_dup_s8(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] @@ -11076,7 +10665,6 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { transmute(vld2_dup_s16(transmute(a))) } - #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] @@ -11100,7 +10688,6 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { transmute(vld2q_dup_s16(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] @@ -11117,7 +10704,6 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { } _vld2_f32(a as *const i8, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] @@ -11134,7 +10720,6 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { } _vld2q_f32(a as *const i8, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] @@ -11151,7 +10736,6 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { } _vld2_s8(a as *const i8, 1) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] @@ -11168,7 +10752,6 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { } _vld2q_s8(a as *const i8, 1) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] @@ -11185,7 +10768,6 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { } _vld2_s16(a as *const i8, 2) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] @@ -11202,7 +10784,6 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { } _vld2q_s16(a as *const i8, 2) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] @@ -11219,7 +10800,6 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { } _vld2_s32(a as *const i8, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] @@ -11236,7 +10816,6 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { } _vld2q_s32(a as *const i8, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] @@ -11256,7 +10835,6 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { } _vld2_f32(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] @@ -11276,7 +10854,6 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { } _vld2q_f32(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] @@ -11296,7 +10873,6 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { } _vld2_s8(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] @@ -11316,7 +10892,6 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { } _vld2q_s8(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] @@ -11336,7 +10911,6 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { } _vld2_s16(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] @@ -11356,7 +10930,6 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { } _vld2q_s16(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] @@ -11376,7 +10949,6 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { } _vld2_s32(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] @@ -11396,7 +10968,6 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { } _vld2q_s32(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] @@ -11418,7 +10989,6 @@ pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> } _vld2_lane_f32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] @@ -11441,7 +11011,6 @@ pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) - } _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] @@ -11463,7 +11032,6 @@ pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8 } _vld2_lane_s8(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] @@ -11485,7 +11053,6 @@ pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> i } _vld2_lane_s16(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] @@ -11507,7 +11074,6 @@ pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> } _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] @@ -11529,7 +11095,6 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i } _vld2_lane_s32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] @@ -11551,7 +11116,6 @@ pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> } _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] @@ -11576,7 +11140,6 @@ pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> } _vld2_lane_f32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] @@ -11601,7 +11164,6 @@ pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) - } _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] @@ -11626,7 +11188,6 @@ pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> } _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] @@ -11651,7 +11212,6 @@ pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> } _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] @@ -11671,7 +11231,6 @@ pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8 } _vld2_lane_s8(a as _, b.0, b.1, LANE, 1) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] @@ -11696,7 +11255,6 @@ pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> i } _vld2_lane_s16(a as _, b.0, b.1, LANE, 2) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] @@ -11721,7 +11279,6 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i } _vld2_lane_s32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] #[doc = "## Safety"] @@ -11747,7 +11304,6 @@ pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uin static_assert_uimm_bits!(LANE, 3); transmute(vld2_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] #[doc = "## Safety"] @@ -11773,7 +11329,6 @@ pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld2_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] #[doc = "## Safety"] @@ -11799,7 +11354,6 @@ pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> static_assert_uimm_bits!(LANE, 3); transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] #[doc = "## Safety"] @@ -11825,7 +11379,6 @@ pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld2_lane_s32::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] #[doc = "## Safety"] @@ -11851,7 +11404,6 @@ pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld2q_lane_s32::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] #[doc = "## Safety"] @@ -11877,7 +11429,6 @@ pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> pol static_assert_uimm_bits!(LANE, 3); transmute(vld2_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] #[doc = "## Safety"] @@ -11903,7 +11454,6 @@ pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld2_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] #[doc = "## Safety"] @@ -11929,7 +11479,6 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> static_assert_uimm_bits!(LANE, 3); transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] #[doc = "## Safety"] @@ -11953,7 +11502,6 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { transmute(vld2_s64(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] @@ -11970,7 +11518,6 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { } _vld2_s64(a as *const i8, 8) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] @@ -11990,7 +11537,6 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { } _vld2_s64(a as _) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] #[doc = "## Safety"] @@ -12014,7 +11560,6 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { transmute(vld2_s64(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] @@ -12038,7 +11583,6 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { transmute(vld2_s8(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] @@ -12062,7 +11606,6 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { transmute(vld2q_s8(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] @@ -12086,7 +11629,6 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { transmute(vld2_s16(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] @@ -12110,7 +11652,6 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { transmute(vld2q_s16(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] @@ -12134,7 +11675,6 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { transmute(vld2_s32(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] @@ -12158,7 +11698,6 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { transmute(vld2q_s32(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] @@ -12182,7 +11721,6 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { transmute(vld2_s8(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] @@ -12206,7 +11744,6 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { transmute(vld2q_s8(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] @@ -12230,7 +11767,6 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { transmute(vld2_s16(transmute(a))) } - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] @@ -12254,7 +11790,6 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { transmute(vld2q_s16(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] @@ -12274,7 +11809,6 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { } _vld3_dup_f32(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] @@ -12294,7 +11828,6 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { } _vld3q_dup_f32(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] @@ -12314,7 +11847,6 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { } _vld3_dup_s8(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] @@ -12334,7 +11866,6 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { } _vld3q_dup_s8(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] @@ -12354,7 +11885,6 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { } _vld3_dup_s16(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] @@ -12374,7 +11904,6 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { } _vld3q_dup_s16(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] @@ -12394,7 +11923,6 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { } _vld3_dup_s32(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] @@ -12414,7 +11942,6 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { } _vld3q_dup_s32(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] @@ -12434,7 +11961,6 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { } _vld3_dup_s64(a as _) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] @@ -12451,7 +11977,6 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { } _vld3_dup_f32(a as *const i8, 4) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] @@ -12468,7 +11993,6 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { } _vld3q_dup_f32(a as *const i8, 4) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] @@ -12485,7 +12009,6 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { } _vld3_dup_s8(a as *const i8, 1) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] @@ -12502,7 +12025,6 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { } _vld3q_dup_s8(a as *const i8, 1) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] @@ -12519,7 +12041,6 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { } _vld3_dup_s16(a as *const i8, 2) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] @@ -12536,7 +12057,6 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { } _vld3q_dup_s16(a as *const i8, 2) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] @@ -12553,7 +12073,6 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { } _vld3_dup_s32(a as *const i8, 4) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] @@ -12570,7 +12089,6 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { } _vld3q_dup_s32(a as *const i8, 4) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] #[doc = "## Safety"] @@ -12594,7 +12112,6 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { transmute(vld3_dup_s64(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] @@ -12611,7 +12128,6 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { } _vld3_dup_s64(a as *const i8, 8) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] #[doc = "## Safety"] @@ -12635,7 +12151,6 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { transmute(vld3_dup_s64(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] @@ -12659,7 +12174,6 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { transmute(vld3_dup_s8(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] @@ -12683,7 +12197,6 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { transmute(vld3q_dup_s8(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] @@ -12707,7 +12220,6 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { transmute(vld3_dup_s16(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] @@ -12731,7 +12243,6 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { transmute(vld3q_dup_s16(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] @@ -12755,7 +12266,6 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { transmute(vld3_dup_s32(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] @@ -12779,7 +12289,6 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { transmute(vld3q_dup_s32(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] @@ -12803,7 +12312,6 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { transmute(vld3_dup_s8(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] @@ -12827,7 +12335,6 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { transmute(vld3q_dup_s8(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] @@ -12851,7 +12358,6 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { transmute(vld3_dup_s16(transmute(a))) } - #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] @@ -12875,7 +12381,6 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { transmute(vld3q_dup_s16(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] @@ -12895,7 +12400,6 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { } _vld3_f32(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] @@ -12915,7 +12419,6 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { } _vld3q_f32(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] @@ -12935,7 +12438,6 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { } _vld3_s8(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] @@ -12955,7 +12457,6 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { } _vld3q_s8(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] @@ -12975,7 +12476,6 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { } _vld3_s16(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] @@ -12995,7 +12495,6 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { } _vld3q_s16(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] @@ -13015,7 +12514,6 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { } _vld3_s32(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] @@ -13035,7 +12533,6 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { } _vld3q_s32(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] @@ -13052,7 +12549,6 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { } _vld3_f32(a as *const i8, 4) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] @@ -13069,7 +12565,6 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { } _vld3q_f32(a as *const i8, 4) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] @@ -13086,7 +12581,6 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { } _vld3_s8(a as *const i8, 1) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] @@ -13103,7 +12597,6 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { } _vld3q_s8(a as *const i8, 1) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] @@ -13120,7 +12613,6 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { } _vld3_s16(a as *const i8, 2) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] @@ -13137,7 +12629,6 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { } _vld3q_s16(a as *const i8, 2) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] @@ -13154,7 +12645,6 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { } _vld3_s32(a as *const i8, 4) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] @@ -13171,7 +12661,6 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { } _vld3q_s32(a as *const i8, 4) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] @@ -13199,7 +12688,6 @@ pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> } _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] @@ -13227,7 +12715,6 @@ pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) - } _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] @@ -13253,7 +12740,6 @@ pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> } _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] @@ -13281,7 +12767,6 @@ pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8 } _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] @@ -13309,7 +12794,6 @@ pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> i } _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] @@ -13337,7 +12821,6 @@ pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> } _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] @@ -13365,7 +12848,6 @@ pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> i } _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] @@ -13393,7 +12875,6 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> } _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] @@ -13419,7 +12900,6 @@ pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8 } _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] @@ -13445,7 +12925,6 @@ pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> i } _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] @@ -13471,7 +12950,6 @@ pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> } _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] @@ -13497,7 +12975,6 @@ pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> i } _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] @@ -13523,7 +13000,6 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> } _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] #[doc = "## Safety"] @@ -13549,7 +13025,6 @@ pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uin static_assert_uimm_bits!(LANE, 3); transmute(vld3_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] #[doc = "## Safety"] @@ -13575,7 +13050,6 @@ pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld3_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] #[doc = "## Safety"] @@ -13601,7 +13075,6 @@ pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> static_assert_uimm_bits!(LANE, 3); transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] #[doc = "## Safety"] @@ -13627,7 +13100,6 @@ pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld3_lane_s32::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] #[doc = "## Safety"] @@ -13653,7 +13125,6 @@ pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld3q_lane_s32::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] #[doc = "## Safety"] @@ -13679,7 +13150,6 @@ pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> pol static_assert_uimm_bits!(LANE, 3); transmute(vld3_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] #[doc = "## Safety"] @@ -13705,7 +13175,6 @@ pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld3_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] #[doc = "## Safety"] @@ -13731,7 +13200,6 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> static_assert_uimm_bits!(LANE, 3); transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] #[doc = "## Safety"] @@ -13755,7 +13223,6 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { transmute(vld3_s64(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] @@ -13775,7 +13242,6 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { } _vld3_s64(a as _) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] @@ -13792,7 +13258,6 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { } _vld3_s64(a as *const i8, 8) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] #[doc = "## Safety"] @@ -13816,7 +13281,6 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { transmute(vld3_s64(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] #[doc = "## Safety"] @@ -13840,7 +13304,6 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { transmute(vld3_s8(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] @@ -13864,7 +13327,6 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { transmute(vld3q_s8(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] @@ -13888,7 +13350,6 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { transmute(vld3_s16(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] @@ -13912,7 +13373,6 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { transmute(vld3q_s16(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] @@ -13936,7 +13396,6 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { transmute(vld3_s32(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] @@ -13960,7 +13419,6 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { transmute(vld3q_s32(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] @@ -13984,7 +13442,6 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { transmute(vld3_s8(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] @@ -14008,7 +13465,6 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { transmute(vld3q_s8(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] @@ -14032,7 +13488,6 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { transmute(vld3_s16(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] @@ -14056,7 +13511,6 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { transmute(vld3q_s16(transmute(a))) } - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] @@ -14082,7 +13536,6 @@ pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) - } _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] @@ -14099,7 +13552,6 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { } _vld4_dup_f32(a as *const i8, 4) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] @@ -14116,7 +13568,6 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { } _vld4q_dup_f32(a as *const i8, 4) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] @@ -14133,7 +13584,6 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { } _vld4_dup_s8(a as *const i8, 1) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] @@ -14150,7 +13600,6 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { } _vld4q_dup_s8(a as *const i8, 1) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] @@ -14167,7 +13616,6 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { } _vld4_dup_s16(a as *const i8, 2) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] @@ -14184,7 +13632,6 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { } _vld4q_dup_s16(a as *const i8, 2) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] @@ -14201,7 +13648,6 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { } _vld4_dup_s32(a as *const i8, 4) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] @@ -14218,7 +13664,6 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { } _vld4q_dup_s32(a as *const i8, 4) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] @@ -14238,7 +13683,6 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { } _vld4_dup_f32(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] @@ -14258,7 +13702,6 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { } _vld4q_dup_f32(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] @@ -14278,7 +13721,6 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { } _vld4_dup_s8(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] @@ -14298,7 +13740,6 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { } _vld4q_dup_s8(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] @@ -14318,7 +13759,6 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { } _vld4_dup_s16(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] @@ -14338,7 +13778,6 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { } _vld4q_dup_s16(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] @@ -14358,7 +13797,6 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { } _vld4_dup_s32(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] @@ -14378,7 +13816,6 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { } _vld4q_dup_s32(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] @@ -14398,7 +13835,6 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { } _vld4_dup_s64(a as _) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] #[doc = "## Safety"] @@ -14422,7 +13858,6 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { transmute(vld4_dup_s64(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] @@ -14439,7 +13874,6 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { } _vld4_dup_s64(a as *const i8, 8) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] #[doc = "## Safety"] @@ -14463,7 +13897,6 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { transmute(vld4_dup_s64(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] #[doc = "## Safety"] @@ -14487,7 +13920,6 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { transmute(vld4_dup_s8(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] #[doc = "## Safety"] @@ -14511,7 +13943,6 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { transmute(vld4q_dup_s8(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] #[doc = "## Safety"] @@ -14535,7 +13966,6 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { transmute(vld4_dup_s16(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] #[doc = "## Safety"] @@ -14559,7 +13989,6 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { transmute(vld4q_dup_s16(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] #[doc = "## Safety"] @@ -14583,7 +14012,6 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { transmute(vld4_dup_s32(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] #[doc = "## Safety"] @@ -14607,7 +14035,6 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { transmute(vld4q_dup_s32(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] #[doc = "## Safety"] @@ -14631,7 +14058,6 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { transmute(vld4_dup_s8(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] #[doc = "## Safety"] @@ -14655,7 +14081,6 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { transmute(vld4q_dup_s8(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] #[doc = "## Safety"] @@ -14679,7 +14104,6 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { transmute(vld4_dup_s16(transmute(a))) } - #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] #[doc = "## Safety"] @@ -14703,7 +14127,6 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { transmute(vld4q_dup_s16(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] @@ -14723,7 +14146,6 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { } _vld4_f32(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] @@ -14743,7 +14165,6 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { } _vld4q_f32(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] @@ -14763,7 +14184,6 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { } _vld4_s8(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] @@ -14783,7 +14203,6 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { } _vld4q_s8(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] @@ -14803,7 +14222,6 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { } _vld4_s16(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] @@ -14823,7 +14241,6 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { } _vld4q_s16(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] @@ -14843,7 +14260,6 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { } _vld4_s32(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] @@ -14863,7 +14279,6 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { } _vld4q_s32(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] @@ -14880,7 +14295,6 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { } _vld4_f32(a as *const i8, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] @@ -14897,7 +14311,6 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { } _vld4q_f32(a as *const i8, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] @@ -14914,7 +14327,6 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { } _vld4_s8(a as *const i8, 1) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] @@ -14931,7 +14343,6 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { } _vld4q_s8(a as *const i8, 1) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] @@ -14948,7 +14359,6 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { } _vld4_s16(a as *const i8, 2) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] @@ -14965,7 +14375,6 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { } _vld4q_s16(a as *const i8, 2) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] @@ -14982,7 +14391,6 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { } _vld4_s32(a as *const i8, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] @@ -14999,7 +14407,6 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { } _vld4q_s32(a as *const i8, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] #[doc = "## Safety"] @@ -15028,7 +14435,6 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> } _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] #[doc = "## Safety"] @@ -15057,7 +14463,6 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - } _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] #[doc = "## Safety"] @@ -15086,7 +14491,6 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 } _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] #[doc = "## Safety"] @@ -15115,7 +14519,6 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i } _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] #[doc = "## Safety"] @@ -15144,7 +14547,6 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> } _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] #[doc = "## Safety"] @@ -15173,7 +14575,6 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i } _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] #[doc = "## Safety"] @@ -15202,7 +14603,6 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> } _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] #[doc = "## Safety"] @@ -15229,7 +14629,6 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> } _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] #[doc = "## Safety"] @@ -15256,7 +14655,6 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - } _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] #[doc = "## Safety"] @@ -15283,7 +14681,6 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 } _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] #[doc = "## Safety"] @@ -15310,7 +14707,6 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i } _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] #[doc = "## Safety"] @@ -15337,7 +14733,6 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> } _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] #[doc = "## Safety"] @@ -15364,7 +14759,6 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i } _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] #[doc = "## Safety"] @@ -15391,7 +14785,6 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> } _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] #[doc = "## Safety"] @@ -15417,7 +14810,6 @@ pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uin static_assert_uimm_bits!(LANE, 3); transmute(vld4_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] #[doc = "## Safety"] @@ -15443,7 +14835,6 @@ pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld4_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] #[doc = "## Safety"] @@ -15469,7 +14860,6 @@ pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> static_assert_uimm_bits!(LANE, 3); transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] #[doc = "## Safety"] @@ -15495,7 +14885,6 @@ pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> static_assert_uimm_bits!(LANE, 1); transmute(vld4_lane_s32::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] #[doc = "## Safety"] @@ -15521,7 +14910,6 @@ pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld4q_lane_s32::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] #[doc = "## Safety"] @@ -15547,7 +14935,6 @@ pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> pol static_assert_uimm_bits!(LANE, 3); transmute(vld4_lane_s8::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] #[doc = "## Safety"] @@ -15573,7 +14960,6 @@ pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> static_assert_uimm_bits!(LANE, 2); transmute(vld4_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] #[doc = "## Safety"] @@ -15599,7 +14985,6 @@ pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> static_assert_uimm_bits!(LANE, 3); transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] #[doc = "## Safety"] @@ -15623,7 +15008,6 @@ pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { transmute(vld4_s64(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] #[doc = "## Safety"] @@ -15643,7 +15027,6 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { } _vld4_s64(a as _) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] #[doc = "## Safety"] @@ -15660,7 +15043,6 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { } _vld4_s64(a as *const i8, 8) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] #[doc = "## Safety"] @@ -15684,7 +15066,6 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { transmute(vld4_s64(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] #[doc = "## Safety"] @@ -15708,7 +15089,6 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { transmute(vld4_s8(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] @@ -15732,7 +15112,6 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { transmute(vld4q_s8(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] @@ -15756,7 +15135,6 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { transmute(vld4_s16(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] @@ -15780,7 +15158,6 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { transmute(vld4q_s16(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] @@ -15804,7 +15181,6 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { transmute(vld4_s32(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] @@ -15828,7 +15204,6 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { transmute(vld4q_s32(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] @@ -15852,7 +15227,6 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { transmute(vld4_s8(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] @@ -15876,7 +15250,6 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { transmute(vld4q_s8(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] @@ -15900,7 +15273,6 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { transmute(vld4_s16(transmute(a))) } - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] @@ -15924,7 +15296,6 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { transmute(vld4q_s16(transmute(a))) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] #[doc = "## Safety"] @@ -15956,7 +15327,6 @@ pub unsafe fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vmax_f32(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] #[doc = "## Safety"] @@ -15988,7 +15358,6 @@ pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vmaxq_f32(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] #[doc = "## Safety"] @@ -16020,7 +15389,6 @@ pub unsafe fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vmax_s8(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] #[doc = "## Safety"] @@ -16052,7 +15420,6 @@ pub unsafe fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vmaxq_s8(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] #[doc = "## Safety"] @@ -16084,7 +15451,6 @@ pub unsafe fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vmax_s16(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] #[doc = "## Safety"] @@ -16116,7 +15482,6 @@ pub unsafe fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vmaxq_s16(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] #[doc = "## Safety"] @@ -16148,7 +15513,6 @@ pub unsafe fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vmax_s32(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] #[doc = "## Safety"] @@ -16180,7 +15544,6 @@ pub unsafe fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vmaxq_s32(a, b) } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] #[doc = "## Safety"] @@ -16212,7 +15575,6 @@ pub unsafe fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vmax_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] #[doc = "## Safety"] @@ -16244,7 +15606,6 @@ pub unsafe fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vmaxq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] #[doc = "## Safety"] @@ -16276,7 +15637,6 @@ pub unsafe fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vmax_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] #[doc = "## Safety"] @@ -16308,7 +15668,6 @@ pub unsafe fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vmaxq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] #[doc = "## Safety"] @@ -16340,7 +15699,6 @@ pub unsafe fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vmax_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] #[doc = "## Safety"] @@ -16372,7 +15730,6 @@ pub unsafe fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vmaxq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] #[doc = "## Safety"] @@ -16404,7 +15761,6 @@ pub unsafe fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vmaxnm_f32(a, b) } - #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] #[doc = "## Safety"] @@ -16436,7 +15792,6 @@ pub unsafe fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vmaxnmq_f32(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] #[doc = "## Safety"] @@ -16468,7 +15823,6 @@ pub unsafe fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vmin_f32(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] #[doc = "## Safety"] @@ -16500,7 +15854,6 @@ pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vminq_f32(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] #[doc = "## Safety"] @@ -16532,7 +15885,6 @@ pub unsafe fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vmin_s8(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] #[doc = "## Safety"] @@ -16564,7 +15916,6 @@ pub unsafe fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vminq_s8(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] #[doc = "## Safety"] @@ -16596,7 +15947,6 @@ pub unsafe fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vmin_s16(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] #[doc = "## Safety"] @@ -16628,7 +15978,6 @@ pub unsafe fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vminq_s16(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] #[doc = "## Safety"] @@ -16660,7 +16009,6 @@ pub unsafe fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vmin_s32(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] #[doc = "## Safety"] @@ -16692,7 +16040,6 @@ pub unsafe fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vminq_s32(a, b) } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] #[doc = "## Safety"] @@ -16724,7 +16071,6 @@ pub unsafe fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vmin_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] #[doc = "## Safety"] @@ -16756,7 +16102,6 @@ pub unsafe fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vminq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] #[doc = "## Safety"] @@ -16788,7 +16133,6 @@ pub unsafe fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vmin_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] #[doc = "## Safety"] @@ -16820,7 +16164,6 @@ pub unsafe fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vminq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] #[doc = "## Safety"] @@ -16852,7 +16195,6 @@ pub unsafe fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vmin_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] #[doc = "## Safety"] @@ -16884,7 +16226,6 @@ pub unsafe fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vminq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] #[doc = "## Safety"] @@ -16916,7 +16257,6 @@ pub unsafe fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vminnm_f32(a, b) } - #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] #[doc = "## Safety"] @@ -16948,7 +16288,6 @@ pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vminnmq_f32(a, b) } - #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] #[doc = "## Safety"] @@ -16972,7 +16311,6 @@ pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] #[doc = "## Safety"] @@ -16996,7 +16334,6 @@ pub unsafe fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 pub unsafe fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] #[doc = "## Safety"] @@ -17026,7 +16363,6 @@ pub unsafe fn vmla_lane_f32( static_assert_uimm_bits!(LANE, 1); vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] #[doc = "## Safety"] @@ -17056,7 +16392,6 @@ pub unsafe fn vmla_laneq_f32( static_assert_uimm_bits!(LANE, 2); vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] #[doc = "## Safety"] @@ -17090,7 +16425,6 @@ pub unsafe fn vmlaq_lane_f32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] #[doc = "## Safety"] @@ -17124,7 +16458,6 @@ pub unsafe fn vmlaq_laneq_f32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] #[doc = "## Safety"] @@ -17158,7 +16491,6 @@ pub unsafe fn vmla_lane_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] #[doc = "## Safety"] @@ -17192,7 +16524,6 @@ pub unsafe fn vmla_lane_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] #[doc = "## Safety"] @@ -17226,7 +16557,6 @@ pub unsafe fn vmla_laneq_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] #[doc = "## Safety"] @@ -17260,7 +16590,6 @@ pub unsafe fn vmla_laneq_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] #[doc = "## Safety"] @@ -17307,7 +16636,6 @@ pub unsafe fn vmlaq_lane_s16( ), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] #[doc = "## Safety"] @@ -17354,7 +16682,6 @@ pub unsafe fn vmlaq_lane_u16( ), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] #[doc = "## Safety"] @@ -17401,7 +16728,6 @@ pub unsafe fn vmlaq_laneq_s16( ), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] #[doc = "## Safety"] @@ -17448,7 +16774,6 @@ pub unsafe fn vmlaq_laneq_u16( ), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] #[doc = "## Safety"] @@ -17478,7 +16803,6 @@ pub unsafe fn vmla_lane_s32( static_assert_uimm_bits!(LANE, 1); vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] #[doc = "## Safety"] @@ -17508,7 +16832,6 @@ pub unsafe fn vmla_lane_u32( static_assert_uimm_bits!(LANE, 1); vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] #[doc = "## Safety"] @@ -17538,7 +16861,6 @@ pub unsafe fn vmla_laneq_s32( static_assert_uimm_bits!(LANE, 2); vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] #[doc = "## Safety"] @@ -17568,7 +16890,6 @@ pub unsafe fn vmla_laneq_u32( static_assert_uimm_bits!(LANE, 2); vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] #[doc = "## Safety"] @@ -17602,7 +16923,6 @@ pub unsafe fn vmlaq_lane_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] #[doc = "## Safety"] @@ -17636,7 +16956,6 @@ pub unsafe fn vmlaq_lane_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"] #[doc = "## Safety"] @@ -17670,7 +16989,6 @@ pub unsafe fn vmlaq_laneq_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"] #[doc = "## Safety"] @@ -17704,7 +17022,6 @@ pub unsafe fn vmlaq_laneq_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"] #[doc = "## Safety"] @@ -17728,7 +17045,6 @@ pub unsafe fn vmlaq_laneq_u32( pub unsafe fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vmla_f32(a, b, vdup_n_f32(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"] #[doc = "## Safety"] @@ -17752,7 +17068,6 @@ pub unsafe fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t pub unsafe fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vmlaq_f32(a, b, vdupq_n_f32(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"] #[doc = "## Safety"] @@ -17776,7 +17091,6 @@ pub unsafe fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t pub unsafe fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { vmla_s16(a, b, vdup_n_s16(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"] #[doc = "## Safety"] @@ -17800,7 +17114,6 @@ pub unsafe fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { pub unsafe fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { vmlaq_s16(a, b, vdupq_n_s16(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"] #[doc = "## Safety"] @@ -17824,7 +17137,6 @@ pub unsafe fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { pub unsafe fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { vmla_u16(a, b, vdup_n_u16(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"] #[doc = "## Safety"] @@ -17848,7 +17160,6 @@ pub unsafe fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { pub unsafe fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { vmlaq_u16(a, b, vdupq_n_u16(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"] #[doc = "## Safety"] @@ -17872,7 +17183,6 @@ pub unsafe fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { pub unsafe fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { vmla_s32(a, b, vdup_n_s32(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"] #[doc = "## Safety"] @@ -17896,7 +17206,6 @@ pub unsafe fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { pub unsafe fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { vmlaq_s32(a, b, vdupq_n_s32(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"] #[doc = "## Safety"] @@ -17920,7 +17229,6 @@ pub unsafe fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { pub unsafe fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { vmla_u32(a, b, vdup_n_u32(c)) } - #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"] #[doc = "## Safety"] @@ -17944,7 +17252,6 @@ pub unsafe fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { pub unsafe fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { vmlaq_u32(a, b, vdupq_n_u32(c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"] #[doc = "## Safety"] @@ -17968,7 +17275,6 @@ pub unsafe fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { pub unsafe fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"] #[doc = "## Safety"] @@ -17992,7 +17298,6 @@ pub unsafe fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { pub unsafe fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"] #[doc = "## Safety"] @@ -18016,7 +17321,6 @@ pub unsafe fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { pub unsafe fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"] #[doc = "## Safety"] @@ -18040,7 +17344,6 @@ pub unsafe fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { pub unsafe fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"] #[doc = "## Safety"] @@ -18064,7 +17367,6 @@ pub unsafe fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { pub unsafe fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"] #[doc = "## Safety"] @@ -18088,7 +17390,6 @@ pub unsafe fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { pub unsafe fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"] #[doc = "## Safety"] @@ -18112,7 +17413,6 @@ pub unsafe fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { pub unsafe fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"] #[doc = "## Safety"] @@ -18136,7 +17436,6 @@ pub unsafe fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { pub unsafe fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"] #[doc = "## Safety"] @@ -18160,7 +17459,6 @@ pub unsafe fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_ pub unsafe fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"] #[doc = "## Safety"] @@ -18184,7 +17482,6 @@ pub unsafe fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_ pub unsafe fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"] #[doc = "## Safety"] @@ -18208,7 +17505,6 @@ pub unsafe fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8 pub unsafe fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"] #[doc = "## Safety"] @@ -18232,7 +17528,6 @@ pub unsafe fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_ pub unsafe fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { simd_add(a, simd_mul(b, c)) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"] #[doc = "## Safety"] @@ -18266,7 +17561,6 @@ pub unsafe fn vmlal_lane_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"] #[doc = "## Safety"] @@ -18300,7 +17594,6 @@ pub unsafe fn vmlal_laneq_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"] #[doc = "## Safety"] @@ -18330,7 +17623,6 @@ pub unsafe fn vmlal_lane_s32( static_assert_uimm_bits!(LANE, 1); vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"] #[doc = "## Safety"] @@ -18360,7 +17652,6 @@ pub unsafe fn vmlal_laneq_s32( static_assert_uimm_bits!(LANE, 2); vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"] #[doc = "## Safety"] @@ -18394,7 +17685,6 @@ pub unsafe fn vmlal_lane_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"] #[doc = "## Safety"] @@ -18428,7 +17718,6 @@ pub unsafe fn vmlal_laneq_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"] #[doc = "## Safety"] @@ -18458,7 +17747,6 @@ pub unsafe fn vmlal_lane_u32( static_assert_uimm_bits!(LANE, 1); vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"] #[doc = "## Safety"] @@ -18488,7 +17776,6 @@ pub unsafe fn vmlal_laneq_u32( static_assert_uimm_bits!(LANE, 2); vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"] #[doc = "## Safety"] @@ -18512,7 +17799,6 @@ pub unsafe fn vmlal_laneq_u32( pub unsafe fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vmlal_s16(a, b, vdup_n_s16(c)) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"] #[doc = "## Safety"] @@ -18536,7 +17822,6 @@ pub unsafe fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { pub unsafe fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vmlal_s32(a, b, vdup_n_s32(c)) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"] #[doc = "## Safety"] @@ -18560,7 +17845,6 @@ pub unsafe fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { pub unsafe fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { vmlal_u16(a, b, vdup_n_u16(c)) } - #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"] #[doc = "## Safety"] @@ -18584,7 +17868,6 @@ pub unsafe fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { pub unsafe fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { vmlal_u32(a, b, vdup_n_u32(c)) } - #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"] #[doc = "## Safety"] @@ -18608,7 +17891,6 @@ pub unsafe fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { pub unsafe fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { simd_add(a, vmull_s8(b, c)) } - #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"] #[doc = "## Safety"] @@ -18632,7 +17914,6 @@ pub unsafe fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { pub unsafe fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { simd_add(a, vmull_s16(b, c)) } - #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"] #[doc = "## Safety"] @@ -18656,7 +17937,6 @@ pub unsafe fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { pub unsafe fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { simd_add(a, vmull_s32(b, c)) } - #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"] #[doc = "## Safety"] @@ -18680,7 +17960,6 @@ pub unsafe fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { pub unsafe fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { simd_add(a, vmull_u8(b, c)) } - #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"] #[doc = "## Safety"] @@ -18704,7 +17983,6 @@ pub unsafe fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t pub unsafe fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { simd_add(a, vmull_u16(b, c)) } - #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"] #[doc = "## Safety"] @@ -18728,7 +18006,6 @@ pub unsafe fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4 pub unsafe fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { simd_add(a, vmull_u32(b, c)) } - #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"] #[doc = "## Safety"] @@ -18752,7 +18029,6 @@ pub unsafe fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2 pub unsafe fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"] #[doc = "## Safety"] @@ -18776,7 +18052,6 @@ pub unsafe fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 pub unsafe fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"] #[doc = "## Safety"] @@ -18806,7 +18081,6 @@ pub unsafe fn vmls_lane_f32( static_assert_uimm_bits!(LANE, 1); vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"] #[doc = "## Safety"] @@ -18836,7 +18110,6 @@ pub unsafe fn vmls_laneq_f32( static_assert_uimm_bits!(LANE, 2); vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"] #[doc = "## Safety"] @@ -18870,7 +18143,6 @@ pub unsafe fn vmlsq_lane_f32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"] #[doc = "## Safety"] @@ -18904,7 +18176,6 @@ pub unsafe fn vmlsq_laneq_f32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"] #[doc = "## Safety"] @@ -18938,7 +18209,6 @@ pub unsafe fn vmls_lane_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"] #[doc = "## Safety"] @@ -18972,7 +18242,6 @@ pub unsafe fn vmls_lane_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"] #[doc = "## Safety"] @@ -19006,7 +18275,6 @@ pub unsafe fn vmls_laneq_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"] #[doc = "## Safety"] @@ -19040,7 +18308,6 @@ pub unsafe fn vmls_laneq_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"] #[doc = "## Safety"] @@ -19087,7 +18354,6 @@ pub unsafe fn vmlsq_lane_s16( ), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"] #[doc = "## Safety"] @@ -19134,7 +18400,6 @@ pub unsafe fn vmlsq_lane_u16( ), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"] #[doc = "## Safety"] @@ -19181,7 +18446,6 @@ pub unsafe fn vmlsq_laneq_s16( ), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"] #[doc = "## Safety"] @@ -19228,7 +18492,6 @@ pub unsafe fn vmlsq_laneq_u16( ), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"] #[doc = "## Safety"] @@ -19258,7 +18521,6 @@ pub unsafe fn vmls_lane_s32( static_assert_uimm_bits!(LANE, 1); vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"] #[doc = "## Safety"] @@ -19288,7 +18550,6 @@ pub unsafe fn vmls_lane_u32( static_assert_uimm_bits!(LANE, 1); vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"] #[doc = "## Safety"] @@ -19318,7 +18579,6 @@ pub unsafe fn vmls_laneq_s32( static_assert_uimm_bits!(LANE, 2); vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"] #[doc = "## Safety"] @@ -19348,7 +18608,6 @@ pub unsafe fn vmls_laneq_u32( static_assert_uimm_bits!(LANE, 2); vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"] #[doc = "## Safety"] @@ -19382,7 +18641,6 @@ pub unsafe fn vmlsq_lane_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"] #[doc = "## Safety"] @@ -19416,7 +18674,6 @@ pub unsafe fn vmlsq_lane_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"] #[doc = "## Safety"] @@ -19450,7 +18707,6 @@ pub unsafe fn vmlsq_laneq_s32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"] #[doc = "## Safety"] @@ -19484,7 +18740,6 @@ pub unsafe fn vmlsq_laneq_u32( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"] #[doc = "## Safety"] @@ -19508,7 +18763,6 @@ pub unsafe fn vmlsq_laneq_u32( pub unsafe fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vmls_f32(a, b, vdup_n_f32(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"] #[doc = "## Safety"] @@ -19532,7 +18786,6 @@ pub unsafe fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t pub unsafe fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vmlsq_f32(a, b, vdupq_n_f32(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"] #[doc = "## Safety"] @@ -19556,7 +18809,6 @@ pub unsafe fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t pub unsafe fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { vmls_s16(a, b, vdup_n_s16(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"] #[doc = "## Safety"] @@ -19580,7 +18832,6 @@ pub unsafe fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { pub unsafe fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { vmlsq_s16(a, b, vdupq_n_s16(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"] #[doc = "## Safety"] @@ -19604,7 +18855,6 @@ pub unsafe fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { pub unsafe fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { vmls_u16(a, b, vdup_n_u16(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"] #[doc = "## Safety"] @@ -19628,7 +18878,6 @@ pub unsafe fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { pub unsafe fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { vmlsq_u16(a, b, vdupq_n_u16(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"] #[doc = "## Safety"] @@ -19652,7 +18901,6 @@ pub unsafe fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { pub unsafe fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { vmls_s32(a, b, vdup_n_s32(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"] #[doc = "## Safety"] @@ -19676,7 +18924,6 @@ pub unsafe fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { pub unsafe fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { vmlsq_s32(a, b, vdupq_n_s32(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"] #[doc = "## Safety"] @@ -19700,7 +18947,6 @@ pub unsafe fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { pub unsafe fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { vmls_u32(a, b, vdup_n_u32(c)) } - #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"] #[doc = "## Safety"] @@ -19724,7 +18970,6 @@ pub unsafe fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { pub unsafe fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { vmlsq_u32(a, b, vdupq_n_u32(c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"] #[doc = "## Safety"] @@ -19748,7 +18993,6 @@ pub unsafe fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { pub unsafe fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"] #[doc = "## Safety"] @@ -19772,7 +19016,6 @@ pub unsafe fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { pub unsafe fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"] #[doc = "## Safety"] @@ -19796,7 +19039,6 @@ pub unsafe fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { pub unsafe fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"] #[doc = "## Safety"] @@ -19820,7 +19062,6 @@ pub unsafe fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { pub unsafe fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"] #[doc = "## Safety"] @@ -19844,7 +19085,6 @@ pub unsafe fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { pub unsafe fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"] #[doc = "## Safety"] @@ -19868,7 +19108,6 @@ pub unsafe fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { pub unsafe fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"] #[doc = "## Safety"] @@ -19892,7 +19131,6 @@ pub unsafe fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { pub unsafe fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"] #[doc = "## Safety"] @@ -19916,7 +19154,6 @@ pub unsafe fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { pub unsafe fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"] #[doc = "## Safety"] @@ -19940,7 +19177,6 @@ pub unsafe fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_ pub unsafe fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"] #[doc = "## Safety"] @@ -19964,7 +19200,6 @@ pub unsafe fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_ pub unsafe fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"] #[doc = "## Safety"] @@ -19988,7 +19223,6 @@ pub unsafe fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8 pub unsafe fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"] #[doc = "## Safety"] @@ -20012,7 +19246,6 @@ pub unsafe fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_ pub unsafe fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { simd_sub(a, simd_mul(b, c)) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"] #[doc = "## Safety"] @@ -20046,7 +19279,6 @@ pub unsafe fn vmlsl_lane_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"] #[doc = "## Safety"] @@ -20080,7 +19312,6 @@ pub unsafe fn vmlsl_laneq_s16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"] #[doc = "## Safety"] @@ -20110,7 +19341,6 @@ pub unsafe fn vmlsl_lane_s32( static_assert_uimm_bits!(LANE, 1); vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"] #[doc = "## Safety"] @@ -20140,7 +19370,6 @@ pub unsafe fn vmlsl_laneq_s32( static_assert_uimm_bits!(LANE, 2); vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"] #[doc = "## Safety"] @@ -20174,7 +19403,6 @@ pub unsafe fn vmlsl_lane_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"] #[doc = "## Safety"] @@ -20208,7 +19436,6 @@ pub unsafe fn vmlsl_laneq_u16( simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"] #[doc = "## Safety"] @@ -20238,7 +19465,6 @@ pub unsafe fn vmlsl_lane_u32( static_assert_uimm_bits!(LANE, 1); vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"] #[doc = "## Safety"] @@ -20268,7 +19494,6 @@ pub unsafe fn vmlsl_laneq_u32( static_assert_uimm_bits!(LANE, 2); vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"] #[doc = "## Safety"] @@ -20292,7 +19517,6 @@ pub unsafe fn vmlsl_laneq_u32( pub unsafe fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vmlsl_s16(a, b, vdup_n_s16(c)) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"] #[doc = "## Safety"] @@ -20316,7 +19540,6 @@ pub unsafe fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { pub unsafe fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vmlsl_s32(a, b, vdup_n_s32(c)) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"] #[doc = "## Safety"] @@ -20340,7 +19563,6 @@ pub unsafe fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { pub unsafe fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { vmlsl_u16(a, b, vdup_n_u16(c)) } - #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"] #[doc = "## Safety"] @@ -20364,7 +19586,6 @@ pub unsafe fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { pub unsafe fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { vmlsl_u32(a, b, vdup_n_u32(c)) } - #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"] #[doc = "## Safety"] @@ -20388,7 +19609,6 @@ pub unsafe fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { pub unsafe fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { simd_sub(a, vmull_s8(b, c)) } - #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"] #[doc = "## Safety"] @@ -20412,7 +19632,6 @@ pub unsafe fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { pub unsafe fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { simd_sub(a, vmull_s16(b, c)) } - #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"] #[doc = "## Safety"] @@ -20436,7 +19655,6 @@ pub unsafe fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { pub unsafe fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { simd_sub(a, vmull_s32(b, c)) } - #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"] #[doc = "## Safety"] @@ -20460,7 +19678,6 @@ pub unsafe fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { pub unsafe fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { simd_sub(a, vmull_u8(b, c)) } - #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"] #[doc = "## Safety"] @@ -20484,7 +19701,6 @@ pub unsafe fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t pub unsafe fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { simd_sub(a, vmull_u16(b, c)) } - #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"] #[doc = "## Safety"] @@ -20508,7 +19724,6 @@ pub unsafe fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4 pub unsafe fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { simd_sub(a, vmull_u32(b, c)) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"] #[doc = "## Safety"] @@ -20532,7 +19747,6 @@ pub unsafe fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2 pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"] #[doc = "## Safety"] @@ -20556,7 +19770,6 @@ pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_mul(a, b) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"] #[doc = "## Safety"] @@ -20582,7 +19795,6 @@ pub unsafe fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> static_assert_uimm_bits!(LANE, 1); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"] #[doc = "## Safety"] @@ -20608,7 +19820,6 @@ pub unsafe fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> static_assert_uimm_bits!(LANE, 2); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"] #[doc = "## Safety"] @@ -20637,7 +19848,6 @@ pub unsafe fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"] #[doc = "## Safety"] @@ -20666,7 +19876,6 @@ pub unsafe fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"] #[doc = "## Safety"] @@ -20695,7 +19904,6 @@ pub unsafe fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int1 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"] #[doc = "## Safety"] @@ -20737,7 +19945,6 @@ pub unsafe fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int ), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"] #[doc = "## Safety"] @@ -20763,7 +19970,6 @@ pub unsafe fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int3 static_assert_uimm_bits!(LANE, 1); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"] #[doc = "## Safety"] @@ -20792,7 +19998,6 @@ pub unsafe fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"] #[doc = "## Safety"] @@ -20821,7 +20026,6 @@ pub unsafe fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> ui simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"] #[doc = "## Safety"] @@ -20863,7 +20067,6 @@ pub unsafe fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> u ), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"] #[doc = "## Safety"] @@ -20889,7 +20092,6 @@ pub unsafe fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> ui static_assert_uimm_bits!(LANE, 1); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"] #[doc = "## Safety"] @@ -20918,7 +20120,6 @@ pub unsafe fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> u simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"] #[doc = "## Safety"] @@ -20947,7 +20148,6 @@ pub unsafe fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"] #[doc = "## Safety"] @@ -20989,7 +20189,6 @@ pub unsafe fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> in ), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"] #[doc = "## Safety"] @@ -21015,7 +20214,6 @@ pub unsafe fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int static_assert_uimm_bits!(LANE, 2); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"] #[doc = "## Safety"] @@ -21044,7 +20242,6 @@ pub unsafe fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> in simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"] #[doc = "## Safety"] @@ -21073,7 +20270,6 @@ pub unsafe fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> u simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"] #[doc = "## Safety"] @@ -21115,7 +20311,6 @@ pub unsafe fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> ), ) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"] #[doc = "## Safety"] @@ -21141,7 +20336,6 @@ pub unsafe fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> u static_assert_uimm_bits!(LANE, 2); simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"] #[doc = "## Safety"] @@ -21170,7 +20364,6 @@ pub unsafe fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"] #[doc = "## Safety"] @@ -21194,7 +20387,6 @@ pub unsafe fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> pub unsafe fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { simd_mul(a, vdup_n_f32(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"] #[doc = "## Safety"] @@ -21218,7 +20410,6 @@ pub unsafe fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { pub unsafe fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { simd_mul(a, vdupq_n_f32(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"] #[doc = "## Safety"] @@ -21242,7 +20433,6 @@ pub unsafe fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { pub unsafe fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { simd_mul(a, vdup_n_s16(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"] #[doc = "## Safety"] @@ -21266,7 +20456,6 @@ pub unsafe fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { pub unsafe fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { simd_mul(a, vdupq_n_s16(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"] #[doc = "## Safety"] @@ -21290,7 +20479,6 @@ pub unsafe fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { pub unsafe fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { simd_mul(a, vdup_n_s32(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"] #[doc = "## Safety"] @@ -21314,7 +20502,6 @@ pub unsafe fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { pub unsafe fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { simd_mul(a, vdupq_n_s32(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"] #[doc = "## Safety"] @@ -21338,7 +20525,6 @@ pub unsafe fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { pub unsafe fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { simd_mul(a, vdup_n_u16(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"] #[doc = "## Safety"] @@ -21362,7 +20548,6 @@ pub unsafe fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { pub unsafe fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { simd_mul(a, vdupq_n_u16(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"] #[doc = "## Safety"] @@ -21386,7 +20571,6 @@ pub unsafe fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { pub unsafe fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { simd_mul(a, vdup_n_u32(b)) } - #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"] #[doc = "## Safety"] @@ -21410,7 +20594,6 @@ pub unsafe fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { pub unsafe fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { simd_mul(a, vdupq_n_u32(b)) } - #[doc = "Polynomial multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"] #[doc = "## Safety"] @@ -21442,7 +20625,6 @@ pub unsafe fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } _vmul_p8(a, b) } - #[doc = "Polynomial multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"] #[doc = "## Safety"] @@ -21474,7 +20656,6 @@ pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } _vmulq_p8(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"] #[doc = "## Safety"] @@ -21498,7 +20679,6 @@ pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"] #[doc = "## Safety"] @@ -21522,7 +20702,6 @@ pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"] #[doc = "## Safety"] @@ -21546,7 +20725,6 @@ pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"] #[doc = "## Safety"] @@ -21570,7 +20748,6 @@ pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"] #[doc = "## Safety"] @@ -21594,7 +20771,6 @@ pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"] #[doc = "## Safety"] @@ -21618,7 +20794,6 @@ pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"] #[doc = "## Safety"] @@ -21642,7 +20817,6 @@ pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"] #[doc = "## Safety"] @@ -21666,7 +20840,6 @@ pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"] #[doc = "## Safety"] @@ -21690,7 +20863,6 @@ pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"] #[doc = "## Safety"] @@ -21714,7 +20886,6 @@ pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"] #[doc = "## Safety"] @@ -21738,7 +20909,6 @@ pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_mul(a, b) } - #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"] #[doc = "## Safety"] @@ -21762,7 +20932,6 @@ pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_mul(a, b) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"] #[doc = "## Safety"] @@ -21791,7 +20960,6 @@ pub unsafe fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"] #[doc = "## Safety"] @@ -21820,7 +20988,6 @@ pub unsafe fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> in simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"] #[doc = "## Safety"] @@ -21846,7 +21013,6 @@ pub unsafe fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int static_assert_uimm_bits!(LANE, 1); vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"] #[doc = "## Safety"] @@ -21872,7 +21038,6 @@ pub unsafe fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> in static_assert_uimm_bits!(LANE, 2); vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"] #[doc = "## Safety"] @@ -21901,7 +21066,6 @@ pub unsafe fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> u simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"] #[doc = "## Safety"] @@ -21930,7 +21094,6 @@ pub unsafe fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), ) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"] #[doc = "## Safety"] @@ -21956,7 +21119,6 @@ pub unsafe fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> u static_assert_uimm_bits!(LANE, 1); vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"] #[doc = "## Safety"] @@ -21982,7 +21144,6 @@ pub unsafe fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> static_assert_uimm_bits!(LANE, 2); vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } - #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"] #[doc = "## Safety"] @@ -22006,7 +21167,6 @@ pub unsafe fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> pub unsafe fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { vmull_s16(a, vdup_n_s16(b)) } - #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"] #[doc = "## Safety"] @@ -22030,7 +21190,6 @@ pub unsafe fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { pub unsafe fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { vmull_s32(a, vdup_n_s32(b)) } - #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"] #[doc = "## Safety"] @@ -22054,7 +21213,6 @@ pub unsafe fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { pub unsafe fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { vmull_u16(a, vdup_n_u16(b)) } - #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"] #[doc = "## Safety"] @@ -22078,7 +21236,6 @@ pub unsafe fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { pub unsafe fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { vmull_u32(a, vdup_n_u32(b)) } - #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"] #[doc = "## Safety"] @@ -22110,7 +21267,6 @@ pub unsafe fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { } _vmull_p8(a, b) } - #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"] #[doc = "## Safety"] @@ -22142,7 +21298,6 @@ pub unsafe fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } _vmull_s16(a, b) } - #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] #[doc = "## Safety"] @@ -22174,7 +21329,6 @@ pub unsafe fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } _vmull_s32(a, b) } - #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] #[doc = "## Safety"] @@ -22206,7 +21360,6 @@ pub unsafe fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { } _vmull_s8(a, b) } - #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] #[doc = "## Safety"] @@ -22238,7 +21391,6 @@ pub unsafe fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { } _vmull_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] #[doc = "## Safety"] @@ -22270,7 +21422,6 @@ pub unsafe fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { } _vmull_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] #[doc = "## Safety"] @@ -22302,7 +21453,6 @@ pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { } _vmull_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"] #[doc = "## Safety"] @@ -22326,7 +21476,6 @@ pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { pub unsafe fn vneg_f32(a: float32x2_t) -> float32x2_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"] #[doc = "## Safety"] @@ -22350,7 +21499,6 @@ pub unsafe fn vneg_f32(a: float32x2_t) -> float32x2_t { pub unsafe fn vnegq_f32(a: float32x4_t) -> float32x4_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"] #[doc = "## Safety"] @@ -22374,7 +21522,6 @@ pub unsafe fn vnegq_f32(a: float32x4_t) -> float32x4_t { pub unsafe fn vneg_s8(a: int8x8_t) -> int8x8_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"] #[doc = "## Safety"] @@ -22398,7 +21545,6 @@ pub unsafe fn vneg_s8(a: int8x8_t) -> int8x8_t { pub unsafe fn vnegq_s8(a: int8x16_t) -> int8x16_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"] #[doc = "## Safety"] @@ -22422,7 +21568,6 @@ pub unsafe fn vnegq_s8(a: int8x16_t) -> int8x16_t { pub unsafe fn vneg_s16(a: int16x4_t) -> int16x4_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"] #[doc = "## Safety"] @@ -22446,7 +21591,6 @@ pub unsafe fn vneg_s16(a: int16x4_t) -> int16x4_t { pub unsafe fn vnegq_s16(a: int16x8_t) -> int16x8_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"] #[doc = "## Safety"] @@ -22470,7 +21614,6 @@ pub unsafe fn vnegq_s16(a: int16x8_t) -> int16x8_t { pub unsafe fn vneg_s32(a: int32x2_t) -> int32x2_t { simd_neg(a) } - #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"] #[doc = "## Safety"] @@ -22494,7 +21637,6 @@ pub unsafe fn vneg_s32(a: int32x2_t) -> int32x2_t { pub unsafe fn vnegq_s32(a: int32x4_t) -> int32x4_t { simd_neg(a) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"] #[doc = "## Safety"] @@ -22518,7 +21660,6 @@ pub unsafe fn vnegq_s32(a: int32x4_t) -> int32x4_t { pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"] #[doc = "## Safety"] @@ -22542,7 +21683,6 @@ pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"] #[doc = "## Safety"] @@ -22566,7 +21706,6 @@ pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"] #[doc = "## Safety"] @@ -22590,7 +21729,6 @@ pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"] #[doc = "## Safety"] @@ -22614,7 +21752,6 @@ pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"] #[doc = "## Safety"] @@ -22638,7 +21775,6 @@ pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"] #[doc = "## Safety"] @@ -22662,7 +21798,6 @@ pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"] #[doc = "## Safety"] @@ -22686,7 +21821,6 @@ pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"] #[doc = "## Safety"] @@ -22710,7 +21844,6 @@ pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"] #[doc = "## Safety"] @@ -22734,7 +21867,6 @@ pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"] #[doc = "## Safety"] @@ -22758,7 +21890,6 @@ pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"] #[doc = "## Safety"] @@ -22782,7 +21913,6 @@ pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"] #[doc = "## Safety"] @@ -22806,7 +21936,6 @@ pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"] #[doc = "## Safety"] @@ -22830,7 +21959,6 @@ pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"] #[doc = "## Safety"] @@ -22854,7 +21982,6 @@ pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_or(a, b) } - #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"] #[doc = "## Safety"] @@ -22878,7 +22005,6 @@ pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_or(a, b) } - #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] #[doc = "## Safety"] @@ -22910,7 +22036,6 @@ pub unsafe fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vpadd_f32(a, b) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"] #[doc = "## Safety"] @@ -22942,7 +22067,6 @@ pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t { } _vqabs_s8(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"] #[doc = "## Safety"] @@ -22974,7 +22098,6 @@ pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t { } _vqabsq_s8(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"] #[doc = "## Safety"] @@ -23006,7 +22129,6 @@ pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t { } _vqabs_s16(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"] #[doc = "## Safety"] @@ -23038,7 +22160,6 @@ pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t { } _vqabsq_s16(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"] #[doc = "## Safety"] @@ -23070,7 +22191,6 @@ pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t { } _vqabs_s32(a) } - #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"] #[doc = "## Safety"] @@ -23102,7 +22222,6 @@ pub unsafe fn vqabsq_s32(a: int32x4_t) -> int32x4_t { } _vqabsq_s32(a) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"] #[doc = "## Safety"] @@ -23134,7 +22253,6 @@ pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vqadd_s8(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"] #[doc = "## Safety"] @@ -23166,7 +22284,6 @@ pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vqaddq_s8(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"] #[doc = "## Safety"] @@ -23198,7 +22315,6 @@ pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vqadd_s16(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"] #[doc = "## Safety"] @@ -23230,7 +22346,6 @@ pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vqaddq_s16(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"] #[doc = "## Safety"] @@ -23262,7 +22377,6 @@ pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vqadd_s32(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"] #[doc = "## Safety"] @@ -23294,7 +22408,6 @@ pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vqaddq_s32(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"] #[doc = "## Safety"] @@ -23326,7 +22439,6 @@ pub unsafe fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } _vqadd_s64(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"] #[doc = "## Safety"] @@ -23358,7 +22470,6 @@ pub unsafe fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } _vqaddq_s64(a, b) } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"] #[doc = "## Safety"] @@ -23390,7 +22501,6 @@ pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vqadd_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"] #[doc = "## Safety"] @@ -23422,7 +22532,6 @@ pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vqaddq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"] #[doc = "## Safety"] @@ -23454,7 +22563,6 @@ pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vqadd_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"] #[doc = "## Safety"] @@ -23486,7 +22594,6 @@ pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vqaddq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"] #[doc = "## Safety"] @@ -23518,7 +22625,6 @@ pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vqadd_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"] #[doc = "## Safety"] @@ -23550,7 +22656,6 @@ pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vqaddq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"] #[doc = "## Safety"] @@ -23582,7 +22687,6 @@ pub unsafe fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } _vqadd_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"] #[doc = "## Safety"] @@ -23614,7 +22718,6 @@ pub unsafe fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } _vqaddq_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"] #[doc = "## Safety"] @@ -23644,7 +22747,6 @@ pub unsafe fn vqdmlal_lane_s16( static_assert_uimm_bits!(N, 2); vqaddq_s32(a, vqdmull_lane_s16::(b, c)) } - #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"] #[doc = "## Safety"] @@ -23674,7 +22776,6 @@ pub unsafe fn vqdmlal_lane_s32( static_assert_uimm_bits!(N, 1); vqaddq_s64(a, vqdmull_lane_s32::(b, c)) } - #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"] #[doc = "## Safety"] @@ -23698,7 +22799,6 @@ pub unsafe fn vqdmlal_lane_s32( pub unsafe fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vqaddq_s32(a, vqdmull_n_s16(b, c)) } - #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"] #[doc = "## Safety"] @@ -23722,7 +22822,6 @@ pub unsafe fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { pub unsafe fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vqaddq_s64(a, vqdmull_n_s32(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"] #[doc = "## Safety"] @@ -23746,7 +22845,6 @@ pub unsafe fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { pub unsafe fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { vqaddq_s32(a, vqdmull_s16(b, c)) } - #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"] #[doc = "## Safety"] @@ -23770,7 +22868,6 @@ pub unsafe fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t pub unsafe fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { vqaddq_s64(a, vqdmull_s32(b, c)) } - #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"] #[doc = "## Safety"] @@ -23800,7 +22897,6 @@ pub unsafe fn vqdmlsl_lane_s16( static_assert_uimm_bits!(N, 2); vqsubq_s32(a, vqdmull_lane_s16::(b, c)) } - #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"] #[doc = "## Safety"] @@ -23830,7 +22926,6 @@ pub unsafe fn vqdmlsl_lane_s32( static_assert_uimm_bits!(N, 1); vqsubq_s64(a, vqdmull_lane_s32::(b, c)) } - #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"] #[doc = "## Safety"] @@ -23854,7 +22949,6 @@ pub unsafe fn vqdmlsl_lane_s32( pub unsafe fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vqsubq_s32(a, vqdmull_n_s16(b, c)) } - #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"] #[doc = "## Safety"] @@ -23878,7 +22972,6 @@ pub unsafe fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { pub unsafe fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vqsubq_s64(a, vqdmull_n_s32(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"] #[doc = "## Safety"] @@ -23902,7 +22995,6 @@ pub unsafe fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { pub unsafe fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { vqsubq_s32(a, vqdmull_s16(b, c)) } - #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"] #[doc = "## Safety"] @@ -23926,7 +23018,6 @@ pub unsafe fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t pub unsafe fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { vqsubq_s64(a, vqdmull_s32(b, c)) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"] #[doc = "## Safety"] @@ -23952,7 +23043,6 @@ pub unsafe fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> static_assert_uimm_bits!(LANE, 3); vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"] #[doc = "## Safety"] @@ -23978,7 +23068,6 @@ pub unsafe fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> static_assert_uimm_bits!(LANE, 3); vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"] #[doc = "## Safety"] @@ -24004,7 +23093,6 @@ pub unsafe fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> static_assert_uimm_bits!(LANE, 2); vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"] #[doc = "## Safety"] @@ -24030,7 +23118,6 @@ pub unsafe fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> static_assert_uimm_bits!(LANE, 2); vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } - #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"] #[doc = "## Safety"] @@ -24055,7 +23142,6 @@ pub unsafe fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { let b: int16x4_t = vdup_n_s16(b); vqdmulh_s16(a, b) } - #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"] #[doc = "## Safety"] @@ -24080,7 +23166,6 @@ pub unsafe fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { let b: int16x8_t = vdupq_n_s16(b); vqdmulhq_s16(a, b) } - #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"] #[doc = "## Safety"] @@ -24105,7 +23190,6 @@ pub unsafe fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { let b: int32x2_t = vdup_n_s32(b); vqdmulh_s32(a, b) } - #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"] #[doc = "## Safety"] @@ -24130,7 +23214,6 @@ pub unsafe fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { let b: int32x4_t = vdupq_n_s32(b); vqdmulhq_s32(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"] #[doc = "## Safety"] @@ -24162,7 +23245,6 @@ pub unsafe fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vqdmulh_s16(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"] #[doc = "## Safety"] @@ -24194,7 +23276,6 @@ pub unsafe fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vqdmulhq_s16(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"] #[doc = "## Safety"] @@ -24226,7 +23307,6 @@ pub unsafe fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vqdmulh_s32(a, b) } - #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"] #[doc = "## Safety"] @@ -24258,7 +23338,6 @@ pub unsafe fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vqdmulhq_s32(a, b) } - #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"] #[doc = "## Safety"] @@ -24285,7 +23364,6 @@ pub unsafe fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int3 let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); vqdmull_s16(a, b) } - #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"] #[doc = "## Safety"] @@ -24312,7 +23390,6 @@ pub unsafe fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int6 let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); vqdmull_s32(a, b) } - #[doc = "Vector saturating doubling long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"] #[doc = "## Safety"] @@ -24336,7 +23413,6 @@ pub unsafe fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int6 pub unsafe fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { vqdmull_s16(a, vdup_n_s16(b)) } - #[doc = "Vector saturating doubling long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"] #[doc = "## Safety"] @@ -24360,7 +23436,6 @@ pub unsafe fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { pub unsafe fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { vqdmull_s32(a, vdup_n_s32(b)) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"] #[doc = "## Safety"] @@ -24392,7 +23467,6 @@ pub unsafe fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } _vqdmull_s16(a, b) } - #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"] #[doc = "## Safety"] @@ -24424,7 +23498,6 @@ pub unsafe fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } _vqdmull_s32(a, b) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"] #[doc = "## Safety"] @@ -24456,7 +23529,6 @@ pub unsafe fn vqmovn_s16(a: int16x8_t) -> int8x8_t { } _vqmovn_s16(a) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"] #[doc = "## Safety"] @@ -24488,7 +23560,6 @@ pub unsafe fn vqmovn_s32(a: int32x4_t) -> int16x4_t { } _vqmovn_s32(a) } - #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"] #[doc = "## Safety"] @@ -24520,7 +23591,6 @@ pub unsafe fn vqmovn_s64(a: int64x2_t) -> int32x2_t { } _vqmovn_s64(a) } - #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"] #[doc = "## Safety"] @@ -24552,7 +23622,6 @@ pub unsafe fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { } _vqmovn_u16(a.as_signed()).as_unsigned() } - #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"] #[doc = "## Safety"] @@ -24584,7 +23653,6 @@ pub unsafe fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { } _vqmovn_u32(a.as_signed()).as_unsigned() } - #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"] #[doc = "## Safety"] @@ -24616,7 +23684,6 @@ pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { } _vqmovn_u64(a.as_signed()).as_unsigned() } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"] #[doc = "## Safety"] @@ -24648,7 +23715,6 @@ pub unsafe fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { } _vqmovun_s16(a).as_unsigned() } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"] #[doc = "## Safety"] @@ -24680,7 +23746,6 @@ pub unsafe fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { } _vqmovun_s32(a).as_unsigned() } - #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"] #[doc = "## Safety"] @@ -24712,7 +23777,6 @@ pub unsafe fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { } _vqmovun_s64(a).as_unsigned() } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"] #[doc = "## Safety"] @@ -24744,7 +23808,6 @@ pub unsafe fn vqneg_s8(a: int8x8_t) -> int8x8_t { } _vqneg_s8(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"] #[doc = "## Safety"] @@ -24776,7 +23839,6 @@ pub unsafe fn vqnegq_s8(a: int8x16_t) -> int8x16_t { } _vqnegq_s8(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"] #[doc = "## Safety"] @@ -24808,7 +23870,6 @@ pub unsafe fn vqneg_s16(a: int16x4_t) -> int16x4_t { } _vqneg_s16(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"] #[doc = "## Safety"] @@ -24840,7 +23901,6 @@ pub unsafe fn vqnegq_s16(a: int16x8_t) -> int16x8_t { } _vqnegq_s16(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"] #[doc = "## Safety"] @@ -24872,7 +23932,6 @@ pub unsafe fn vqneg_s32(a: int32x2_t) -> int32x2_t { } _vqneg_s32(a) } - #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"] #[doc = "## Safety"] @@ -24904,7 +23963,6 @@ pub unsafe fn vqnegq_s32(a: int32x4_t) -> int32x4_t { } _vqnegq_s32(a) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"] #[doc = "## Safety"] @@ -24931,7 +23989,6 @@ pub unsafe fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmulh_s16(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"] #[doc = "## Safety"] @@ -24958,7 +24015,6 @@ pub unsafe fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); vqrdmulh_s32(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"] #[doc = "## Safety"] @@ -24985,7 +24041,6 @@ pub unsafe fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmulh_s16(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"] #[doc = "## Safety"] @@ -25012,7 +24067,6 @@ pub unsafe fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); vqrdmulh_s32(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"] #[doc = "## Safety"] @@ -25052,7 +24106,6 @@ pub unsafe fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> ); vqrdmulhq_s16(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"] #[doc = "## Safety"] @@ -25079,7 +24132,6 @@ pub unsafe fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmulhq_s32(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"] #[doc = "## Safety"] @@ -25119,7 +24171,6 @@ pub unsafe fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) - ); vqrdmulhq_s16(a, b) } - #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"] #[doc = "## Safety"] @@ -25146,7 +24197,6 @@ pub unsafe fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) - let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vqrdmulhq_s32(a, b) } - #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"] #[doc = "## Safety"] @@ -25170,7 +24220,6 @@ pub unsafe fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) - pub unsafe fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { vqrdmulh_s16(a, vdup_n_s16(b)) } - #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"] #[doc = "## Safety"] @@ -25194,7 +24243,6 @@ pub unsafe fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { pub unsafe fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { vqrdmulhq_s16(a, vdupq_n_s16(b)) } - #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"] #[doc = "## Safety"] @@ -25218,7 +24266,6 @@ pub unsafe fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { pub unsafe fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { vqrdmulh_s32(a, vdup_n_s32(b)) } - #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"] #[doc = "## Safety"] @@ -25242,7 +24289,6 @@ pub unsafe fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { pub unsafe fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { vqrdmulhq_s32(a, vdupq_n_s32(b)) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"] #[doc = "## Safety"] @@ -25274,7 +24320,6 @@ pub unsafe fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vqrdmulh_s16(a, b) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"] #[doc = "## Safety"] @@ -25306,7 +24351,6 @@ pub unsafe fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vqrdmulhq_s16(a, b) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"] #[doc = "## Safety"] @@ -25338,7 +24382,6 @@ pub unsafe fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vqrdmulh_s32(a, b) } - #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"] #[doc = "## Safety"] @@ -25370,7 +24413,6 @@ pub unsafe fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vqrdmulhq_s32(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"] #[doc = "## Safety"] @@ -25402,7 +24444,6 @@ pub unsafe fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vqrshl_s8(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"] #[doc = "## Safety"] @@ -25434,7 +24475,6 @@ pub unsafe fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vqrshlq_s8(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"] #[doc = "## Safety"] @@ -25466,7 +24506,6 @@ pub unsafe fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vqrshl_s16(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"] #[doc = "## Safety"] @@ -25498,7 +24537,6 @@ pub unsafe fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vqrshlq_s16(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"] #[doc = "## Safety"] @@ -25530,7 +24568,6 @@ pub unsafe fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vqrshl_s32(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"] #[doc = "## Safety"] @@ -25562,7 +24599,6 @@ pub unsafe fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vqrshlq_s32(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"] #[doc = "## Safety"] @@ -25594,7 +24630,6 @@ pub unsafe fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } _vqrshl_s64(a, b) } - #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"] #[doc = "## Safety"] @@ -25626,7 +24661,6 @@ pub unsafe fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } _vqrshlq_s64(a, b) } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"] #[doc = "## Safety"] @@ -25658,7 +24692,6 @@ pub unsafe fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } _vqrshl_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"] #[doc = "## Safety"] @@ -25690,7 +24723,6 @@ pub unsafe fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } _vqrshlq_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"] #[doc = "## Safety"] @@ -25722,7 +24754,6 @@ pub unsafe fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } _vqrshl_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"] #[doc = "## Safety"] @@ -25754,7 +24785,6 @@ pub unsafe fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } _vqrshlq_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"] #[doc = "## Safety"] @@ -25786,7 +24816,6 @@ pub unsafe fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } _vqrshl_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"] #[doc = "## Safety"] @@ -25818,7 +24847,6 @@ pub unsafe fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } _vqrshlq_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"] #[doc = "## Safety"] @@ -25850,7 +24878,6 @@ pub unsafe fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } _vqrshl_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"] #[doc = "## Safety"] @@ -25882,7 +24909,6 @@ pub unsafe fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } _vqrshlq_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] #[doc = "## Safety"] @@ -25909,7 +24935,6 @@ pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { }, ) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] #[doc = "## Safety"] @@ -25931,7 +24956,6 @@ pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, ) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] #[doc = "## Safety"] @@ -25950,7 +24974,6 @@ pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { } _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] #[doc = "## Safety"] @@ -25972,7 +24995,6 @@ pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { } _vqrshrn_n_s16(a, N) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] #[doc = "## Safety"] @@ -25994,7 +25016,6 @@ pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { } _vqrshrn_n_s32(a, N) } - #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] #[doc = "## Safety"] @@ -26016,7 +25037,6 @@ pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { } _vqrshrn_n_s64(a, N) } - #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] #[doc = "## Safety"] @@ -26045,7 +25065,6 @@ pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { ) .as_unsigned() } - #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] #[doc = "## Safety"] @@ -26068,7 +25087,6 @@ pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { ) .as_unsigned() } - #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] #[doc = "## Safety"] @@ -26091,7 +25109,6 @@ pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { ) .as_unsigned() } - #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] #[doc = "## Safety"] @@ -26113,7 +25130,6 @@ pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { } _vqrshrn_n_u16(a.as_signed(), N).as_unsigned() } - #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] #[doc = "## Safety"] @@ -26135,7 +25151,6 @@ pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } _vqrshrn_n_u32(a.as_signed(), N).as_unsigned() } - #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] #[doc = "## Safety"] @@ -26157,7 +25172,6 @@ pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { } _vqrshrn_n_u64(a.as_signed(), N).as_unsigned() } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] #[doc = "## Safety"] @@ -26185,7 +25199,6 @@ pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { ) .as_unsigned() } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] #[doc = "## Safety"] @@ -26208,7 +25221,6 @@ pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { ) .as_unsigned() } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] #[doc = "## Safety"] @@ -26227,7 +25239,6 @@ pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { } _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }).as_unsigned() } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] #[doc = "## Safety"] @@ -26249,7 +25260,6 @@ pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { } _vqrshrun_n_s16(a, N).as_unsigned() } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] #[doc = "## Safety"] @@ -26271,7 +25281,6 @@ pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { } _vqrshrun_n_s32(a, N).as_unsigned() } - #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] #[doc = "## Safety"] @@ -26293,7 +25302,6 @@ pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { } _vqrshrun_n_s64(a, N).as_unsigned() } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"] #[doc = "## Safety"] @@ -26319,7 +25327,6 @@ pub unsafe fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); vqshl_s8(a, vdup_n_s8(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"] #[doc = "## Safety"] @@ -26345,7 +25352,6 @@ pub unsafe fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); vqshlq_s8(a, vdupq_n_s8(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"] #[doc = "## Safety"] @@ -26371,7 +25377,6 @@ pub unsafe fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 4); vqshl_s16(a, vdup_n_s16(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"] #[doc = "## Safety"] @@ -26397,7 +25402,6 @@ pub unsafe fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 4); vqshlq_s16(a, vdupq_n_s16(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"] #[doc = "## Safety"] @@ -26423,7 +25427,6 @@ pub unsafe fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 5); vqshl_s32(a, vdup_n_s32(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"] #[doc = "## Safety"] @@ -26449,7 +25452,6 @@ pub unsafe fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 5); vqshlq_s32(a, vdupq_n_s32(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"] #[doc = "## Safety"] @@ -26475,7 +25477,6 @@ pub unsafe fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { static_assert_uimm_bits!(N, 6); vqshl_s64(a, vdup_n_s64(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"] #[doc = "## Safety"] @@ -26501,7 +25502,6 @@ pub unsafe fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 6); vqshlq_s64(a, vdupq_n_s64(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"] #[doc = "## Safety"] @@ -26527,7 +25527,6 @@ pub unsafe fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); vqshl_u8(a, vdup_n_s8(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"] #[doc = "## Safety"] @@ -26553,7 +25552,6 @@ pub unsafe fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); vqshlq_u8(a, vdupq_n_s8(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"] #[doc = "## Safety"] @@ -26579,7 +25577,6 @@ pub unsafe fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); vqshl_u16(a, vdup_n_s16(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"] #[doc = "## Safety"] @@ -26605,7 +25602,6 @@ pub unsafe fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); vqshlq_u16(a, vdupq_n_s16(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"] #[doc = "## Safety"] @@ -26631,7 +25627,6 @@ pub unsafe fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 5); vqshl_u32(a, vdup_n_s32(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"] #[doc = "## Safety"] @@ -26657,7 +25652,6 @@ pub unsafe fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 5); vqshlq_u32(a, vdupq_n_s32(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"] #[doc = "## Safety"] @@ -26683,7 +25677,6 @@ pub unsafe fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert_uimm_bits!(N, 6); vqshl_u64(a, vdup_n_s64(N as _)) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"] #[doc = "## Safety"] @@ -26709,7 +25702,6 @@ pub unsafe fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 6); vqshlq_u64(a, vdupq_n_s64(N as _)) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"] #[doc = "## Safety"] @@ -26741,7 +25733,6 @@ pub unsafe fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vqshl_s8(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"] #[doc = "## Safety"] @@ -26773,7 +25764,6 @@ pub unsafe fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vqshlq_s8(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"] #[doc = "## Safety"] @@ -26805,7 +25795,6 @@ pub unsafe fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vqshl_s16(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"] #[doc = "## Safety"] @@ -26837,7 +25826,6 @@ pub unsafe fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vqshlq_s16(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"] #[doc = "## Safety"] @@ -26869,7 +25857,6 @@ pub unsafe fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vqshl_s32(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"] #[doc = "## Safety"] @@ -26901,7 +25888,6 @@ pub unsafe fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vqshlq_s32(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"] #[doc = "## Safety"] @@ -26933,7 +25919,6 @@ pub unsafe fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } _vqshl_s64(a, b) } - #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"] #[doc = "## Safety"] @@ -26965,7 +25950,6 @@ pub unsafe fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } _vqshlq_s64(a, b) } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"] #[doc = "## Safety"] @@ -26997,7 +25981,6 @@ pub unsafe fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } _vqshl_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"] #[doc = "## Safety"] @@ -27029,7 +26012,6 @@ pub unsafe fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } _vqshlq_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"] #[doc = "## Safety"] @@ -27061,7 +26043,6 @@ pub unsafe fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } _vqshl_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"] #[doc = "## Safety"] @@ -27093,7 +26074,6 @@ pub unsafe fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } _vqshlq_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"] #[doc = "## Safety"] @@ -27125,7 +26105,6 @@ pub unsafe fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } _vqshl_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"] #[doc = "## Safety"] @@ -27157,7 +26136,6 @@ pub unsafe fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } _vqshlq_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"] #[doc = "## Safety"] @@ -27189,7 +26167,6 @@ pub unsafe fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } _vqshl_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"] #[doc = "## Safety"] @@ -27221,7 +26198,6 @@ pub unsafe fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } _vqshlq_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] #[doc = "## Safety"] @@ -27248,7 +26224,6 @@ pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] #[doc = "## Safety"] @@ -27276,7 +26251,6 @@ pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] #[doc = "## Safety"] @@ -27299,7 +26273,6 @@ pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] #[doc = "## Safety"] @@ -27326,7 +26299,6 @@ pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] #[doc = "## Safety"] @@ -27345,7 +26317,6 @@ pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { } _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] #[doc = "## Safety"] @@ -27368,7 +26339,6 @@ pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] #[doc = "## Safety"] @@ -27387,7 +26357,6 @@ pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { } _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] #[doc = "## Safety"] @@ -27406,7 +26375,6 @@ pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { } _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] #[doc = "## Safety"] @@ -27436,7 +26404,6 @@ pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] #[doc = "## Safety"] @@ -27467,7 +26434,6 @@ pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] #[doc = "## Safety"] @@ -27493,7 +26459,6 @@ pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] #[doc = "## Safety"] @@ -27523,7 +26488,6 @@ pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] #[doc = "## Safety"] @@ -27545,7 +26509,6 @@ pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { } _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] #[doc = "## Safety"] @@ -27571,7 +26534,6 @@ pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { ) .as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] #[doc = "## Safety"] @@ -27593,7 +26555,6 @@ pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { } _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }).as_unsigned() } - #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] #[doc = "## Safety"] @@ -27615,7 +26576,6 @@ pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { } _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }).as_unsigned() } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] #[doc = "## Safety"] @@ -27642,7 +26602,6 @@ pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { }, ) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] #[doc = "## Safety"] @@ -27664,7 +26623,6 @@ pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, ) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] #[doc = "## Safety"] @@ -27683,7 +26641,6 @@ pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { } _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] #[doc = "## Safety"] @@ -27705,7 +26662,6 @@ pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { } _vqshrn_n_s16(a, N) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] #[doc = "## Safety"] @@ -27727,7 +26683,6 @@ pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { } _vqshrn_n_s32(a, N) } - #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] #[doc = "## Safety"] @@ -27749,7 +26704,6 @@ pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { } _vqshrn_n_s64(a, N) } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] #[doc = "## Safety"] @@ -27778,7 +26732,6 @@ pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { ) .as_unsigned() } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] #[doc = "## Safety"] @@ -27801,7 +26754,6 @@ pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { ) .as_unsigned() } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] #[doc = "## Safety"] @@ -27824,7 +26776,6 @@ pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { ) .as_unsigned() } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] #[doc = "## Safety"] @@ -27846,7 +26797,6 @@ pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { } _vqshrn_n_u16(a.as_signed(), N).as_unsigned() } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] #[doc = "## Safety"] @@ -27868,7 +26818,6 @@ pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } _vqshrn_n_u32(a.as_signed(), N).as_unsigned() } - #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] #[doc = "## Safety"] @@ -27890,7 +26839,6 @@ pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { } _vqshrn_n_u64(a.as_signed(), N).as_unsigned() } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] #[doc = "## Safety"] @@ -27918,7 +26866,6 @@ pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { ) .as_unsigned() } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] #[doc = "## Safety"] @@ -27941,7 +26888,6 @@ pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { ) .as_unsigned() } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] #[doc = "## Safety"] @@ -27960,7 +26906,6 @@ pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { } _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }).as_unsigned() } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] #[doc = "## Safety"] @@ -27982,7 +26927,6 @@ pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { } _vqshrun_n_s16(a, N).as_unsigned() } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] #[doc = "## Safety"] @@ -28004,7 +26948,6 @@ pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { } _vqshrun_n_s32(a, N).as_unsigned() } - #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] #[doc = "## Safety"] @@ -28026,7 +26969,6 @@ pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { } _vqshrun_n_s64(a, N).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"] #[doc = "## Safety"] @@ -28058,7 +27000,6 @@ pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vqsub_s8(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"] #[doc = "## Safety"] @@ -28090,7 +27031,6 @@ pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vqsubq_s8(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"] #[doc = "## Safety"] @@ -28122,7 +27062,6 @@ pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vqsub_s16(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"] #[doc = "## Safety"] @@ -28154,7 +27093,6 @@ pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vqsubq_s16(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"] #[doc = "## Safety"] @@ -28186,7 +27124,6 @@ pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vqsub_s32(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"] #[doc = "## Safety"] @@ -28218,7 +27155,6 @@ pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vqsubq_s32(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"] #[doc = "## Safety"] @@ -28250,7 +27186,6 @@ pub unsafe fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } _vqsub_s64(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"] #[doc = "## Safety"] @@ -28282,7 +27217,6 @@ pub unsafe fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } _vqsubq_s64(a, b) } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"] #[doc = "## Safety"] @@ -28314,7 +27248,6 @@ pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vqsub_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"] #[doc = "## Safety"] @@ -28346,7 +27279,6 @@ pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vqsubq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"] #[doc = "## Safety"] @@ -28378,7 +27310,6 @@ pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vqsub_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"] #[doc = "## Safety"] @@ -28410,7 +27341,6 @@ pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vqsubq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"] #[doc = "## Safety"] @@ -28442,7 +27372,6 @@ pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vqsub_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"] #[doc = "## Safety"] @@ -28474,7 +27403,6 @@ pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vqsubq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"] #[doc = "## Safety"] @@ -28506,7 +27434,6 @@ pub unsafe fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } _vqsub_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"] #[doc = "## Safety"] @@ -28538,7 +27465,6 @@ pub unsafe fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } _vqsubq_u64(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"] #[doc = "## Safety"] @@ -28570,7 +27496,6 @@ pub unsafe fn vrecpe_f32(a: float32x2_t) -> float32x2_t { } _vrecpe_f32(a) } - #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"] #[doc = "## Safety"] @@ -28602,7 +27527,6 @@ pub unsafe fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { } _vrecpeq_f32(a) } - #[doc = "Unsigned reciprocal estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"] #[doc = "## Safety"] @@ -28634,7 +27558,6 @@ pub unsafe fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { } _vrecpe_u32(a.as_signed()).as_unsigned() } - #[doc = "Unsigned reciprocal estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"] #[doc = "## Safety"] @@ -28666,7 +27589,6 @@ pub unsafe fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { } _vrecpeq_u32(a.as_signed()).as_unsigned() } - #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"] #[doc = "## Safety"] @@ -28698,7 +27620,6 @@ pub unsafe fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vrecps_f32(a, b) } - #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"] #[doc = "## Safety"] @@ -28730,7 +27651,6 @@ pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vrecpsq_f32(a, b) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] #[doc = "## Safety"] @@ -28754,7 +27674,6 @@ pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] #[doc = "## Safety"] @@ -28778,7 +27697,6 @@ pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] #[doc = "## Safety"] @@ -28802,7 +27720,6 @@ pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] #[doc = "## Safety"] @@ -28826,7 +27743,6 @@ pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] #[doc = "## Safety"] @@ -28850,7 +27766,6 @@ pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] #[doc = "## Safety"] @@ -28874,7 +27789,6 @@ pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] #[doc = "## Safety"] @@ -28898,7 +27812,6 @@ pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] #[doc = "## Safety"] @@ -28922,7 +27835,6 @@ pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] #[doc = "## Safety"] @@ -28946,7 +27858,6 @@ pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] #[doc = "## Safety"] @@ -28970,7 +27881,6 @@ pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] #[doc = "## Safety"] @@ -28994,7 +27904,6 @@ pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] #[doc = "## Safety"] @@ -29018,7 +27927,6 @@ pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] #[doc = "## Safety"] @@ -29042,7 +27950,6 @@ pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] #[doc = "## Safety"] @@ -29066,7 +27973,6 @@ pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] #[doc = "## Safety"] @@ -29090,7 +27996,6 @@ pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] #[doc = "## Safety"] @@ -29114,7 +28019,6 @@ pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] #[doc = "## Safety"] @@ -29138,7 +28042,6 @@ pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] #[doc = "## Safety"] @@ -29162,7 +28065,6 @@ pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] #[doc = "## Safety"] @@ -29186,7 +28088,6 @@ pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] #[doc = "## Safety"] @@ -29210,7 +28111,6 @@ pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] #[doc = "## Safety"] @@ -29234,7 +28134,6 @@ pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] #[doc = "## Safety"] @@ -29258,7 +28157,6 @@ pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] #[doc = "## Safety"] @@ -29282,7 +28180,6 @@ pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] #[doc = "## Safety"] @@ -29306,7 +28203,6 @@ pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] #[doc = "## Safety"] @@ -29330,7 +28226,6 @@ pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] #[doc = "## Safety"] @@ -29354,7 +28249,6 @@ pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] #[doc = "## Safety"] @@ -29378,7 +28272,6 @@ pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] #[doc = "## Safety"] @@ -29402,7 +28295,6 @@ pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] #[doc = "## Safety"] @@ -29426,7 +28318,6 @@ pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] #[doc = "## Safety"] @@ -29450,7 +28341,6 @@ pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] #[doc = "## Safety"] @@ -29474,7 +28364,6 @@ pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] #[doc = "## Safety"] @@ -29498,7 +28387,6 @@ pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] #[doc = "## Safety"] @@ -29522,7 +28410,6 @@ pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] #[doc = "## Safety"] @@ -29546,7 +28433,6 @@ pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] #[doc = "## Safety"] @@ -29570,7 +28456,6 @@ pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] #[doc = "## Safety"] @@ -29594,7 +28479,6 @@ pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] #[doc = "## Safety"] @@ -29618,7 +28502,6 @@ pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] #[doc = "## Safety"] @@ -29642,7 +28525,6 @@ pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] #[doc = "## Safety"] @@ -29666,7 +28548,6 @@ pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] #[doc = "## Safety"] @@ -29690,7 +28571,6 @@ pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] #[doc = "## Safety"] @@ -29714,7 +28594,6 @@ pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] #[doc = "## Safety"] @@ -29738,7 +28617,6 @@ pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] #[doc = "## Safety"] @@ -29762,7 +28640,6 @@ pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] #[doc = "## Safety"] @@ -29786,7 +28663,6 @@ pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] #[doc = "## Safety"] @@ -29810,7 +28686,6 @@ pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] #[doc = "## Safety"] @@ -29834,7 +28709,6 @@ pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] #[doc = "## Safety"] @@ -29858,7 +28732,6 @@ pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] #[doc = "## Safety"] @@ -29882,7 +28755,6 @@ pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] #[doc = "## Safety"] @@ -29906,7 +28778,6 @@ pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] #[doc = "## Safety"] @@ -29930,7 +28801,6 @@ pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] #[doc = "## Safety"] @@ -29954,7 +28824,6 @@ pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] #[doc = "## Safety"] @@ -29978,7 +28847,6 @@ pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] #[doc = "## Safety"] @@ -30002,7 +28870,6 @@ pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] #[doc = "## Safety"] @@ -30026,7 +28893,6 @@ pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] #[doc = "## Safety"] @@ -30050,7 +28916,6 @@ pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] #[doc = "## Safety"] @@ -30074,7 +28939,6 @@ pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] #[doc = "## Safety"] @@ -30098,7 +28962,6 @@ pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] #[doc = "## Safety"] @@ -30122,7 +28985,6 @@ pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] #[doc = "## Safety"] @@ -30146,7 +29008,6 @@ pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] #[doc = "## Safety"] @@ -30170,7 +29031,6 @@ pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] #[doc = "## Safety"] @@ -30194,7 +29054,6 @@ pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] #[doc = "## Safety"] @@ -30218,7 +29077,6 @@ pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] #[doc = "## Safety"] @@ -30242,7 +29100,6 @@ pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] #[doc = "## Safety"] @@ -30266,7 +29123,6 @@ pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] #[doc = "## Safety"] @@ -30290,7 +29146,6 @@ pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] #[doc = "## Safety"] @@ -30314,7 +29169,6 @@ pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] #[doc = "## Safety"] @@ -30338,7 +29192,6 @@ pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] #[doc = "## Safety"] @@ -30362,7 +29215,6 @@ pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] #[doc = "## Safety"] @@ -30386,7 +29238,6 @@ pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] #[doc = "## Safety"] @@ -30410,7 +29261,6 @@ pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] #[doc = "## Safety"] @@ -30434,7 +29284,6 @@ pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] #[doc = "## Safety"] @@ -30458,7 +29307,6 @@ pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] #[doc = "## Safety"] @@ -30482,7 +29330,6 @@ pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] #[doc = "## Safety"] @@ -30506,7 +29353,6 @@ pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] #[doc = "## Safety"] @@ -30530,7 +29376,6 @@ pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] #[doc = "## Safety"] @@ -30554,7 +29399,6 @@ pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] #[doc = "## Safety"] @@ -30578,7 +29422,6 @@ pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] #[doc = "## Safety"] @@ -30602,7 +29445,6 @@ pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] #[doc = "## Safety"] @@ -30626,7 +29468,6 @@ pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] #[doc = "## Safety"] @@ -30650,7 +29491,6 @@ pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] #[doc = "## Safety"] @@ -30674,7 +29514,6 @@ pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] #[doc = "## Safety"] @@ -30698,7 +29537,6 @@ pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] #[doc = "## Safety"] @@ -30722,7 +29560,6 @@ pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] #[doc = "## Safety"] @@ -30746,7 +29583,6 @@ pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] #[doc = "## Safety"] @@ -30770,7 +29606,6 @@ pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] #[doc = "## Safety"] @@ -30794,7 +29629,6 @@ pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] #[doc = "## Safety"] @@ -30818,7 +29652,6 @@ pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] #[doc = "## Safety"] @@ -30842,7 +29675,6 @@ pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] #[doc = "## Safety"] @@ -30866,7 +29698,6 @@ pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] #[doc = "## Safety"] @@ -30890,7 +29721,6 @@ pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] #[doc = "## Safety"] @@ -30914,7 +29744,6 @@ pub unsafe fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] #[doc = "## Safety"] @@ -30938,7 +29767,6 @@ pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] #[doc = "## Safety"] @@ -30962,7 +29790,6 @@ pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] #[doc = "## Safety"] @@ -30986,7 +29813,6 @@ pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] #[doc = "## Safety"] @@ -31010,7 +29836,6 @@ pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] #[doc = "## Safety"] @@ -31034,7 +29859,6 @@ pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] #[doc = "## Safety"] @@ -31058,7 +29882,6 @@ pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] #[doc = "## Safety"] @@ -31082,7 +29905,6 @@ pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] #[doc = "## Safety"] @@ -31106,7 +29928,6 @@ pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] #[doc = "## Safety"] @@ -31130,7 +29951,6 @@ pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] #[doc = "## Safety"] @@ -31154,7 +29974,6 @@ pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] #[doc = "## Safety"] @@ -31178,7 +29997,6 @@ pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] #[doc = "## Safety"] @@ -31202,7 +30020,6 @@ pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] #[doc = "## Safety"] @@ -31226,7 +30043,6 @@ pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] #[doc = "## Safety"] @@ -31250,7 +30066,6 @@ pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] #[doc = "## Safety"] @@ -31274,7 +30089,6 @@ pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] #[doc = "## Safety"] @@ -31298,7 +30112,6 @@ pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] #[doc = "## Safety"] @@ -31322,7 +30135,6 @@ pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] #[doc = "## Safety"] @@ -31346,7 +30158,6 @@ pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] #[doc = "## Safety"] @@ -31370,7 +30181,6 @@ pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] #[doc = "## Safety"] @@ -31394,7 +30204,6 @@ pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] #[doc = "## Safety"] @@ -31418,7 +30227,6 @@ pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] #[doc = "## Safety"] @@ -31442,7 +30250,6 @@ pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] #[doc = "## Safety"] @@ -31466,7 +30273,6 @@ pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] #[doc = "## Safety"] @@ -31490,7 +30296,6 @@ pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] #[doc = "## Safety"] @@ -31514,7 +30319,6 @@ pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] #[doc = "## Safety"] @@ -31538,7 +30342,6 @@ pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] #[doc = "## Safety"] @@ -31562,7 +30365,6 @@ pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] #[doc = "## Safety"] @@ -31586,7 +30388,6 @@ pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] #[doc = "## Safety"] @@ -31610,7 +30411,6 @@ pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] #[doc = "## Safety"] @@ -31634,7 +30434,6 @@ pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] #[doc = "## Safety"] @@ -31658,7 +30457,6 @@ pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] #[doc = "## Safety"] @@ -31682,7 +30480,6 @@ pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] #[doc = "## Safety"] @@ -31706,7 +30503,6 @@ pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] #[doc = "## Safety"] @@ -31730,7 +30526,6 @@ pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] #[doc = "## Safety"] @@ -31754,7 +30549,6 @@ pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] #[doc = "## Safety"] @@ -31778,7 +30572,6 @@ pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] #[doc = "## Safety"] @@ -31802,7 +30595,6 @@ pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] #[doc = "## Safety"] @@ -31826,7 +30618,6 @@ pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] #[doc = "## Safety"] @@ -31850,7 +30641,6 @@ pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] #[doc = "## Safety"] @@ -31874,7 +30664,6 @@ pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] #[doc = "## Safety"] @@ -31898,7 +30687,6 @@ pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] #[doc = "## Safety"] @@ -31922,7 +30710,6 @@ pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] #[doc = "## Safety"] @@ -31946,7 +30733,6 @@ pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] #[doc = "## Safety"] @@ -31970,7 +30756,6 @@ pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] #[doc = "## Safety"] @@ -31994,7 +30779,6 @@ pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] #[doc = "## Safety"] @@ -32018,7 +30802,6 @@ pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] #[doc = "## Safety"] @@ -32042,7 +30825,6 @@ pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] #[doc = "## Safety"] @@ -32066,7 +30848,6 @@ pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] #[doc = "## Safety"] @@ -32090,7 +30871,6 @@ pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] #[doc = "## Safety"] @@ -32114,7 +30894,6 @@ pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] #[doc = "## Safety"] @@ -32138,7 +30917,6 @@ pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] #[doc = "## Safety"] @@ -32162,7 +30940,6 @@ pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] #[doc = "## Safety"] @@ -32186,7 +30963,6 @@ pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] #[doc = "## Safety"] @@ -32210,7 +30986,6 @@ pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] #[doc = "## Safety"] @@ -32234,7 +31009,6 @@ pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] #[doc = "## Safety"] @@ -32258,7 +31032,6 @@ pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] #[doc = "## Safety"] @@ -32282,7 +31055,6 @@ pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] #[doc = "## Safety"] @@ -32306,7 +31078,6 @@ pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] #[doc = "## Safety"] @@ -32330,7 +31101,6 @@ pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] #[doc = "## Safety"] @@ -32354,7 +31124,6 @@ pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] #[doc = "## Safety"] @@ -32378,7 +31147,6 @@ pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] #[doc = "## Safety"] @@ -32402,7 +31170,6 @@ pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] #[doc = "## Safety"] @@ -32426,7 +31193,6 @@ pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] #[doc = "## Safety"] @@ -32450,7 +31216,6 @@ pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] #[doc = "## Safety"] @@ -32474,7 +31239,6 @@ pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] #[doc = "## Safety"] @@ -32498,7 +31262,6 @@ pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] #[doc = "## Safety"] @@ -32522,7 +31285,6 @@ pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] #[doc = "## Safety"] @@ -32546,7 +31308,6 @@ pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] #[doc = "## Safety"] @@ -32570,7 +31331,6 @@ pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] #[doc = "## Safety"] @@ -32594,7 +31354,6 @@ pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] #[doc = "## Safety"] @@ -32618,7 +31377,6 @@ pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] #[doc = "## Safety"] @@ -32642,7 +31400,6 @@ pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] #[doc = "## Safety"] @@ -32666,7 +31423,6 @@ pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] #[doc = "## Safety"] @@ -32690,7 +31446,6 @@ pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] #[doc = "## Safety"] @@ -32714,7 +31469,6 @@ pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] #[doc = "## Safety"] @@ -32738,7 +31492,6 @@ pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] #[doc = "## Safety"] @@ -32762,7 +31515,6 @@ pub unsafe fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] #[doc = "## Safety"] @@ -32786,7 +31538,6 @@ pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] #[doc = "## Safety"] @@ -32810,7 +31561,6 @@ pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] #[doc = "## Safety"] @@ -32834,7 +31584,6 @@ pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] #[doc = "## Safety"] @@ -32858,7 +31607,6 @@ pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] #[doc = "## Safety"] @@ -32882,7 +31630,6 @@ pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] #[doc = "## Safety"] @@ -32906,7 +31653,6 @@ pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] #[doc = "## Safety"] @@ -32930,7 +31676,6 @@ pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] #[doc = "## Safety"] @@ -32954,7 +31699,6 @@ pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] #[doc = "## Safety"] @@ -32978,7 +31722,6 @@ pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] #[doc = "## Safety"] @@ -33002,7 +31745,6 @@ pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] #[doc = "## Safety"] @@ -33026,7 +31768,6 @@ pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] #[doc = "## Safety"] @@ -33050,7 +31791,6 @@ pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] #[doc = "## Safety"] @@ -33074,7 +31814,6 @@ pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] #[doc = "## Safety"] @@ -33098,7 +31837,6 @@ pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] #[doc = "## Safety"] @@ -33122,7 +31860,6 @@ pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] #[doc = "## Safety"] @@ -33146,7 +31883,6 @@ pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] #[doc = "## Safety"] @@ -33170,7 +31906,6 @@ pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] #[doc = "## Safety"] @@ -33194,7 +31929,6 @@ pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] #[doc = "## Safety"] @@ -33218,7 +31952,6 @@ pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] #[doc = "## Safety"] @@ -33242,7 +31975,6 @@ pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] #[doc = "## Safety"] @@ -33266,7 +31998,6 @@ pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] #[doc = "## Safety"] @@ -33290,7 +32021,6 @@ pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] #[doc = "## Safety"] @@ -33314,7 +32044,6 @@ pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] #[doc = "## Safety"] @@ -33338,7 +32067,6 @@ pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] #[doc = "## Safety"] @@ -33362,7 +32090,6 @@ pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] #[doc = "## Safety"] @@ -33386,7 +32113,6 @@ pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] #[doc = "## Safety"] @@ -33410,7 +32136,6 @@ pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] #[doc = "## Safety"] @@ -33434,7 +32159,6 @@ pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] #[doc = "## Safety"] @@ -33458,7 +32182,6 @@ pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] #[doc = "## Safety"] @@ -33482,7 +32205,6 @@ pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] #[doc = "## Safety"] @@ -33506,7 +32228,6 @@ pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] #[doc = "## Safety"] @@ -33530,7 +32251,6 @@ pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] #[doc = "## Safety"] @@ -33554,7 +32274,6 @@ pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] #[doc = "## Safety"] @@ -33578,7 +32297,6 @@ pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] #[doc = "## Safety"] @@ -33602,7 +32320,6 @@ pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] #[doc = "## Safety"] @@ -33626,7 +32343,6 @@ pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] #[doc = "## Safety"] @@ -33650,7 +32366,6 @@ pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] #[doc = "## Safety"] @@ -33674,7 +32389,6 @@ pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] #[doc = "## Safety"] @@ -33698,7 +32412,6 @@ pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] #[doc = "## Safety"] @@ -33722,7 +32435,6 @@ pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] #[doc = "## Safety"] @@ -33746,7 +32458,6 @@ pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] #[doc = "## Safety"] @@ -33770,7 +32481,6 @@ pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] #[doc = "## Safety"] @@ -33794,7 +32504,6 @@ pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] #[doc = "## Safety"] @@ -33818,7 +32527,6 @@ pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] #[doc = "## Safety"] @@ -33842,7 +32550,6 @@ pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] #[doc = "## Safety"] @@ -33866,7 +32573,6 @@ pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] #[doc = "## Safety"] @@ -33890,7 +32596,6 @@ pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] #[doc = "## Safety"] @@ -33914,7 +32619,6 @@ pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] #[doc = "## Safety"] @@ -33938,7 +32642,6 @@ pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] #[doc = "## Safety"] @@ -33962,7 +32665,6 @@ pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] #[doc = "## Safety"] @@ -33986,7 +32688,6 @@ pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] #[doc = "## Safety"] @@ -34010,7 +32711,6 @@ pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] #[doc = "## Safety"] @@ -34034,7 +32734,6 @@ pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] #[doc = "## Safety"] @@ -34058,7 +32757,6 @@ pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] #[doc = "## Safety"] @@ -34082,7 +32780,6 @@ pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] #[doc = "## Safety"] @@ -34106,7 +32803,6 @@ pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] #[doc = "## Safety"] @@ -34130,7 +32826,6 @@ pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] #[doc = "## Safety"] @@ -34154,7 +32849,6 @@ pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] #[doc = "## Safety"] @@ -34178,7 +32872,6 @@ pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] #[doc = "## Safety"] @@ -34202,7 +32895,6 @@ pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] #[doc = "## Safety"] @@ -34226,7 +32918,6 @@ pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] #[doc = "## Safety"] @@ -34250,7 +32941,6 @@ pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] #[doc = "## Safety"] @@ -34274,7 +32964,6 @@ pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] #[doc = "## Safety"] @@ -34298,7 +32987,6 @@ pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] #[doc = "## Safety"] @@ -34322,7 +33010,6 @@ pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] #[doc = "## Safety"] @@ -34346,7 +33033,6 @@ pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] #[doc = "## Safety"] @@ -34370,7 +33056,6 @@ pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] #[doc = "## Safety"] @@ -34394,7 +33079,6 @@ pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] #[doc = "## Safety"] @@ -34418,7 +33102,6 @@ pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] #[doc = "## Safety"] @@ -34442,7 +33125,6 @@ pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] #[doc = "## Safety"] @@ -34466,7 +33148,6 @@ pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] #[doc = "## Safety"] @@ -34490,7 +33171,6 @@ pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] #[doc = "## Safety"] @@ -34514,7 +33194,6 @@ pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] #[doc = "## Safety"] @@ -34538,7 +33217,6 @@ pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] #[doc = "## Safety"] @@ -34562,7 +33240,6 @@ pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] #[doc = "## Safety"] @@ -34586,7 +33263,6 @@ pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] #[doc = "## Safety"] @@ -34610,7 +33286,6 @@ pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] #[doc = "## Safety"] @@ -34634,7 +33309,6 @@ pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] #[doc = "## Safety"] @@ -34658,7 +33332,6 @@ pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] #[doc = "## Safety"] @@ -34682,7 +33355,6 @@ pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] #[doc = "## Safety"] @@ -34706,7 +33378,6 @@ pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] #[doc = "## Safety"] @@ -34730,7 +33401,6 @@ pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] #[doc = "## Safety"] @@ -34754,7 +33424,6 @@ pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] #[doc = "## Safety"] @@ -34778,7 +33447,6 @@ pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] #[doc = "## Safety"] @@ -34802,7 +33470,6 @@ pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] #[doc = "## Safety"] @@ -34826,7 +33493,6 @@ pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] #[doc = "## Safety"] @@ -34850,7 +33516,6 @@ pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] #[doc = "## Safety"] @@ -34874,7 +33539,6 @@ pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] #[doc = "## Safety"] @@ -34898,7 +33562,6 @@ pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] #[doc = "## Safety"] @@ -34922,7 +33585,6 @@ pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] #[doc = "## Safety"] @@ -34946,7 +33608,6 @@ pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] #[doc = "## Safety"] @@ -34970,7 +33631,6 @@ pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] #[doc = "## Safety"] @@ -34994,7 +33654,6 @@ pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] #[doc = "## Safety"] @@ -35018,7 +33677,6 @@ pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] #[doc = "## Safety"] @@ -35042,7 +33700,6 @@ pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] #[doc = "## Safety"] @@ -35066,7 +33723,6 @@ pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] #[doc = "## Safety"] @@ -35090,7 +33746,6 @@ pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] #[doc = "## Safety"] @@ -35114,7 +33769,6 @@ pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] #[doc = "## Safety"] @@ -35138,7 +33792,6 @@ pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] #[doc = "## Safety"] @@ -35162,7 +33815,6 @@ pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] #[doc = "## Safety"] @@ -35186,7 +33838,6 @@ pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] #[doc = "## Safety"] @@ -35210,7 +33861,6 @@ pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] #[doc = "## Safety"] @@ -35234,7 +33884,6 @@ pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] #[doc = "## Safety"] @@ -35258,7 +33907,6 @@ pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] #[doc = "## Safety"] @@ -35282,7 +33930,6 @@ pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] #[doc = "## Safety"] @@ -35306,7 +33953,6 @@ pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] #[doc = "## Safety"] @@ -35330,7 +33976,6 @@ pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { transmute(a) } - #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] #[doc = "## Safety"] @@ -35354,7 +33999,6 @@ pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { transmute(a) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"] #[doc = "## Safety"] @@ -35386,7 +34030,6 @@ pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vrhadd_s8(a, b) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"] #[doc = "## Safety"] @@ -35418,7 +34061,6 @@ pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vrhaddq_s8(a, b) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"] #[doc = "## Safety"] @@ -35450,7 +34092,6 @@ pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vrhadd_s16(a, b) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"] #[doc = "## Safety"] @@ -35482,7 +34123,6 @@ pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vrhaddq_s16(a, b) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"] #[doc = "## Safety"] @@ -35514,7 +34154,6 @@ pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vrhadd_s32(a, b) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"] #[doc = "## Safety"] @@ -35546,7 +34185,6 @@ pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vrhaddq_s32(a, b) } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"] #[doc = "## Safety"] @@ -35578,7 +34216,6 @@ pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } _vrhadd_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"] #[doc = "## Safety"] @@ -35610,7 +34247,6 @@ pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } _vrhaddq_u8(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"] #[doc = "## Safety"] @@ -35642,7 +34278,6 @@ pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } _vrhadd_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"] #[doc = "## Safety"] @@ -35674,7 +34309,6 @@ pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } _vrhaddq_u16(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"] #[doc = "## Safety"] @@ -35706,7 +34340,6 @@ pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } _vrhadd_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"] #[doc = "## Safety"] @@ -35738,7 +34371,6 @@ pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } _vrhaddq_u32(a.as_signed(), b.as_signed()).as_unsigned() } - #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"] #[doc = "## Safety"] @@ -35770,7 +34402,6 @@ pub unsafe fn vrndn_f32(a: float32x2_t) -> float32x2_t { } _vrndn_f32(a) } - #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"] #[doc = "## Safety"] @@ -35802,7 +34433,6 @@ pub unsafe fn vrndnq_f32(a: float32x4_t) -> float32x4_t { } _vrndnq_f32(a) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"] #[doc = "## Safety"] @@ -35834,7 +34464,6 @@ pub unsafe fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vrshl_s8(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"] #[doc = "## Safety"] @@ -35866,7 +34495,6 @@ pub unsafe fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vrshlq_s8(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"] #[doc = "## Safety"] @@ -35898,7 +34526,6 @@ pub unsafe fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vrshl_s16(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"] #[doc = "## Safety"] @@ -35930,7 +34557,6 @@ pub unsafe fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vrshlq_s16(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"] #[doc = "## Safety"] @@ -35962,7 +34588,6 @@ pub unsafe fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vrshl_s32(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"] #[doc = "## Safety"] @@ -35994,7 +34619,6 @@ pub unsafe fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vrshlq_s32(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"] #[doc = "## Safety"] @@ -36026,7 +34650,6 @@ pub unsafe fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } _vrshl_s64(a, b) } - #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"] #[doc = "## Safety"] @@ -36058,7 +34681,6 @@ pub unsafe fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } _vrshlq_s64(a, b) } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"] #[doc = "## Safety"] @@ -36090,7 +34712,6 @@ pub unsafe fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } _vrshl_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"] #[doc = "## Safety"] @@ -36122,7 +34743,6 @@ pub unsafe fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } _vrshlq_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"] #[doc = "## Safety"] @@ -36154,7 +34774,6 @@ pub unsafe fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } _vrshl_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"] #[doc = "## Safety"] @@ -36186,7 +34805,6 @@ pub unsafe fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } _vrshlq_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"] #[doc = "## Safety"] @@ -36218,7 +34836,6 @@ pub unsafe fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } _vrshl_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"] #[doc = "## Safety"] @@ -36250,7 +34867,6 @@ pub unsafe fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } _vrshlq_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"] #[doc = "## Safety"] @@ -36282,7 +34898,6 @@ pub unsafe fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } _vrshl_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"] #[doc = "## Safety"] @@ -36314,7 +34929,6 @@ pub unsafe fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } _vrshlq_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"] #[doc = "## Safety"] @@ -36340,7 +34954,6 @@ pub unsafe fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); vrshl_s8(a, vdup_n_s8(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"] #[doc = "## Safety"] @@ -36366,7 +34979,6 @@ pub unsafe fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); vrshlq_s8(a, vdupq_n_s8(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"] #[doc = "## Safety"] @@ -36392,7 +35004,6 @@ pub unsafe fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); vrshl_s16(a, vdup_n_s16(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"] #[doc = "## Safety"] @@ -36418,7 +35029,6 @@ pub unsafe fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); vrshlq_s16(a, vdupq_n_s16(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"] #[doc = "## Safety"] @@ -36444,7 +35054,6 @@ pub unsafe fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); vrshl_s32(a, vdup_n_s32(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"] #[doc = "## Safety"] @@ -36470,7 +35079,6 @@ pub unsafe fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); vrshlq_s32(a, vdupq_n_s32(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"] #[doc = "## Safety"] @@ -36496,7 +35104,6 @@ pub unsafe fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); vrshl_s64(a, vdup_n_s64(-N as _)) } - #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"] #[doc = "## Safety"] @@ -36522,7 +35129,6 @@ pub unsafe fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); vrshlq_s64(a, vdupq_n_s64(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"] #[doc = "## Safety"] @@ -36548,7 +35154,6 @@ pub unsafe fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); vrshl_u8(a, vdup_n_s8(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"] #[doc = "## Safety"] @@ -36574,7 +35179,6 @@ pub unsafe fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); vrshlq_u8(a, vdupq_n_s8(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"] #[doc = "## Safety"] @@ -36600,7 +35204,6 @@ pub unsafe fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); vrshl_u16(a, vdup_n_s16(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"] #[doc = "## Safety"] @@ -36626,7 +35229,6 @@ pub unsafe fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); vrshlq_u16(a, vdupq_n_s16(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"] #[doc = "## Safety"] @@ -36652,7 +35254,6 @@ pub unsafe fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); vrshl_u32(a, vdup_n_s32(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"] #[doc = "## Safety"] @@ -36678,7 +35279,6 @@ pub unsafe fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); vrshlq_u32(a, vdupq_n_s32(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"] #[doc = "## Safety"] @@ -36704,7 +35304,6 @@ pub unsafe fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); vrshl_u64(a, vdup_n_s64(-N as _)) } - #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"] #[doc = "## Safety"] @@ -36730,7 +35329,6 @@ pub unsafe fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); vrshlq_u64(a, vdupq_n_s64(-N as _)) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] #[doc = "## Safety"] @@ -36757,7 +35355,6 @@ pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { }, ) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] #[doc = "## Safety"] @@ -36779,7 +35376,6 @@ pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, ) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] #[doc = "## Safety"] @@ -36798,7 +35394,6 @@ pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { } _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] #[doc = "## Safety"] @@ -36820,7 +35415,6 @@ pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { } _vrshrn_n_s16(a, N) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] #[doc = "## Safety"] @@ -36842,7 +35436,6 @@ pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { } _vrshrn_n_s32(a, N) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] #[doc = "## Safety"] @@ -36864,7 +35457,6 @@ pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { } _vrshrn_n_s64(a, N) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"] #[doc = "## Safety"] @@ -36890,7 +35482,6 @@ pub unsafe fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); transmute(vrshrn_n_s16::(transmute(a))) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"] #[doc = "## Safety"] @@ -36916,7 +35507,6 @@ pub unsafe fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); transmute(vrshrn_n_s32::(transmute(a))) } - #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"] #[doc = "## Safety"] @@ -36942,7 +35532,6 @@ pub unsafe fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); transmute(vrshrn_n_s64::(transmute(a))) } - #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"] #[doc = "## Safety"] @@ -36974,7 +35563,6 @@ pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { } _vrsqrte_f32(a) } - #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"] #[doc = "## Safety"] @@ -37006,7 +35594,6 @@ pub unsafe fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { } _vrsqrteq_f32(a) } - #[doc = "Unsigned reciprocal square root estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"] #[doc = "## Safety"] @@ -37038,7 +35625,6 @@ pub unsafe fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { } _vrsqrte_u32(a.as_signed()).as_unsigned() } - #[doc = "Unsigned reciprocal square root estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"] #[doc = "## Safety"] @@ -37070,7 +35656,6 @@ pub unsafe fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { } _vrsqrteq_u32(a.as_signed()).as_unsigned() } - #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"] #[doc = "## Safety"] @@ -37102,7 +35687,6 @@ pub unsafe fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } _vrsqrts_f32(a, b) } - #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"] #[doc = "## Safety"] @@ -37134,7 +35718,6 @@ pub unsafe fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } _vrsqrtsq_f32(a, b) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"] #[doc = "## Safety"] @@ -37160,7 +35743,6 @@ pub unsafe fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); simd_add(a, vrshr_n_s8::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"] #[doc = "## Safety"] @@ -37186,7 +35768,6 @@ pub unsafe fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t static_assert!(N >= 1 && N <= 8); simd_add(a, vrshrq_n_s8::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"] #[doc = "## Safety"] @@ -37212,7 +35793,6 @@ pub unsafe fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t static_assert!(N >= 1 && N <= 16); simd_add(a, vrshr_n_s16::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"] #[doc = "## Safety"] @@ -37238,7 +35818,6 @@ pub unsafe fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_ static_assert!(N >= 1 && N <= 16); simd_add(a, vrshrq_n_s16::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"] #[doc = "## Safety"] @@ -37264,7 +35843,6 @@ pub unsafe fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t static_assert!(N >= 1 && N <= 32); simd_add(a, vrshr_n_s32::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"] #[doc = "## Safety"] @@ -37290,7 +35868,6 @@ pub unsafe fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_ static_assert!(N >= 1 && N <= 32); simd_add(a, vrshrq_n_s32::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"] #[doc = "## Safety"] @@ -37316,7 +35893,6 @@ pub unsafe fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t static_assert!(N >= 1 && N <= 64); simd_add(a, vrshr_n_s64::(b)) } - #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"] #[doc = "## Safety"] @@ -37342,7 +35918,6 @@ pub unsafe fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_ static_assert!(N >= 1 && N <= 64); simd_add(a, vrshrq_n_s64::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"] #[doc = "## Safety"] @@ -37368,7 +35943,6 @@ pub unsafe fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t static_assert!(N >= 1 && N <= 8); simd_add(a, vrshr_n_u8::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"] #[doc = "## Safety"] @@ -37394,7 +35968,6 @@ pub unsafe fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x1 static_assert!(N >= 1 && N <= 8); simd_add(a, vrshrq_n_u8::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"] #[doc = "## Safety"] @@ -37420,7 +35993,6 @@ pub unsafe fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x static_assert!(N >= 1 && N <= 16); simd_add(a, vrshr_n_u16::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] #[doc = "## Safety"] @@ -37446,7 +36018,6 @@ pub unsafe fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16 static_assert!(N >= 1 && N <= 16); simd_add(a, vrshrq_n_u16::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] #[doc = "## Safety"] @@ -37472,7 +36043,6 @@ pub unsafe fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x static_assert!(N >= 1 && N <= 32); simd_add(a, vrshr_n_u32::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] #[doc = "## Safety"] @@ -37498,7 +36068,6 @@ pub unsafe fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32 static_assert!(N >= 1 && N <= 32); simd_add(a, vrshrq_n_u32::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] #[doc = "## Safety"] @@ -37524,7 +36093,6 @@ pub unsafe fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x static_assert!(N >= 1 && N <= 64); simd_add(a, vrshr_n_u64::(b)) } - #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] #[doc = "## Safety"] @@ -37550,7 +36118,6 @@ pub unsafe fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64 static_assert!(N >= 1 && N <= 64); simd_add(a, vrshrq_n_u64::(b)) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] #[doc = "## Safety"] @@ -37582,7 +36149,6 @@ pub unsafe fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { } _vrsubhn_s16(a, b) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] #[doc = "## Safety"] @@ -37614,7 +36180,6 @@ pub unsafe fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { } _vrsubhn_s32(a, b) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] #[doc = "## Safety"] @@ -37646,7 +36211,6 @@ pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { } _vrsubhn_s64(a, b) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] #[doc = "## Safety"] @@ -37670,7 +36234,6 @@ pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { transmute(vrsubhn_s16(transmute(a), transmute(b))) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] #[doc = "## Safety"] @@ -37694,7 +36257,6 @@ pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { transmute(vrsubhn_s32(transmute(a), transmute(b))) } - #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] #[doc = "## Safety"] @@ -37718,7 +36280,6 @@ pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { transmute(vrsubhn_s64(transmute(a), transmute(b))) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] #[doc = "## Safety"] @@ -37744,7 +36305,6 @@ pub unsafe fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] #[doc = "## Safety"] @@ -37770,7 +36330,6 @@ pub unsafe fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32 static_assert_uimm_bits!(LANE, 2); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] #[doc = "## Safety"] @@ -37796,7 +36355,6 @@ pub unsafe fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(LANE, 3); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] #[doc = "## Safety"] @@ -37822,7 +36380,6 @@ pub unsafe fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(LANE, 4); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] #[doc = "## Safety"] @@ -37848,7 +36405,6 @@ pub unsafe fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t static_assert_uimm_bits!(LANE, 2); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] #[doc = "## Safety"] @@ -37874,7 +36430,6 @@ pub unsafe fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t static_assert_uimm_bits!(LANE, 3); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] #[doc = "## Safety"] @@ -37900,7 +36455,6 @@ pub unsafe fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] #[doc = "## Safety"] @@ -37926,7 +36480,6 @@ pub unsafe fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t static_assert_uimm_bits!(LANE, 2); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] #[doc = "## Safety"] @@ -37952,7 +36505,6 @@ pub unsafe fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] #[doc = "## Safety"] @@ -37978,7 +36530,6 @@ pub unsafe fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(LANE, 3); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] #[doc = "## Safety"] @@ -38004,7 +36555,6 @@ pub unsafe fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t static_assert_uimm_bits!(LANE, 4); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] #[doc = "## Safety"] @@ -38030,7 +36580,6 @@ pub unsafe fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_ static_assert_uimm_bits!(LANE, 2); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] #[doc = "## Safety"] @@ -38056,7 +36605,6 @@ pub unsafe fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8 static_assert_uimm_bits!(LANE, 3); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] #[doc = "## Safety"] @@ -38082,7 +36630,6 @@ pub unsafe fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_ static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] #[doc = "## Safety"] @@ -38108,7 +36655,6 @@ pub unsafe fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4 static_assert_uimm_bits!(LANE, 2); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] #[doc = "## Safety"] @@ -38134,7 +36680,6 @@ pub unsafe fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2 static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] #[doc = "## Safety"] @@ -38160,7 +36705,6 @@ pub unsafe fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(LANE, 3); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] #[doc = "## Safety"] @@ -38186,7 +36730,6 @@ pub unsafe fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t static_assert_uimm_bits!(LANE, 4); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] #[doc = "## Safety"] @@ -38212,7 +36755,6 @@ pub unsafe fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_ static_assert_uimm_bits!(LANE, 2); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] #[doc = "## Safety"] @@ -38238,7 +36780,6 @@ pub unsafe fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8 static_assert_uimm_bits!(LANE, 3); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] #[doc = "## Safety"] @@ -38264,7 +36805,6 @@ pub unsafe fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_ static_assert!(LANE == 0); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"] #[doc = "## Safety"] @@ -38290,7 +36830,6 @@ pub unsafe fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t static_assert!(LANE == 0); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"] #[doc = "## Safety"] @@ -38316,7 +36855,6 @@ pub unsafe fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_ static_assert!(LANE == 0); simd_insert!(b, LANE as u32, a) } - #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] #[doc = "## Safety"] @@ -38342,7 +36880,6 @@ pub unsafe fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2 static_assert_uimm_bits!(LANE, 1); simd_insert!(b, LANE as u32, a) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"] #[doc = "## Safety"] @@ -38368,7 +36905,6 @@ pub unsafe fn vshl_n_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); simd_shl(a, vdup_n_s8(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"] #[doc = "## Safety"] @@ -38394,7 +36930,6 @@ pub unsafe fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); simd_shl(a, vdupq_n_s8(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"] #[doc = "## Safety"] @@ -38420,7 +36955,6 @@ pub unsafe fn vshl_n_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 4); simd_shl(a, vdup_n_s16(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"] #[doc = "## Safety"] @@ -38446,7 +36980,6 @@ pub unsafe fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 4); simd_shl(a, vdupq_n_s16(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"] #[doc = "## Safety"] @@ -38472,7 +37005,6 @@ pub unsafe fn vshl_n_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 5); simd_shl(a, vdup_n_s32(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"] #[doc = "## Safety"] @@ -38498,7 +37030,6 @@ pub unsafe fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 5); simd_shl(a, vdupq_n_s32(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"] #[doc = "## Safety"] @@ -38524,7 +37055,6 @@ pub unsafe fn vshl_n_s64(a: int64x1_t) -> int64x1_t { static_assert_uimm_bits!(N, 6); simd_shl(a, vdup_n_s64(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"] #[doc = "## Safety"] @@ -38550,7 +37080,6 @@ pub unsafe fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 6); simd_shl(a, vdupq_n_s64(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"] #[doc = "## Safety"] @@ -38576,7 +37105,6 @@ pub unsafe fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); simd_shl(a, vdup_n_u8(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"] #[doc = "## Safety"] @@ -38602,7 +37130,6 @@ pub unsafe fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); simd_shl(a, vdupq_n_u8(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"] #[doc = "## Safety"] @@ -38628,7 +37155,6 @@ pub unsafe fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); simd_shl(a, vdup_n_u16(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"] #[doc = "## Safety"] @@ -38654,7 +37180,6 @@ pub unsafe fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); simd_shl(a, vdupq_n_u16(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"] #[doc = "## Safety"] @@ -38680,7 +37205,6 @@ pub unsafe fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 5); simd_shl(a, vdup_n_u32(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"] #[doc = "## Safety"] @@ -38706,7 +37230,6 @@ pub unsafe fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 5); simd_shl(a, vdupq_n_u32(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"] #[doc = "## Safety"] @@ -38732,7 +37255,6 @@ pub unsafe fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert_uimm_bits!(N, 6); simd_shl(a, vdup_n_u64(N as _)) } - #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"] #[doc = "## Safety"] @@ -38758,7 +37280,6 @@ pub unsafe fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 6); simd_shl(a, vdupq_n_u64(N as _)) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"] #[doc = "## Safety"] @@ -38790,7 +37311,6 @@ pub unsafe fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } _vshl_s8(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"] #[doc = "## Safety"] @@ -38822,7 +37342,6 @@ pub unsafe fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } _vshlq_s8(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"] #[doc = "## Safety"] @@ -38854,7 +37373,6 @@ pub unsafe fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } _vshl_s16(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"] #[doc = "## Safety"] @@ -38886,7 +37404,6 @@ pub unsafe fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } _vshlq_s16(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"] #[doc = "## Safety"] @@ -38918,7 +37435,6 @@ pub unsafe fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } _vshl_s32(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"] #[doc = "## Safety"] @@ -38950,7 +37466,6 @@ pub unsafe fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } _vshlq_s32(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"] #[doc = "## Safety"] @@ -38982,7 +37497,6 @@ pub unsafe fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } _vshl_s64(a, b) } - #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"] #[doc = "## Safety"] @@ -39014,7 +37528,6 @@ pub unsafe fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } _vshlq_s64(a, b) } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"] #[doc = "## Safety"] @@ -39046,7 +37559,6 @@ pub unsafe fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } _vshl_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"] #[doc = "## Safety"] @@ -39078,7 +37590,6 @@ pub unsafe fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } _vshlq_u8(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"] #[doc = "## Safety"] @@ -39110,7 +37621,6 @@ pub unsafe fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } _vshl_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"] #[doc = "## Safety"] @@ -39142,7 +37652,6 @@ pub unsafe fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } _vshlq_u16(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"] #[doc = "## Safety"] @@ -39174,7 +37683,6 @@ pub unsafe fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } _vshl_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"] #[doc = "## Safety"] @@ -39206,7 +37714,6 @@ pub unsafe fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } _vshlq_u32(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"] #[doc = "## Safety"] @@ -39238,7 +37745,6 @@ pub unsafe fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } _vshl_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"] #[doc = "## Safety"] @@ -39270,7 +37776,6 @@ pub unsafe fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } _vshlq_u64(a.as_signed(), b).as_unsigned() } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"] #[doc = "## Safety"] @@ -39296,7 +37801,6 @@ pub unsafe fn vshll_n_s16(a: int16x4_t) -> int32x4_t { static_assert!(N >= 0 && N <= 16); simd_shl(simd_cast(a), vdupq_n_s32(N as _)) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"] #[doc = "## Safety"] @@ -39322,7 +37826,6 @@ pub unsafe fn vshll_n_s32(a: int32x2_t) -> int64x2_t { static_assert!(N >= 0 && N <= 32); simd_shl(simd_cast(a), vdupq_n_s64(N as _)) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"] #[doc = "## Safety"] @@ -39348,7 +37851,6 @@ pub unsafe fn vshll_n_s8(a: int8x8_t) -> int16x8_t { static_assert!(N >= 0 && N <= 8); simd_shl(simd_cast(a), vdupq_n_s16(N as _)) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"] #[doc = "## Safety"] @@ -39374,7 +37876,6 @@ pub unsafe fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 16); simd_shl(simd_cast(a), vdupq_n_u32(N as _)) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"] #[doc = "## Safety"] @@ -39400,7 +37901,6 @@ pub unsafe fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 32); simd_shl(simd_cast(a), vdupq_n_u64(N as _)) } - #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"] #[doc = "## Safety"] @@ -39426,7 +37926,6 @@ pub unsafe fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { static_assert!(N >= 0 && N <= 8); simd_shl(simd_cast(a), vdupq_n_u16(N as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"] #[doc = "## Safety"] @@ -39453,7 +37952,6 @@ pub unsafe fn vshr_n_s8(a: int8x8_t) -> int8x8_t { let n: i32 = if N == 8 { 7 } else { N }; simd_shr(a, vdup_n_s8(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"] #[doc = "## Safety"] @@ -39480,7 +37978,6 @@ pub unsafe fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { let n: i32 = if N == 8 { 7 } else { N }; simd_shr(a, vdupq_n_s8(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"] #[doc = "## Safety"] @@ -39507,7 +38004,6 @@ pub unsafe fn vshr_n_s16(a: int16x4_t) -> int16x4_t { let n: i32 = if N == 16 { 15 } else { N }; simd_shr(a, vdup_n_s16(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"] #[doc = "## Safety"] @@ -39534,7 +38030,6 @@ pub unsafe fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { let n: i32 = if N == 16 { 15 } else { N }; simd_shr(a, vdupq_n_s16(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"] #[doc = "## Safety"] @@ -39561,7 +38056,6 @@ pub unsafe fn vshr_n_s32(a: int32x2_t) -> int32x2_t { let n: i32 = if N == 32 { 31 } else { N }; simd_shr(a, vdup_n_s32(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"] #[doc = "## Safety"] @@ -39588,7 +38082,6 @@ pub unsafe fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { let n: i32 = if N == 32 { 31 } else { N }; simd_shr(a, vdupq_n_s32(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"] #[doc = "## Safety"] @@ -39615,7 +38108,6 @@ pub unsafe fn vshr_n_s64(a: int64x1_t) -> int64x1_t { let n: i32 = if N == 64 { 63 } else { N }; simd_shr(a, vdup_n_s64(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"] #[doc = "## Safety"] @@ -39642,7 +38134,6 @@ pub unsafe fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { let n: i32 = if N == 64 { 63 } else { N }; simd_shr(a, vdupq_n_s64(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"] #[doc = "## Safety"] @@ -39673,7 +38164,6 @@ pub unsafe fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { }; simd_shr(a, vdup_n_u8(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"] #[doc = "## Safety"] @@ -39704,7 +38194,6 @@ pub unsafe fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { }; simd_shr(a, vdupq_n_u8(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"] #[doc = "## Safety"] @@ -39735,7 +38224,6 @@ pub unsafe fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { }; simd_shr(a, vdup_n_u16(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"] #[doc = "## Safety"] @@ -39766,7 +38254,6 @@ pub unsafe fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { }; simd_shr(a, vdupq_n_u16(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"] #[doc = "## Safety"] @@ -39797,7 +38284,6 @@ pub unsafe fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { }; simd_shr(a, vdup_n_u32(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"] #[doc = "## Safety"] @@ -39828,7 +38314,6 @@ pub unsafe fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { }; simd_shr(a, vdupq_n_u32(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"] #[doc = "## Safety"] @@ -39859,7 +38344,6 @@ pub unsafe fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { }; simd_shr(a, vdup_n_u64(n as _)) } - #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"] #[doc = "## Safety"] @@ -39890,7 +38374,6 @@ pub unsafe fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { }; simd_shr(a, vdupq_n_u64(n as _)) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"] #[doc = "## Safety"] @@ -39916,7 +38399,6 @@ pub unsafe fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); simd_cast(simd_shr(a, vdupq_n_s16(N as _))) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"] #[doc = "## Safety"] @@ -39942,7 +38424,6 @@ pub unsafe fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); simd_cast(simd_shr(a, vdupq_n_s32(N as _))) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"] #[doc = "## Safety"] @@ -39968,7 +38449,6 @@ pub unsafe fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); simd_cast(simd_shr(a, vdupq_n_s64(N as _))) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"] #[doc = "## Safety"] @@ -39994,7 +38474,6 @@ pub unsafe fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); simd_cast(simd_shr(a, vdupq_n_u16(N as _))) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"] #[doc = "## Safety"] @@ -40020,7 +38499,6 @@ pub unsafe fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); simd_cast(simd_shr(a, vdupq_n_u32(N as _))) } - #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"] #[doc = "## Safety"] @@ -40046,7 +38524,6 @@ pub unsafe fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); simd_cast(simd_shr(a, vdupq_n_u64(N as _))) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"] #[doc = "## Safety"] @@ -40072,7 +38549,6 @@ pub unsafe fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); simd_add(a, vshr_n_s8::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"] #[doc = "## Safety"] @@ -40098,7 +38574,6 @@ pub unsafe fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t static_assert!(N >= 1 && N <= 8); simd_add(a, vshrq_n_s8::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"] #[doc = "## Safety"] @@ -40124,7 +38599,6 @@ pub unsafe fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t static_assert!(N >= 1 && N <= 16); simd_add(a, vshr_n_s16::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"] #[doc = "## Safety"] @@ -40150,7 +38624,6 @@ pub unsafe fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t static_assert!(N >= 1 && N <= 16); simd_add(a, vshrq_n_s16::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"] #[doc = "## Safety"] @@ -40176,7 +38649,6 @@ pub unsafe fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t static_assert!(N >= 1 && N <= 32); simd_add(a, vshr_n_s32::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"] #[doc = "## Safety"] @@ -40202,7 +38674,6 @@ pub unsafe fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t static_assert!(N >= 1 && N <= 32); simd_add(a, vshrq_n_s32::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"] #[doc = "## Safety"] @@ -40228,7 +38699,6 @@ pub unsafe fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t static_assert!(N >= 1 && N <= 64); simd_add(a, vshr_n_s64::(b)) } - #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"] #[doc = "## Safety"] @@ -40254,7 +38724,6 @@ pub unsafe fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t static_assert!(N >= 1 && N <= 64); simd_add(a, vshrq_n_s64::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"] #[doc = "## Safety"] @@ -40280,7 +38749,6 @@ pub unsafe fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); simd_add(a, vshr_n_u8::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"] #[doc = "## Safety"] @@ -40306,7 +38774,6 @@ pub unsafe fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16 static_assert!(N >= 1 && N <= 8); simd_add(a, vshrq_n_u8::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"] #[doc = "## Safety"] @@ -40332,7 +38799,6 @@ pub unsafe fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4 static_assert!(N >= 1 && N <= 16); simd_add(a, vshr_n_u16::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"] #[doc = "## Safety"] @@ -40358,7 +38824,6 @@ pub unsafe fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x static_assert!(N >= 1 && N <= 16); simd_add(a, vshrq_n_u16::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"] #[doc = "## Safety"] @@ -40384,7 +38849,6 @@ pub unsafe fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2 static_assert!(N >= 1 && N <= 32); simd_add(a, vshr_n_u32::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"] #[doc = "## Safety"] @@ -40410,7 +38874,6 @@ pub unsafe fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x static_assert!(N >= 1 && N <= 32); simd_add(a, vshrq_n_u32::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"] #[doc = "## Safety"] @@ -40436,7 +38899,6 @@ pub unsafe fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1 static_assert!(N >= 1 && N <= 64); simd_add(a, vshr_n_u64::(b)) } - #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"] #[doc = "## Safety"] @@ -40462,7 +38924,6 @@ pub unsafe fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x static_assert!(N >= 1 && N <= 64); simd_add(a, vshrq_n_u64::(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] @@ -40479,7 +38940,6 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { } _vst1_f32_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] @@ -40496,7 +38956,6 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { } _vst1q_f32_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] @@ -40516,7 +38975,6 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { } _vst1_f32_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] @@ -40536,7 +38994,6 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { } _vst1q_f32_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] #[doc = "## Safety"] @@ -40553,7 +39010,6 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { } _vst1_f32_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] #[doc = "## Safety"] @@ -40570,7 +39026,6 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { } _vst1q_f32_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] #[doc = "## Safety"] @@ -40590,7 +39045,6 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { } _vst1_f32_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] #[doc = "## Safety"] @@ -40610,7 +39064,6 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { } _vst1q_f32_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] @@ -40633,7 +39086,6 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { } _vst1_f32_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] @@ -40656,7 +39108,6 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { } _vst1q_f32_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] @@ -40682,7 +39133,6 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { } _vst1_f32_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] @@ -40708,7 +39158,6 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { } _vst1q_f32_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"] #[doc = "## Safety"] @@ -40734,7 +39183,6 @@ pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"] #[doc = "## Safety"] @@ -40760,7 +39208,6 @@ pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { static_assert_uimm_bits!(LANE, 2); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"] #[doc = "## Safety"] @@ -40786,7 +39233,6 @@ pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { static_assert_uimm_bits!(LANE, 3); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"] #[doc = "## Safety"] @@ -40812,7 +39258,6 @@ pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { static_assert_uimm_bits!(LANE, 4); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"] #[doc = "## Safety"] @@ -40838,7 +39283,6 @@ pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { static_assert_uimm_bits!(LANE, 2); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"] #[doc = "## Safety"] @@ -40864,7 +39308,6 @@ pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { static_assert_uimm_bits!(LANE, 3); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"] #[doc = "## Safety"] @@ -40890,7 +39333,6 @@ pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"] #[doc = "## Safety"] @@ -40916,7 +39358,6 @@ pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { static_assert_uimm_bits!(LANE, 2); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"] #[doc = "## Safety"] @@ -40942,7 +39383,6 @@ pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"] #[doc = "## Safety"] @@ -40968,7 +39408,6 @@ pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { static_assert_uimm_bits!(LANE, 3); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"] #[doc = "## Safety"] @@ -40994,7 +39433,6 @@ pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { static_assert_uimm_bits!(LANE, 4); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"] #[doc = "## Safety"] @@ -41020,7 +39458,6 @@ pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { static_assert_uimm_bits!(LANE, 2); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"] #[doc = "## Safety"] @@ -41046,7 +39483,6 @@ pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { static_assert_uimm_bits!(LANE, 3); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"] #[doc = "## Safety"] @@ -41072,7 +39508,6 @@ pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"] #[doc = "## Safety"] @@ -41098,7 +39533,6 @@ pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { static_assert_uimm_bits!(LANE, 2); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"] #[doc = "## Safety"] @@ -41124,7 +39558,6 @@ pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"] #[doc = "## Safety"] @@ -41150,7 +39583,6 @@ pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { static_assert_uimm_bits!(LANE, 3); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"] #[doc = "## Safety"] @@ -41176,7 +39608,6 @@ pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { static_assert_uimm_bits!(LANE, 4); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"] #[doc = "## Safety"] @@ -41202,7 +39633,6 @@ pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { static_assert_uimm_bits!(LANE, 2); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"] #[doc = "## Safety"] @@ -41228,7 +39658,6 @@ pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { static_assert_uimm_bits!(LANE, 3); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"] #[doc = "## Safety"] @@ -41254,7 +39683,6 @@ pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { static_assert!(LANE == 0); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"] #[doc = "## Safety"] @@ -41280,7 +39708,6 @@ pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { static_assert!(LANE == 0); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"] #[doc = "## Safety"] @@ -41306,7 +39733,6 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { static_assert!(LANE == 0); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"] #[doc = "## Safety"] @@ -41330,7 +39756,6 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { vst1_s64_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"] #[doc = "## Safety"] @@ -41354,7 +39779,6 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { vst1_s64_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"] #[doc = "## Safety"] @@ -41378,7 +39802,6 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { vst1_s64_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"] #[doc = "## Safety"] @@ -41402,7 +39825,6 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { vst1q_s64_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"] #[doc = "## Safety"] @@ -41426,7 +39848,6 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { vst1q_s64_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"] #[doc = "## Safety"] @@ -41450,7 +39871,6 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { vst1q_s64_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] @@ -41470,7 +39890,6 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { } _vst1_s8_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] @@ -41490,7 +39909,6 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { } _vst1q_s8_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] @@ -41510,7 +39928,6 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { } _vst1_s16_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] @@ -41530,7 +39947,6 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { } _vst1q_s16_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] @@ -41550,7 +39966,6 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { } _vst1_s32_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] @@ -41570,7 +39985,6 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { } _vst1q_s32_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] @@ -41590,7 +40004,6 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { } _vst1_s64_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] @@ -41610,7 +40023,6 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { } _vst1q_s64_x2(b.0, b.1, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] @@ -41627,7 +40039,6 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { } _vst1_s8_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] @@ -41644,7 +40055,6 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { } _vst1q_s8_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] @@ -41661,7 +40071,6 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { } _vst1_s16_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] @@ -41678,7 +40087,6 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { } _vst1q_s16_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] @@ -41695,7 +40103,6 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { } _vst1_s32_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] @@ -41712,7 +40119,6 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { } _vst1q_s32_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] @@ -41729,7 +40135,6 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { } _vst1_s64_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] @@ -41746,7 +40151,6 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { } _vst1q_s64_x2(a, b.0, b.1) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] @@ -41766,7 +40170,6 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { } _vst1_s8_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] @@ -41786,7 +40189,6 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { } _vst1q_s8_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] @@ -41806,7 +40208,6 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { } _vst1_s16_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] @@ -41826,7 +40227,6 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { } _vst1q_s16_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] @@ -41846,7 +40246,6 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { } _vst1_s32_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] @@ -41866,7 +40265,6 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { } _vst1q_s32_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] @@ -41886,7 +40284,6 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { } _vst1_s64_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] @@ -41906,7 +40303,6 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { } _vst1q_s64_x3(b.0, b.1, b.2, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] @@ -41923,7 +40319,6 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { } _vst1_s8_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] @@ -41940,7 +40335,6 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { } _vst1q_s8_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] @@ -41957,7 +40351,6 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { } _vst1_s16_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] @@ -41974,7 +40367,6 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { } _vst1q_s16_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] @@ -41991,7 +40383,6 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { } _vst1_s32_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] @@ -42008,7 +40399,6 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { } _vst1q_s32_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] @@ -42025,7 +40415,6 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { } _vst1_s64_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] @@ -42042,7 +40431,6 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { } _vst1q_s64_x3(a, b.0, b.1, b.2) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] @@ -42062,7 +40450,6 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { } _vst1_s8_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] @@ -42082,7 +40469,6 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { } _vst1q_s8_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] @@ -42102,7 +40488,6 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { } _vst1_s16_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] @@ -42122,7 +40507,6 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { } _vst1q_s16_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] @@ -42142,7 +40526,6 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { } _vst1_s32_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] @@ -42162,7 +40545,6 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { } _vst1q_s32_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] @@ -42182,7 +40564,6 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { } _vst1_s64_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] @@ -42202,7 +40583,6 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { } _vst1q_s64_x4(b.0, b.1, b.2, b.3, a) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] @@ -42219,7 +40599,6 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { } _vst1_s8_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] @@ -42236,7 +40615,6 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { } _vst1q_s8_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] @@ -42253,7 +40631,6 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { } _vst1_s16_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] @@ -42270,7 +40647,6 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { } _vst1q_s16_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] @@ -42287,7 +40663,6 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { } _vst1_s32_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] @@ -42304,7 +40679,6 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { } _vst1q_s32_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] @@ -42321,7 +40695,6 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { } _vst1_s64_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] @@ -42338,7 +40711,6 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { } _vst1q_s64_x4(a, b.0, b.1, b.2, b.3) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"] #[doc = "## Safety"] @@ -42362,7 +40734,6 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { vst1_s8_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"] #[doc = "## Safety"] @@ -42386,7 +40757,6 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { vst1_s8_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"] #[doc = "## Safety"] @@ -42410,7 +40780,6 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { vst1_s8_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"] #[doc = "## Safety"] @@ -42434,7 +40803,6 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { vst1q_s8_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"] #[doc = "## Safety"] @@ -42458,7 +40826,6 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { vst1q_s8_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"] #[doc = "## Safety"] @@ -42482,7 +40849,6 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { vst1q_s8_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"] #[doc = "## Safety"] @@ -42506,7 +40872,6 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { vst1_s16_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"] #[doc = "## Safety"] @@ -42530,7 +40895,6 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { vst1_s16_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"] #[doc = "## Safety"] @@ -42554,7 +40918,6 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { vst1_s16_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"] #[doc = "## Safety"] @@ -42578,7 +40941,6 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { vst1q_s16_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"] #[doc = "## Safety"] @@ -42602,7 +40964,6 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { vst1q_s16_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"] #[doc = "## Safety"] @@ -42626,7 +40987,6 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { vst1q_s16_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"] #[doc = "## Safety"] @@ -42650,7 +41010,6 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { vst1_s32_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"] #[doc = "## Safety"] @@ -42674,7 +41033,6 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { vst1_s32_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"] #[doc = "## Safety"] @@ -42698,7 +41056,6 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { vst1_s32_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"] #[doc = "## Safety"] @@ -42722,7 +41079,6 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { vst1q_s32_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"] #[doc = "## Safety"] @@ -42746,7 +41102,6 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { vst1q_s32_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"] #[doc = "## Safety"] @@ -42770,7 +41125,6 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { vst1q_s32_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"] #[doc = "## Safety"] @@ -42794,7 +41148,6 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { vst1_s64_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"] #[doc = "## Safety"] @@ -42818,7 +41171,6 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { vst1_s64_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"] #[doc = "## Safety"] @@ -42842,7 +41194,6 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { vst1_s64_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"] #[doc = "## Safety"] @@ -42866,7 +41217,6 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { vst1q_s64_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"] #[doc = "## Safety"] @@ -42890,7 +41240,6 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { vst1q_s64_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"] #[doc = "## Safety"] @@ -42914,7 +41263,6 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { vst1q_s64_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"] #[doc = "## Safety"] @@ -42938,7 +41286,6 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { vst1_s8_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"] #[doc = "## Safety"] @@ -42962,7 +41309,6 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { vst1_s8_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"] #[doc = "## Safety"] @@ -42986,7 +41332,6 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { vst1_s8_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"] #[doc = "## Safety"] @@ -43010,7 +41355,6 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { vst1q_s8_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"] #[doc = "## Safety"] @@ -43034,7 +41378,6 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { vst1q_s8_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"] #[doc = "## Safety"] @@ -43058,7 +41401,6 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { vst1q_s8_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"] #[doc = "## Safety"] @@ -43082,7 +41424,6 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { vst1_s16_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"] #[doc = "## Safety"] @@ -43106,7 +41447,6 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { vst1_s16_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"] #[doc = "## Safety"] @@ -43130,7 +41470,6 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { vst1_s16_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"] #[doc = "## Safety"] @@ -43154,7 +41493,6 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { vst1q_s16_x2(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"] #[doc = "## Safety"] @@ -43178,7 +41516,6 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { vst1q_s16_x3(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"] #[doc = "## Safety"] @@ -43202,7 +41539,6 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) { vst1q_s16_x4(transmute(a), transmute(b)) } - #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"] #[doc = "## Safety"] @@ -43228,7 +41564,6 @@ pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { static_assert_uimm_bits!(LANE, 1); *a = simd_extract!(b, LANE as u32); } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] @@ -43248,7 +41583,6 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { } _vst2_f32(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] @@ -43268,7 +41602,6 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { } _vst2q_f32(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] @@ -43288,7 +41621,6 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { } _vst2_s8(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] @@ -43308,7 +41640,6 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { } _vst2q_s8(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] @@ -43328,7 +41659,6 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { } _vst2_s16(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] @@ -43348,7 +41678,6 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { } _vst2q_s16(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] @@ -43368,7 +41697,6 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { } _vst2_s32(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] @@ -43388,7 +41716,6 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { } _vst2q_s32(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] @@ -43405,7 +41732,6 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { } _vst2_f32(a as _, b.0, b.1, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] @@ -43422,7 +41748,6 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { } _vst2q_f32(a as _, b.0, b.1, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] @@ -43439,7 +41764,6 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { } _vst2_s8(a as _, b.0, b.1, 1) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] @@ -43456,7 +41780,6 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { } _vst2q_s8(a as _, b.0, b.1, 1) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] @@ -43473,7 +41796,6 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { } _vst2_s16(a as _, b.0, b.1, 2) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] @@ -43490,7 +41812,6 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { } _vst2q_s16(a as _, b.0, b.1, 2) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] @@ -43507,7 +41828,6 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { } _vst2_s32(a as _, b.0, b.1, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] @@ -43524,7 +41844,6 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { } _vst2q_s32(a as _, b.0, b.1, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] @@ -43546,7 +41865,6 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { } _vst2_lane_f32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] @@ -43568,7 +41886,6 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { } _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] @@ -43590,7 +41907,6 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { } _vst2_lane_s8(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] @@ -43612,7 +41928,6 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { } _vst2_lane_s16(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] @@ -43634,7 +41949,6 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { } _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] @@ -43656,7 +41970,6 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { } _vst2_lane_s32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] @@ -43678,7 +41991,6 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { } _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] @@ -43697,7 +42009,6 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { } _vst2_lane_f32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] @@ -43716,7 +42027,6 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { } _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] @@ -43735,7 +42045,6 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { } _vst2_lane_s8(a as _, b.0, b.1, LANE, 1) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] @@ -43754,7 +42063,6 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { } _vst2_lane_s16(a as _, b.0, b.1, LANE, 2) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] @@ -43773,7 +42081,6 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { } _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] @@ -43792,7 +42099,6 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { } _vst2_lane_s32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] @@ -43811,7 +42117,6 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { } _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"] #[doc = "## Safety"] @@ -43837,7 +42142,6 @@ pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { static_assert_uimm_bits!(LANE, 3); vst2_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"] #[doc = "## Safety"] @@ -43863,7 +42167,6 @@ pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { static_assert_uimm_bits!(LANE, 2); vst2_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"] #[doc = "## Safety"] @@ -43889,7 +42192,6 @@ pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { static_assert_uimm_bits!(LANE, 3); vst2q_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"] #[doc = "## Safety"] @@ -43915,7 +42217,6 @@ pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { static_assert_uimm_bits!(LANE, 1); vst2_lane_s32::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"] #[doc = "## Safety"] @@ -43941,7 +42242,6 @@ pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { static_assert_uimm_bits!(LANE, 2); vst2q_lane_s32::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"] #[doc = "## Safety"] @@ -43967,7 +42267,6 @@ pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { static_assert_uimm_bits!(LANE, 3); vst2_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"] #[doc = "## Safety"] @@ -43993,7 +42292,6 @@ pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { static_assert_uimm_bits!(LANE, 2); vst2_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"] #[doc = "## Safety"] @@ -44019,7 +42317,6 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { static_assert_uimm_bits!(LANE, 3); vst2q_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"] #[doc = "## Safety"] @@ -44043,7 +42340,6 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { vst2_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] @@ -44060,7 +42356,6 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { } _vst2_s64(a as _, b.0, b.1, 8) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] @@ -44080,7 +42375,6 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { } _vst2_s64(b.0, b.1, a as _) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] #[doc = "## Safety"] @@ -44104,7 +42398,6 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { vst2_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"] #[doc = "## Safety"] @@ -44128,7 +42421,6 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { vst2_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"] #[doc = "## Safety"] @@ -44152,7 +42444,6 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { vst2q_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"] #[doc = "## Safety"] @@ -44176,7 +42467,6 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { vst2_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"] #[doc = "## Safety"] @@ -44200,7 +42490,6 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { vst2q_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"] #[doc = "## Safety"] @@ -44224,7 +42513,6 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { vst2_s32(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"] #[doc = "## Safety"] @@ -44248,7 +42536,6 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { vst2q_s32(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"] #[doc = "## Safety"] @@ -44272,7 +42559,6 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { vst2_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"] #[doc = "## Safety"] @@ -44296,7 +42582,6 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { vst2q_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"] #[doc = "## Safety"] @@ -44320,7 +42605,6 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { vst2_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"] #[doc = "## Safety"] @@ -44344,7 +42628,6 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { vst2q_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] @@ -44361,7 +42644,6 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { } _vst3_f32(a as _, b.0, b.1, b.2, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] @@ -44378,7 +42660,6 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { } _vst3q_f32(a as _, b.0, b.1, b.2, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] @@ -44395,7 +42676,6 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { } _vst3_s8(a as _, b.0, b.1, b.2, 1) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] @@ -44412,7 +42692,6 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { } _vst3q_s8(a as _, b.0, b.1, b.2, 1) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] @@ -44429,7 +42708,6 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { } _vst3_s16(a as _, b.0, b.1, b.2, 2) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] @@ -44446,7 +42724,6 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { } _vst3q_s16(a as _, b.0, b.1, b.2, 2) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] @@ -44463,7 +42740,6 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { } _vst3_s32(a as _, b.0, b.1, b.2, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] @@ -44480,7 +42756,6 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { } _vst3q_s32(a as _, b.0, b.1, b.2, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] @@ -44500,7 +42775,6 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { } _vst3_f32(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] @@ -44520,7 +42794,6 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { } _vst3q_f32(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] @@ -44540,7 +42813,6 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { } _vst3_s8(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] @@ -44560,7 +42832,6 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { } _vst3q_s8(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] @@ -44580,7 +42851,6 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { } _vst3_s16(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] @@ -44600,7 +42870,6 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { } _vst3q_s16(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] @@ -44620,7 +42889,6 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { } _vst3_s32(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] @@ -44640,7 +42908,6 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { } _vst3q_s32(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] @@ -44666,7 +42933,6 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { } _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] @@ -44692,7 +42958,6 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { } _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] @@ -44711,7 +42976,6 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { } _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] @@ -44737,7 +43001,6 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { } _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] @@ -44763,7 +43026,6 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { } _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] @@ -44789,7 +43051,6 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { } _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] @@ -44815,7 +43076,6 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { } _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] @@ -44837,7 +43097,6 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { } _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] @@ -44859,7 +43118,6 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { } _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] @@ -44881,7 +43139,6 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { } _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] @@ -44903,7 +43160,6 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { } _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] @@ -44925,7 +43181,6 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { } _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] @@ -44947,7 +43202,6 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { } _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] @@ -44969,7 +43223,6 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { } _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"] #[doc = "## Safety"] @@ -44995,7 +43248,6 @@ pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { static_assert_uimm_bits!(LANE, 3); vst3_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"] #[doc = "## Safety"] @@ -45021,7 +43273,6 @@ pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { static_assert_uimm_bits!(LANE, 2); vst3_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"] #[doc = "## Safety"] @@ -45047,7 +43298,6 @@ pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { static_assert_uimm_bits!(LANE, 3); vst3q_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"] #[doc = "## Safety"] @@ -45073,7 +43323,6 @@ pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { static_assert_uimm_bits!(LANE, 1); vst3_lane_s32::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"] #[doc = "## Safety"] @@ -45099,7 +43348,6 @@ pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { static_assert_uimm_bits!(LANE, 2); vst3q_lane_s32::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"] #[doc = "## Safety"] @@ -45125,7 +43373,6 @@ pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { static_assert_uimm_bits!(LANE, 3); vst3_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"] #[doc = "## Safety"] @@ -45151,7 +43398,6 @@ pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { static_assert_uimm_bits!(LANE, 2); vst3_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"] #[doc = "## Safety"] @@ -45177,7 +43423,6 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { static_assert_uimm_bits!(LANE, 3); vst3q_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"] #[doc = "## Safety"] @@ -45201,7 +43446,6 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { vst3_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] @@ -45221,7 +43465,6 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { } _vst3_s64(b.0, b.1, b.2, a as _) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] @@ -45238,7 +43481,6 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { } _vst3_s64(a as _, b.0, b.1, b.2, 8) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] #[doc = "## Safety"] @@ -45262,7 +43504,6 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { vst3_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"] #[doc = "## Safety"] @@ -45286,7 +43527,6 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { vst3_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"] #[doc = "## Safety"] @@ -45310,7 +43550,6 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { vst3q_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"] #[doc = "## Safety"] @@ -45334,7 +43573,6 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { vst3_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"] #[doc = "## Safety"] @@ -45358,7 +43596,6 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { vst3q_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"] #[doc = "## Safety"] @@ -45382,7 +43619,6 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { vst3_s32(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"] #[doc = "## Safety"] @@ -45406,7 +43642,6 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { vst3q_s32(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"] #[doc = "## Safety"] @@ -45430,7 +43665,6 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { vst3_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"] #[doc = "## Safety"] @@ -45454,7 +43688,6 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { vst3q_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"] #[doc = "## Safety"] @@ -45478,7 +43711,6 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { vst3_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"] #[doc = "## Safety"] @@ -45502,7 +43734,6 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { vst3q_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] @@ -45526,7 +43757,6 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { } _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] @@ -45550,7 +43780,6 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { } _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] @@ -45567,7 +43796,6 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { } _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] @@ -45591,7 +43819,6 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { } _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] @@ -45615,7 +43842,6 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { } _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] @@ -45639,7 +43865,6 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { } _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] @@ -45663,7 +43888,6 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { } _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] @@ -45687,7 +43911,6 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { } _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] @@ -45707,7 +43930,6 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { } _vst4_f32(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] @@ -45727,7 +43949,6 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { } _vst4q_f32(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] @@ -45747,7 +43968,6 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { } _vst4_s8(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] @@ -45767,7 +43987,6 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { } _vst4q_s8(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] @@ -45787,7 +44006,6 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { } _vst4_s16(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] @@ -45807,7 +44025,6 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { } _vst4q_s16(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] @@ -45827,7 +44044,6 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { } _vst4_s32(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] @@ -45847,7 +44063,6 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { } _vst4q_s32(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] @@ -45874,7 +44089,6 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { } _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] @@ -45901,7 +44115,6 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { } _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] @@ -45928,7 +44141,6 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { } _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] @@ -45955,7 +44167,6 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { } _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] @@ -45982,7 +44193,6 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { } _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] @@ -46009,7 +44219,6 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { } _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] @@ -46036,7 +44245,6 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { } _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] @@ -46065,7 +44273,6 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { } _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] @@ -46094,7 +44301,6 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { } _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] @@ -46116,7 +44322,6 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { } _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] @@ -46145,7 +44350,6 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { } _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] @@ -46174,7 +44378,6 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { } _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] @@ -46203,7 +44406,6 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { } _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] @@ -46232,7 +44434,6 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { } _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] #[doc = "## Safety"] @@ -46258,7 +44459,6 @@ pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { static_assert_uimm_bits!(LANE, 3); vst4_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] #[doc = "## Safety"] @@ -46284,7 +44484,6 @@ pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { static_assert_uimm_bits!(LANE, 2); vst4_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] #[doc = "## Safety"] @@ -46310,7 +44509,6 @@ pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { static_assert_uimm_bits!(LANE, 3); vst4q_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] #[doc = "## Safety"] @@ -46336,7 +44534,6 @@ pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { static_assert_uimm_bits!(LANE, 1); vst4_lane_s32::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] #[doc = "## Safety"] @@ -46362,7 +44559,6 @@ pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { static_assert_uimm_bits!(LANE, 2); vst4q_lane_s32::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] #[doc = "## Safety"] @@ -46388,7 +44584,6 @@ pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { static_assert_uimm_bits!(LANE, 3); vst4_lane_s8::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] #[doc = "## Safety"] @@ -46414,7 +44609,6 @@ pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { static_assert_uimm_bits!(LANE, 2); vst4_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] #[doc = "## Safety"] @@ -46440,7 +44634,6 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { static_assert_uimm_bits!(LANE, 3); vst4q_lane_s16::(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] #[doc = "## Safety"] @@ -46464,7 +44657,6 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { vst4_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] @@ -46488,7 +44680,6 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { } _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] @@ -46508,7 +44699,6 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { } _vst4_s64(b.0, b.1, b.2, b.3, a as _) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] #[doc = "## Safety"] @@ -46532,7 +44722,6 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { vst4_s64(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] #[doc = "## Safety"] @@ -46556,7 +44745,6 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { vst4_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] #[doc = "## Safety"] @@ -46580,7 +44768,6 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { vst4q_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] #[doc = "## Safety"] @@ -46604,7 +44791,6 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { vst4_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] #[doc = "## Safety"] @@ -46628,7 +44814,6 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { vst4q_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] #[doc = "## Safety"] @@ -46652,7 +44837,6 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { vst4_s32(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] #[doc = "## Safety"] @@ -46676,7 +44860,6 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { vst4q_s32(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] #[doc = "## Safety"] @@ -46700,7 +44883,6 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { vst4_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] #[doc = "## Safety"] @@ -46724,7 +44906,6 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { vst4q_s8(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] #[doc = "## Safety"] @@ -46748,7 +44929,6 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { vst4_s16(transmute(a), transmute(b)) } - #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] #[doc = "## Safety"] @@ -46772,7 +44952,6 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { vst4q_s16(transmute(a), transmute(b)) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] #[doc = "## Safety"] @@ -46796,7 +44975,6 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] #[doc = "## Safety"] @@ -46820,7 +44998,6 @@ pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] #[doc = "## Safety"] @@ -46844,7 +45021,6 @@ pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] #[doc = "## Safety"] @@ -46868,7 +45044,6 @@ pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] #[doc = "## Safety"] @@ -46892,7 +45067,6 @@ pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] #[doc = "## Safety"] @@ -46916,7 +45090,6 @@ pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] #[doc = "## Safety"] @@ -46940,7 +45113,6 @@ pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] #[doc = "## Safety"] @@ -46964,7 +45136,6 @@ pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] #[doc = "## Safety"] @@ -46988,7 +45159,6 @@ pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] #[doc = "## Safety"] @@ -47012,7 +45182,6 @@ pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] #[doc = "## Safety"] @@ -47036,7 +45205,6 @@ pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] #[doc = "## Safety"] @@ -47060,7 +45228,6 @@ pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] #[doc = "## Safety"] @@ -47084,7 +45251,6 @@ pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] #[doc = "## Safety"] @@ -47108,7 +45274,6 @@ pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] #[doc = "## Safety"] @@ -47132,7 +45297,6 @@ pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] #[doc = "## Safety"] @@ -47156,7 +45320,6 @@ pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] #[doc = "## Safety"] @@ -47180,7 +45343,6 @@ pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_sub(a, b) } - #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] #[doc = "## Safety"] @@ -47204,7 +45366,6 @@ pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { pub unsafe fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_sub(a, b) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] #[doc = "## Safety"] @@ -47229,7 +45390,6 @@ pub unsafe fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x1 let d: int8x8_t = vsubhn_s16(b, c); simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] #[doc = "## Safety"] @@ -47254,7 +45414,6 @@ pub unsafe fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16 let d: int16x4_t = vsubhn_s32(b, c); simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] #[doc = "## Safety"] @@ -47279,7 +45438,6 @@ pub unsafe fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32 let d: int32x2_t = vsubhn_s64(b, c); simd_shuffle!(a, d, [0, 1, 2, 3]) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] #[doc = "## Safety"] @@ -47304,7 +45462,6 @@ pub unsafe fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uin let d: uint8x8_t = vsubhn_u16(b, c); simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] #[doc = "## Safety"] @@ -47329,7 +45486,6 @@ pub unsafe fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> ui let d: uint16x4_t = vsubhn_u32(b, c); simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] #[doc = "## Safety"] @@ -47354,7 +45510,6 @@ pub unsafe fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> ui let d: uint32x2_t = vsubhn_u64(b, c); simd_shuffle!(a, d, [0, 1, 2, 3]) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] #[doc = "## Safety"] @@ -47379,7 +45534,6 @@ pub unsafe fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] #[doc = "## Safety"] @@ -47404,7 +45558,6 @@ pub unsafe fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { let c: i32x4 = i32x4::new(16, 16, 16, 16); simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] #[doc = "## Safety"] @@ -47429,7 +45582,6 @@ pub unsafe fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { let c: i64x2 = i64x2::new(32, 32); simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] #[doc = "## Safety"] @@ -47454,7 +45606,6 @@ pub unsafe fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] #[doc = "## Safety"] @@ -47479,7 +45630,6 @@ pub unsafe fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { let c: u32x4 = u32x4::new(16, 16, 16, 16); simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } - #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] #[doc = "## Safety"] @@ -47504,7 +45654,6 @@ pub unsafe fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { let c: u64x2 = u64x2::new(32, 32); simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } - #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] #[doc = "## Safety"] @@ -47530,7 +45679,6 @@ pub unsafe fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { let d: int16x8_t = simd_cast(b); simd_sub(c, d) } - #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] #[doc = "## Safety"] @@ -47556,7 +45704,6 @@ pub unsafe fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { let d: int32x4_t = simd_cast(b); simd_sub(c, d) } - #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] #[doc = "## Safety"] @@ -47582,7 +45729,6 @@ pub unsafe fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { let d: int64x2_t = simd_cast(b); simd_sub(c, d) } - #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] #[doc = "## Safety"] @@ -47608,7 +45754,6 @@ pub unsafe fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { let d: uint16x8_t = simd_cast(b); simd_sub(c, d) } - #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] #[doc = "## Safety"] @@ -47634,7 +45779,6 @@ pub unsafe fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { let d: uint32x4_t = simd_cast(b); simd_sub(c, d) } - #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] #[doc = "## Safety"] @@ -47660,7 +45804,6 @@ pub unsafe fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { let d: uint64x2_t = simd_cast(b); simd_sub(c, d) } - #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] #[doc = "## Safety"] @@ -47684,7 +45827,6 @@ pub unsafe fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { pub unsafe fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { simd_sub(a, simd_cast(b)) } - #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] #[doc = "## Safety"] @@ -47708,7 +45850,6 @@ pub unsafe fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { pub unsafe fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { simd_sub(a, simd_cast(b)) } - #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] #[doc = "## Safety"] @@ -47732,7 +45873,6 @@ pub unsafe fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { pub unsafe fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { simd_sub(a, simd_cast(b)) } - #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] #[doc = "## Safety"] @@ -47756,7 +45896,6 @@ pub unsafe fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { pub unsafe fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { simd_sub(a, simd_cast(b)) } - #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] #[doc = "## Safety"] @@ -47780,7 +45919,6 @@ pub unsafe fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { pub unsafe fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { simd_sub(a, simd_cast(b)) } - #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] #[doc = "## Safety"] @@ -47804,7 +45942,6 @@ pub unsafe fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { pub unsafe fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { simd_sub(a, simd_cast(b)) } - #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] #[doc = "## Safety"] @@ -47836,7 +45973,6 @@ pub unsafe fn vsudot_lane_s32( let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vusdot_s32(a, transmute(c), b) } - #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] #[doc = "## Safety"] @@ -47868,7 +46004,6 @@ pub unsafe fn vsudotq_lane_s32( let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vusdotq_s32(a, transmute(c), b) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] #[doc = "## Safety"] @@ -47894,7 +46029,6 @@ pub unsafe fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] #[doc = "## Safety"] @@ -47920,7 +46054,6 @@ pub unsafe fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] #[doc = "## Safety"] @@ -47946,7 +46079,6 @@ pub unsafe fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] #[doc = "## Safety"] @@ -47972,7 +46104,6 @@ pub unsafe fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] #[doc = "## Safety"] @@ -47998,7 +46129,6 @@ pub unsafe fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] #[doc = "## Safety"] @@ -48032,7 +46162,6 @@ pub unsafe fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { ); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] #[doc = "## Safety"] @@ -48058,7 +46187,6 @@ pub unsafe fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] #[doc = "## Safety"] @@ -48084,7 +46212,6 @@ pub unsafe fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] #[doc = "## Safety"] @@ -48110,7 +46237,6 @@ pub unsafe fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] #[doc = "## Safety"] @@ -48136,7 +46262,6 @@ pub unsafe fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] #[doc = "## Safety"] @@ -48170,7 +46295,6 @@ pub unsafe fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { ); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] #[doc = "## Safety"] @@ -48196,7 +46320,6 @@ pub unsafe fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] #[doc = "## Safety"] @@ -48222,7 +46345,6 @@ pub unsafe fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] #[doc = "## Safety"] @@ -48248,7 +46370,6 @@ pub unsafe fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] #[doc = "## Safety"] @@ -48274,7 +46395,6 @@ pub unsafe fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] #[doc = "## Safety"] @@ -48308,7 +46428,6 @@ pub unsafe fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { ); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] #[doc = "## Safety"] @@ -48334,7 +46453,6 @@ pub unsafe fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); transmute((a1, b1)) } - #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] #[doc = "## Safety"] @@ -48360,7 +46478,6 @@ pub unsafe fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); transmute((a1, b1)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] #[doc = "## Safety"] @@ -48386,7 +46503,6 @@ pub unsafe fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] #[doc = "## Safety"] @@ -48412,7 +46528,6 @@ pub unsafe fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] #[doc = "## Safety"] @@ -48438,7 +46553,6 @@ pub unsafe fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { let d: i16x4 = i16x4::new(0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] #[doc = "## Safety"] @@ -48464,7 +46578,6 @@ pub unsafe fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] #[doc = "## Safety"] @@ -48490,7 +46603,6 @@ pub unsafe fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { let d: i32x2 = i32x2::new(0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] #[doc = "## Safety"] @@ -48516,7 +46628,6 @@ pub unsafe fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { let d: i32x4 = i32x4::new(0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] #[doc = "## Safety"] @@ -48542,7 +46653,6 @@ pub unsafe fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] #[doc = "## Safety"] @@ -48568,7 +46678,6 @@ pub unsafe fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] #[doc = "## Safety"] @@ -48594,7 +46703,6 @@ pub unsafe fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { let d: i16x4 = i16x4::new(0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] #[doc = "## Safety"] @@ -48620,7 +46728,6 @@ pub unsafe fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] #[doc = "## Safety"] @@ -48646,7 +46753,6 @@ pub unsafe fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] #[doc = "## Safety"] @@ -48672,7 +46778,6 @@ pub unsafe fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] #[doc = "## Safety"] @@ -48698,7 +46803,6 @@ pub unsafe fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { let d: u16x4 = u16x4::new(0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] #[doc = "## Safety"] @@ -48724,7 +46828,6 @@ pub unsafe fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] #[doc = "## Safety"] @@ -48750,7 +46853,6 @@ pub unsafe fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { let d: u32x2 = u32x2::new(0, 0); simd_ne(c, transmute(d)) } - #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] #[doc = "## Safety"] @@ -48776,7 +46878,6 @@ pub unsafe fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { let d: u32x4 = u32x4::new(0, 0, 0, 0); simd_ne(c, transmute(d)) } - #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] #[doc = "## Safety"] @@ -48808,7 +46909,6 @@ pub unsafe fn vusdot_lane_s32( let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); vusdot_s32(a, b, transmute(c)) } - #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] #[doc = "## Safety"] @@ -48840,7 +46940,6 @@ pub unsafe fn vusdotq_lane_s32( let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); vusdotq_s32(a, b, transmute(c)) } - #[doc = "Dot product vector form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] #[doc = "## Safety"] @@ -48872,7 +46971,6 @@ pub unsafe fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { } _vusdot_s32(a, b.as_signed(), c) } - #[doc = "Dot product vector form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] #[doc = "## Safety"] @@ -48904,7 +47002,6 @@ pub unsafe fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_ } _vusdotq_s32(a, b.as_signed(), c) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] #[doc = "## Safety"] @@ -48930,7 +47027,6 @@ pub unsafe fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] #[doc = "## Safety"] @@ -48956,7 +47052,6 @@ pub unsafe fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] #[doc = "## Safety"] @@ -48982,7 +47077,6 @@ pub unsafe fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] #[doc = "## Safety"] @@ -49008,7 +47102,6 @@ pub unsafe fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] #[doc = "## Safety"] @@ -49034,7 +47127,6 @@ pub unsafe fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] #[doc = "## Safety"] @@ -49068,7 +47160,6 @@ pub unsafe fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { ); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] #[doc = "## Safety"] @@ -49094,7 +47185,6 @@ pub unsafe fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] #[doc = "## Safety"] @@ -49120,7 +47210,6 @@ pub unsafe fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] #[doc = "## Safety"] @@ -49146,7 +47235,6 @@ pub unsafe fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] #[doc = "## Safety"] @@ -49172,7 +47260,6 @@ pub unsafe fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] #[doc = "## Safety"] @@ -49206,7 +47293,6 @@ pub unsafe fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { ); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] #[doc = "## Safety"] @@ -49232,7 +47318,6 @@ pub unsafe fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] #[doc = "## Safety"] @@ -49258,7 +47343,6 @@ pub unsafe fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] #[doc = "## Safety"] @@ -49284,7 +47368,6 @@ pub unsafe fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] #[doc = "## Safety"] @@ -49310,7 +47393,6 @@ pub unsafe fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] #[doc = "## Safety"] @@ -49344,7 +47426,6 @@ pub unsafe fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { ); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] #[doc = "## Safety"] @@ -49370,7 +47451,6 @@ pub unsafe fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); transmute((a0, b0)) } - #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] #[doc = "## Safety"] @@ -49396,7 +47476,6 @@ pub unsafe fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] #[doc = "## Safety"] @@ -49422,7 +47501,6 @@ pub unsafe fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] #[doc = "## Safety"] @@ -49448,7 +47526,6 @@ pub unsafe fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] #[doc = "## Safety"] @@ -49474,7 +47551,6 @@ pub unsafe fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] #[doc = "## Safety"] @@ -49500,7 +47576,6 @@ pub unsafe fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] #[doc = "## Safety"] @@ -49526,7 +47601,6 @@ pub unsafe fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] #[doc = "## Safety"] @@ -49552,7 +47626,6 @@ pub unsafe fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] #[doc = "## Safety"] @@ -49578,7 +47651,6 @@ pub unsafe fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] #[doc = "## Safety"] @@ -49604,7 +47676,6 @@ pub unsafe fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] #[doc = "## Safety"] @@ -49630,7 +47701,6 @@ pub unsafe fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] #[doc = "## Safety"] @@ -49656,7 +47726,6 @@ pub unsafe fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] #[doc = "## Safety"] @@ -49690,7 +47759,6 @@ pub unsafe fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { ); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] #[doc = "## Safety"] @@ -49716,7 +47784,6 @@ pub unsafe fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] #[doc = "## Safety"] @@ -49742,7 +47809,6 @@ pub unsafe fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] #[doc = "## Safety"] @@ -49776,7 +47842,6 @@ pub unsafe fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { ); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] #[doc = "## Safety"] @@ -49802,7 +47867,6 @@ pub unsafe fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] #[doc = "## Safety"] @@ -49828,7 +47892,6 @@ pub unsafe fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] #[doc = "## Safety"] @@ -49862,7 +47925,6 @@ pub unsafe fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { ); transmute((a0, b0)) } - #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] #[doc = "## Safety"] diff --git a/crates/intrinsic-test/Cargo.toml b/crates/intrinsic-test/Cargo.toml index 06af3c6b66..e5c6186436 100644 --- a/crates/intrinsic-test/Cargo.toml +++ b/crates/intrinsic-test/Cargo.toml @@ -19,4 +19,4 @@ log = "0.4.11" pretty_env_logger = "0.5.0" rayon = "1.5.0" diff = "0.1.12" -itertools = "0.11.0" +itertools = "0.14.0" diff --git a/crates/stdarch-gen-arm/Cargo.toml b/crates/stdarch-gen-arm/Cargo.toml index 3cc4982549..4112018666 100644 --- a/crates/stdarch-gen-arm/Cargo.toml +++ b/crates/stdarch-gen-arm/Cargo.toml @@ -12,7 +12,7 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -itertools = "0.10" +itertools = "0.14.0" lazy_static = "1.4.0" proc-macro2 = "1.0" quote = "1.0" diff --git a/crates/stdarch-gen-arm/src/input.rs b/crates/stdarch-gen-arm/src/input.rs index bb2414adec..ca104fa9c0 100644 --- a/crates/stdarch-gen-arm/src/input.rs +++ b/crates/stdarch-gen-arm/src/input.rs @@ -253,6 +253,7 @@ impl IntrinsicInput { .into_iter() .map(|v| v.into_iter()) .multi_cartesian_product() + .filter(|set| !set.is_empty()) .map(|set| InputSet(set.into_iter().flatten().collect_vec())); Ok(it) } diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs index 4a973691b1..c3f2ad7b91 100644 --- a/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/crates/stdarch-gen-arm/src/intrinsic.rs @@ -1,5 +1,5 @@ use itertools::Itertools; -use proc_macro2::{Punct, Spacing, TokenStream}; +use proc_macro2::{Delimiter, Group, Punct, Spacing, TokenStream}; use quote::{format_ident, quote, ToTokens, TokenStreamExt}; use serde::{Deserialize, Serialize}; use serde_with::{DeserializeFromStr, SerializeDisplay}; @@ -417,35 +417,32 @@ impl ToTokens for LLVMLinkAttribute { fn to_tokens(&self, tokens: &mut TokenStream) { let LLVMLinkAttribute { arch, link } = self; let link = link.to_string(); - let archs: Vec<&str> = arch.split(',').collect(); - let arch_len = archs.len(); - if arch_len == 1 { - tokens.append_all(quote! { - #[cfg_attr(target_arch = #arch, link_name = #link)] - }) - } else { - tokens.append(Punct::new('#', Spacing::Alone)); - tokens.append(Punct::new('[', Spacing::Alone)); - tokens.append_all(quote! { cfg_attr }); - tokens.append(Punct::new('(', Spacing::Alone)); - tokens.append_all(quote! { any }); - tokens.append(Punct::new('(', Spacing::Alone)); - let mut i = 0; - while i < arch_len { - let arch = archs[i].to_string(); - tokens.append_all(quote! { target_arch = #arch }); - if i + 1 != arch_len { - tokens.append(Punct::new(',', Spacing::Alone)); - } - i += 1; + // For example: + // + // #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i16")] + // + // #[cfg_attr( + // any(target_arch = "aarch64", target_arch = "arm64ec"), + // link_name = "llvm.aarch64.neon.suqadd.i32" + // )] + + let mut cfg_attr_cond = TokenStream::new(); + let mut single_arch = true; + for arch in arch.split(',') { + if !cfg_attr_cond.is_empty() { + single_arch = false; + cfg_attr_cond.append(Punct::new(',', Spacing::Alone)); } - tokens.append(Punct::new(')', Spacing::Alone)); - tokens.append(Punct::new(',', Spacing::Alone)); - tokens.append_all(quote! { link_name = #link }); - tokens.append(Punct::new(')', Spacing::Alone)); - tokens.append(Punct::new(']', Spacing::Alone)); + cfg_attr_cond.append_all(quote! { target_arch = #arch }); + } + assert!(!cfg_attr_cond.is_empty()); + if !single_arch { + cfg_attr_cond = quote! { any( #cfg_attr_cond ) }; } + tokens.append_all(quote! { + #[cfg_attr(#cfg_attr_cond, link_name = #link)] + }) } } @@ -1560,10 +1557,10 @@ impl ToTokens for Intrinsic { /* Target feature will get added here */ let attr_expressions = &mut attr.iter().peekable(); while let Some(ex) = attr_expressions.next() { + let mut inner = TokenStream::new(); + ex.to_tokens(&mut inner); tokens.append(Punct::new('#', Spacing::Alone)); - tokens.append(Punct::new('[', Spacing::Alone)); - ex.to_tokens(tokens); - tokens.append(Punct::new(']', Spacing::Alone)); + tokens.append(Group::new(Delimiter::Bracket, inner)); } } else { tokens.append_all(quote! { @@ -1586,30 +1583,34 @@ impl ToTokens for Intrinsic { tokens.append_all(quote! { unsafe }); } tokens.append_all(quote! { #signature }); - tokens.append(Punct::new('{', Spacing::Alone)); - - let mut body_unsafe = false; - let mut expressions = self.compose.iter().peekable(); - while let Some(ex) = expressions.next() { - if !body_unsafe && safety.is_safe() && ex.requires_unsafe_wrapper(&fn_name) { - body_unsafe = true; - tokens.append_all(quote! { unsafe }); - tokens.append(Punct::new('{', Spacing::Alone)); + + // If the intrinsic function is explicitly unsafe, we populate `body_default_safety` with + // the implementation. No explicit unsafe blocks are required. + // + // If the intrinsic is safe, we fill `body_default_safety` until we encounter an expression + // that requires an unsafe wrapper, then switch to `body_unsafe`. Since the unsafe + // operation (e.g. memory access) is typically the last step, this tends to minimises the + // amount of unsafe code required. + let mut body_default_safety = TokenStream::new(); + let mut body_unsafe = TokenStream::new(); + let mut body_current = &mut body_default_safety; + for (pos, ex) in self.compose.iter().with_position() { + if safety.is_safe() && ex.requires_unsafe_wrapper(&fn_name) { + body_current = &mut body_unsafe; } - // If it's not the last and not a LLVM link, add a trailing semicolon - if expressions.peek().is_some() && !matches!(ex, Expression::LLVMLink(_)) { - tokens.append_all(quote! { #ex; }) - } else { - ex.to_tokens(tokens) + ex.to_tokens(body_current); + let is_last = matches!(pos, itertools::Position::Last | itertools::Position::Only); + let is_llvm_link = matches!(ex, Expression::LLVMLink(_)); + if !is_last && !is_llvm_link { + body_current.append(Punct::new(';', Spacing::Alone)); } } - if body_unsafe { - tokens.append(Punct::new('}', Spacing::Alone)); + let mut body = body_default_safety; + if !body_unsafe.is_empty() { + body.append_all(quote! { unsafe { #body_unsafe } }); } - tokens.append(Punct::new('}', Spacing::Alone)); - tokens.append(Punct::new('\n', Spacing::Alone)); - tokens.append(Punct::new('\n', Spacing::Alone)); + tokens.append(Group::new(Delimiter::Brace, body)); } } diff --git a/crates/stdarch-gen-arm/src/load_store_tests.rs b/crates/stdarch-gen-arm/src/load_store_tests.rs index d697a8d22d..83d0ac975c 100644 --- a/crates/stdarch-gen-arm/src/load_store_tests.rs +++ b/crates/stdarch-gen-arm/src/load_store_tests.rs @@ -91,11 +91,11 @@ pub fn generate_load_store_tests( format!( "// This code is automatically generated. DO NOT MODIFY. // -// Instead, modify `crates/stdarch-gen2/spec/sve` and run the following command to re-generate this -// file: +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: // // ``` -// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec // ``` {}", quote! { #preamble #(#tests)* #manual_tests } diff --git a/crates/stdarch-gen-arm/src/main.rs b/crates/stdarch-gen-arm/src/main.rs index 22bf6724b0..c78e5dc4e4 100644 --- a/crates/stdarch-gen-arm/src/main.rs +++ b/crates/stdarch-gen-arm/src/main.rs @@ -104,7 +104,10 @@ fn parse_args() -> Vec<(PathBuf, Option)> { let mut args_it = std::env::args().skip(1); assert!( 1 <= args_it.len() && args_it.len() <= 2, - "Usage: cargo run -p stdarch-gen2 -- INPUT_DIR [OUTPUT_DIR]" + "Usage: cargo run -p stdarch-gen-arm -- INPUT_DIR [OUTPUT_DIR]\n\ + where:\n\ + - INPUT_DIR contains a tree like: INPUT_DIR//.spec.yml\n\ + - OUTPUT_DIR is a directory like: crates/core_arch/src/" ); let in_path = Path::new(args_it.next().unwrap().as_str()).to_path_buf(); @@ -124,7 +127,7 @@ fn parse_args() -> Vec<(PathBuf, Option)> { std::env::current_exe() .map(|mut f| { f.pop(); - f.push("../../crates/core_arch/src/aarch64/"); + f.push("../../crates/core_arch/src/"); f.exists().then_some(f) }) .ok() @@ -147,10 +150,10 @@ fn generate_file( out, r#"// This code is automatically generated. DO NOT MODIFY. // -// Instead, modify `crates/stdarch-gen2/spec/` and run the following command to re-generate this file: +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: // // ``` -// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec // ``` #![allow(improper_ctypes)] @@ -183,17 +186,19 @@ pub fn format_code( output.write_all(proc.wait_with_output()?.stdout.as_slice()) } -/// Derive an output file name from an input file and an output directory. +/// Derive an output file path from an input file path and an output directory. /// -/// The name is formed by: +/// `in_filepath` is expected to have a structure like: +/// ...//.spec.yml /// -/// - ... taking in_filepath.file_name() (dropping all directory components), -/// - ... dropping a .yml or .yaml extension (if present), -/// - ... then dropping a .spec extension (if present). +/// The resulting output path will have a structure like: +/// ///generated.rs /// /// Panics if the resulting name is empty, or if file_name() is not UTF-8. fn make_output_filepath(in_filepath: &Path, out_dirpath: &Path) -> PathBuf { - make_filepath(in_filepath, out_dirpath, |name: &str| format!("{name}.rs")) + make_filepath(in_filepath, out_dirpath, |_name: &str| { + format!("generated.rs") + }) } fn make_tests_filepath(in_filepath: &Path, out_dirpath: &Path) -> PathBuf { @@ -207,22 +212,27 @@ fn make_filepath String>( out_dirpath: &Path, name_formatter: F, ) -> PathBuf { - let mut parts = in_filepath.iter(); - let name = parts - .next_back() - .and_then(|f| f.to_str()) - .expect("Inputs must have valid, UTF-8 file_name()"); - let dir = parts.next_back().unwrap(); + let mut parts = in_filepath.components().rev().map(|f| { + f.as_os_str() + .to_str() + .expect("Inputs must have valid, UTF-8 file_name()") + }); + let yml = parts.next().expect("Not enough input path elements."); + let feature = parts.next().expect("Not enough input path elements."); - let name = name - .trim_end_matches(".yml") - .trim_end_matches(".yaml") - .trim_end_matches(".spec"); - assert!(!name.is_empty()); + let arch = yml + .strip_suffix(".yml") + .expect("Expected .yml file input.") + .strip_suffix(".spec") + .expect("Expected .spec.yml file input."); + if arch.is_empty() { + panic!("Extended ARCH.spec.yml file input."); + } let mut output = out_dirpath.to_path_buf(); - output.push(dir); - output.push(name_formatter(name)); + output.push(arch); + output.push(feature); + output.push(name_formatter(arch)); output } @@ -233,47 +243,68 @@ mod tests { #[test] fn infer_output_file() { macro_rules! t { - ($src:expr, $outdir:expr, $dst:expr) => { + ($src:expr, $outdir:expr, $dst:expr, $ldst:expr) => { let src: PathBuf = $src.iter().collect(); let outdir: PathBuf = $outdir.iter().collect(); let dst: PathBuf = $dst.iter().collect(); + let ldst: PathBuf = $ldst.iter().collect(); assert_eq!(make_output_filepath(&src, &outdir), dst); + assert_eq!(make_tests_filepath(&src, &outdir), ldst); }; } // Documented usage. - t!(["x", "NAME.spec.yml"], [""], ["x", "NAME.rs"]); t!( - ["x", "NAME.spec.yml"], - ["a", "b"], - ["a", "b", "x", "NAME.rs"] + ["FEAT", "ARCH.spec.yml"], + [""], + ["ARCH", "FEAT", "generated.rs"], + ["ARCH", "FEAT", "ld_st_tests_ARCH.rs"] ); t!( - ["x", "y", "NAME.spec.yml"], + ["x", "y", "FEAT", "ARCH.spec.yml"], ["out"], - ["out", "y", "NAME.rs"] + ["out", "ARCH", "FEAT", "generated.rs"], + ["out", "ARCH", "FEAT", "ld_st_tests_ARCH.rs"] ); - t!(["x", "NAME.spec.yaml"], ["out"], ["out", "x", "NAME.rs"]); - t!(["x", "NAME.spec"], ["out"], ["out", "x", "NAME.rs"]); - t!(["x", "NAME.yml"], ["out"], ["out", "x", "NAME.rs"]); - t!(["x", "NAME.yaml"], ["out"], ["out", "x", "NAME.rs"]); - // Unrecognised extensions get treated as part of the stem. t!( - ["x", "NAME.spac.yml"], - ["out"], - ["out", "x", "NAME.spac.rs"] + ["p", "q", "FEAT", "ARCH.spec.yml"], + ["a", "b"], + ["a", "b", "ARCH", "FEAT", "generated.rs"], + ["a", "b", "ARCH", "FEAT", "ld_st_tests_ARCH.rs"] ); - t!(["x", "NAME.txt"], ["out"], ["out", "x", "NAME.txt.rs"]); - // Always take the top-level directory from the input path + // Extra extensions get treated as part of the stem. t!( - ["x", "y", "z", "NAME.spec.yml"], + ["FEAT", "ARCH.variant.spec.yml"], ["out"], - ["out", "z", "NAME.rs"] + ["out", "ARCH.variant", "FEAT", "generated.rs"], + ["out", "ARCH.variant", "FEAT", "ld_st_tests_ARCH.variant.rs"] ); } #[test] #[should_panic] fn infer_output_file_no_stem() { - make_output_filepath(Path::new(".spec.yml"), Path::new("")); + let src = PathBuf::from("FEAT/.spec.yml"); + make_output_filepath(&src, Path::new("")); + } + + #[test] + #[should_panic] + fn infer_output_file_no_feat() { + let src = PathBuf::from("ARCH.spec.yml"); + make_output_filepath(&src, Path::new("")); + } + + #[test] + #[should_panic] + fn infer_output_file_ldst_no_stem() { + let src = PathBuf::from("FEAT/.spec.yml"); + make_tests_filepath(&src, Path::new("")); + } + + #[test] + #[should_panic] + fn infer_output_file_ldst_no_feat() { + let src = PathBuf::from("ARCH.spec.yml"); + make_tests_filepath(&src, Path::new("")); } }