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alpha.def
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/* This doesn't look like -*- C -*-, but it is! */
/* alpha.def - Alpha ISA machine definition */
/* SimpleScalar(TM) Tool Suite
* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
* All Rights Reserved.
*
* THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
* YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
*
* No portion of this work may be used by any commercial entity, or for any
* commercial purpose, without the prior, written permission of SimpleScalar,
* LLC ([email protected]). Nonprofit and noncommercial use is permitted
* as described below.
*
* 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
* or implied. The user of the program accepts full responsibility for the
* application of the program and the use of any results.
*
* 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
* downloaded, compiled, executed, copied, and modified solely for nonprofit,
* educational, noncommercial research, and noncommercial scholarship
* purposes provided that this notice in its entirety accompanies all copies.
* Copies of the modified software can be delivered to persons who use it
* solely for nonprofit, educational, noncommercial research, and
* noncommercial scholarship purposes provided that this notice in its
* entirety accompanies all copies.
*
* 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
* PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC ([email protected]).
*
* 4. No nonprofit user may place any restrictions on the use of this software,
* including as modified by the user, by any other authorized user.
*
* 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
* in compiled or executable form as set forth in Section 2, provided that
* either: (A) it is accompanied by the corresponding machine-readable source
* code, or (B) it is accompanied by a written offer, with no time limit, to
* give anyone a machine-readable copy of the corresponding source code in
* return for reimbursement of the cost of distribution. This written offer
* must permit verbatim duplication by anyone, or (C) it is distributed by
* someone who received only the executable form, and is accompanied by a
* copy of the written offer of source code.
*
* 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
* currently maintained by SimpleScalar LLC ([email protected]). US Mail:
* 2395 Timbercrest Court, Ann Arbor, MI 48105.
*
* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
*/
/* FIXME: these comments are out-of-date */
/* This file defines all aspects of the SimpleScalar instruction set
* architecture. Each instruction set in the architecture has a DEFINST()
* macro call included below. The contents of a instruction definition are
* as follows:
*
* DEFINST(<enum>, <opcode>,
* <opname>, <operands>,
* <fu_req>, <iflags>,
* <output deps...>, <input deps...>,
* <expr>)
*
* Where:
*
* <enum> - is an enumerator that is returned when an instruction is
* decoded by SS_OP_ENUM()
* <opcode> - is the opcode of this instruction
* <opname> - name of this instruction as a string, used by disassembler
* <operands> - specified the instruction operand fields and their printed
* order for disassembly, used by disassembler, the recognized
* operand field are (the instruction format is detailed in
* the header file ss.h):
* J - target field
* j - PC relative target (offset + PC)
* s - S register field
* b - S register field (base register)
* t - T register field
* d - D register field
* S - S register field (FP register)
* T - T register field (FP register)
* D - D register field (FP register)
* o - load address offset (offset)
* i - signed immediate field value
* u - unsigned immediate field value
* U - upper immediate field value
* H - shift amount immediate field value
* B - break code
*
* <fu_req> - functional unit requirements for this instruction
* <iflags> - instruction flags, accessible via the SS_OP_FLAGS()
* macro, flags are defined with F_* prefix in ss.h
* <output deps...>
* - a list of up to two output dependency designators, the
* following designators are recognized (place an DNA in any
* unused fields:
* DGPR(N) - general purpose register N
* DGPR_D(N) - double word general purpose register N
* DCGPR(N) - general purpose register conditional on
* pre/post- increment/decrement mode
* DFPR_L(N) - floating-point register N, as word
* DFPR_F(N) - floating-point reg N, as single-prec float
* DFPR_D(N) - floating-point reg N, as double-prec double
* DHI - HI result register
* DLO - LO result register
* DFCC - floating point condition codes
* DCPC - current PC
* DNPC - next PC
* DNA - no dependence
*
* <input deps...>
* - a list of up to three input dependency designators, the
* designators are defined above (place an DNA in any unused
* fields.
*
* <expr> - a C expression that implements the instruction being
* defined, the expression must modify all architected state
* affected by the instruction's execution, by default, the
* next PC (NPC) value defaults to the current PC (CPC) plus
* SS_INST_SIZE, as a result, only taken branches need to set
* NPC
*
* The following predefined macros are available for use in
* DEFINST() instruction expressions to access the value of
* instruction operand/opcode field values:
*
* RS - RS register field value
* RT - RT register field value
* RD - RD register field value
* FS - RS register field value
* FT - RT register field value
* FD - RD register field value
* BS - RS register field value
* TARG - jump target field value
* OFS - signed offset field value
* IMM - signed offset field value
* UIMM - unsigned offset field value
* SHAMT - shift amount field value
* BCODE - break code field value
*
* To facilitate the construction of performance simulators
* (which may want to specialize their architected state
* storage format), all architected register and memory state
* is accessed through the following macros:
*
* GPR(N) - read general purpose register N
* SET_GPR(N,E) - write general purpose register N with E
* GPR_D(N) - read double word general purpose reg N
* SET_GPR_D(N,E) - write double word gen purpose reg N w/ E
* FPR_L(N) - read floating-point register N, as word
* SET_FPR_L(N,E) - floating-point reg N, as word, with E
* FPR_F(N) - read FP reg N, as single-prec float
* SET_FPR_F(N,E) - write FP reg N, as single-prec float w/ E
* FPR_D(N) - read FP reg N, as double-prec double
* SET_FPR_D(N,E) - write FP reg N, as double-prec double w/E
* HI - read HI result register
* SET_HI(E) - write HI result register with E
* LO - read LO result register
* SET_LO(E) - write LO result register with E
* FCC - read floating point condition codes
* SET_FCC(E) - write floating point condition codes w/ E
* CPC - read current PC register
* NPC - read next PC register
* SET_NPC(E) - write next PC register with E
* TPC - read target PC register
* SET_TPC(E) - write target PC register with E
*
* READ_SIGNED_BYTE(A) - read signed byte from address A
* READ_UNSIGNED_BYTE(A) - read unsigned byte from address A
* READ_SIGNED_HALF(A) - read signed half from address A
* READ_UNSIGNED_HALF(A) - read unsigned half from address A
* READ_WORD(A) - read word from address A
* WRITE_BYTE(E,A) - write byte value E to address A
* WRITE_HALF(E,A) - write half value E to address A
* WRITE_WORD(E,A) - write word value E to address A
*
* Finally, the following helper functions are available to
* assist in the construction of instruction expressions:
*
* INC_DEC(E,N,S) - execute E and update N as per pre/post-
* incr/decr addressing sementics for an
* access of S bytes
* OVER(X,Y) - check for overflow for X+Y, both signed
* UNDER(X,Y) - check for umderflow for X-Y, both signed
* DIV0(N) - check for divide by zero, N is denom
* INTALIGN(N) - check double word int reg N alignment
* FPALIGN(N) - check double word FP reg N alignment
* TALIGN(T) - check jump target T alignment
*/
#if 0
/* TOP LEVEL decode table */
DEFLINK(TOPLEV, 0x00, "toplev", 26, 0x3f)
CONNECT(TOPLEV)
#endif
DEFLINK(CALL_PAL, 0x00, "call_pal", 0, 0xff)
#define LDA_IMPL \
{ \
SET_GPR(RA, GPR(RB) + SEXT(OFS)); \
}
DEFINST(LDA, 0x08,
"lda", "a,o(b)",
IntALU, F_ICOMP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
#define LDAH_IMPL \
{ \
SET_GPR(RA, GPR(RB) + SEXT32(65536 * OFS)); \
}
DEFINST(LDAH, 0x09,
"ldah", "a,o(b)",
IntALU, F_ICOMP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
/* EV56 BWX extension... */
#define LDBU_IMPL \
{ \
byte_t _result; \
enum md_fault_type _fault; \
\
_result = READ_BYTE(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, (qword_t)_result); \
}
DEFINST(LDBU, 0x0a,
"ldbu", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
#define LDQ_U_IMPL \
{ \
qword_t _result; \
enum md_fault_type _fault; \
\
_result = READ_QWORD((GPR(RB) + SEXT(OFS)) & ~7, _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, _result); \
}
DEFINST(LDQ_U, 0x0b,
"ldq_u", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
/* EV56 BWX extension... */
#define LDWU_IMPL \
{ \
half_t _result; \
enum md_fault_type _fault; \
\
_result = READ_HALF(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, (qword_t)_result); \
}
DEFINST(LDWU, 0x0c,
"ldwu", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
/* EV56 BWX extension... */
#define STW_IMPL \
{ \
enum md_fault_type _fault; \
\
WRITE_HALF((half_t)GPR(RA), GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STW, 0x0d,
"stw", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
/* EV56 BWX extension... */
#define STB_IMPL \
{ \
enum md_fault_type _fault; \
\
WRITE_BYTE((byte_t)GPR(RA), GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STB, 0x0e,
"stb", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
#define STQ_U_IMPL \
{ \
enum md_fault_type _fault; \
\
WRITE_QWORD(GPR(RA), (GPR(RB) + SEXT(OFS)) & ~7, _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STQ_U, 0x0f,
"stq_u", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
DEFLINK(INTA, 0x10, "inta", 5, 0x7f)
DEFLINK(INTL, 0x11, "intl", 5, 0x7f)
DEFLINK(INTS, 0x12, "ints", 5, 0x7f)
/* changed from 0x7f to 0x3f to allow MUL{Q,L}/V */
DEFLINK(INTM, 0x13, "intm", 5, 0x3f)
/* added 02/27/99, plakal@cecil, from Alpha Arch Handbook (Rev.4, EV6) */
/* FIX extensions */
DEFLINK(ITFP, 0x14, "itfp", 5, 0x3f)
#define FLTV_IMPL \
{ \
/* FIXME: unimplemented */ \
DECLARE_FAULT(md_fault_unimpl); \
}
DEFINST(FLTV, 0x15,
"fltv (unimpl)", "",
NA, NA,
DNA, DNA, DNA, DNA, DNA)
DEFLINK(FLTI, 0x16, "flti", 5, 0x3f)
DEFLINK(FLTL, 0x17, "fltl", 5, /* FIXME: check this... */0x7f)
/* changed the shift & mask to incorporate new instructions in the group */
DEFLINK(MISC, 0x18, "misc", 8, 0xff)
DEFLINK(JMPJSR, 0x1a, "jmpjsr", 14, 0x03)
/* changed from EXTS to FPTI to include more extensions (FIX,CIX,MVI) */
DEFLINK(FPTI, 0x1c, "fpti", 5, 0x7f)
#define LDF_IMPL \
{ \
/* FIXME: unimplemented */ \
DECLARE_FAULT(md_fault_unimpl); \
}
DEFINST(LDF, 0x20,
"ldf (unimpl)", "",
NA, NA,
DNA, DNA, DNA, DNA, DNA)
#define LDG_IMPL \
{ \
/* FIXME: unimplemented */ \
DECLARE_FAULT(md_fault_unimpl); \
}
DEFINST(LDG, 0x21,
"ldg (unimpl)", "",
NA, NA,
DNA, DNA, DNA, DNA, DNA)
#define LDS_IMPL \
{ \
sqword_t _longhold, _e1, _e2; \
enum md_fault_type _fault; \
\
_longhold = READ_WORD(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
_e1 = _longhold & 0x40000000; \
_e2 = (_longhold >> 23) & ULL(0x7f); \
if (_e1) \
{ \
if (_e2 == ULL(0x3f800000)) \
_e2 = ULL(0x7ff); \
else \
_e2 |= ULL(0x400); \
} \
else \
{ \
if (_e2 == 0) \
_e2 = 0; \
else \
_e2 |= ULL(0x380); \
} \
SET_FPR_Q(RA, ((_longhold & ULL(0x80000000)) << 32 \
| _e2 << 52 | (_longhold & ULL(0x7fffff)) << 29)); \
}
DEFINST(LDS, 0x22,
"lds", "A,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DFPR(RA), DNA, DNA, DGPR(RB), DNA)
#define LDT_IMPL \
{ \
qword_t _result; \
enum md_fault_type _fault; \
\
_result = READ_QWORD(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_FPR_Q(RA, _result); \
}
DEFINST(LDT, 0x23,
"ldt", "A,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DFPR(RA), DNA, DNA, DGPR(RB), DNA)
#define STF_IMPL \
{ \
/* FIXME: unimplemented */ \
DECLARE_FAULT(md_fault_unimpl); \
}
DEFINST(STF, 0x24,
"stf (unimpl)", "",
NA, NA,
DNA, DNA, DNA, DNA, DNA)
#define STG_IMPL \
{ \
/* FIXME: unimplemented */ \
DECLARE_FAULT(md_fault_unimpl); \
}
DEFINST(STG, 0x25,
"stg (unimpl)", "",
NA, NA,
DNA, DNA, DNA, DNA, DNA)
#define STS_IMPL \
{ \
sqword_t _longhold; \
sword_t _inthold; \
enum md_fault_type _fault; \
\
_longhold = FPR_Q(RA); \
_inthold = (((_longhold >> 32) & ULL(0xc0000000)) \
| ((_longhold >> 29) & ULL(0x3fffffff))); \
WRITE_WORD(_inthold, GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STS, 0x26,
"sts", "A,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DFPR(RA), DGPR(RB), DNA)
#define STT_IMPL \
{ \
enum md_fault_type _fault; \
\
WRITE_QWORD(FPR_Q(RA), GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STT, 0x27,
"stt", "A,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DFPR(RA), DGPR(RB), DNA)
#define LDL_IMPL \
{ \
word_t _result; \
enum md_fault_type _fault; \
\
_result = READ_WORD(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, (sqword_t)((sword_t)_result)); \
}
DEFINST(LDL, 0x28,
"ldl", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
#define LDQ_IMPL \
{ \
qword_t _result; \
enum md_fault_type _fault; \
\
_result = READ_QWORD(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, _result); \
}
DEFINST(LDQ, 0x29,
"ldq", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
/* FIXME: not fully implemented... */
#define LDL_L_IMPL \
{ \
word_t _result; \
enum md_fault_type _fault; \
\
_result = READ_WORD(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, (sqword_t)((sword_t)_result)); \
}
DEFINST(LDL_L, 0x2a,
"ldl_l (unimpl)", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
/* FIXME: not fully implemented... */
#define LDQ_L_IMPL \
{ \
qword_t _result; \
enum md_fault_type _fault; \
\
_result = READ_QWORD(GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
\
SET_GPR(RA, _result); \
}
DEFINST(LDQ_L, 0x2b,
"ldq_l (unimpl)", "a,o(b)",
RdPort, F_MEM|F_LOAD|F_DISP,
DGPR(RA), DNA, DNA, DGPR(RB), DNA)
#define STL_IMPL \
{ \
word_t _src; \
enum md_fault_type _fault; \
\
_src = (word_t)(GPR(RA) & ULL(0xffffffff)); \
WRITE_WORD(_src, GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STL, 0x2c,
"stl", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
#define STQ_IMPL \
{ \
enum md_fault_type _fault; \
\
WRITE_QWORD(GPR(RA), GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STQ, 0x2d,
"stq", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
/* FIXME: not fully implemented... */
#define STL_C_IMPL \
{ \
word_t _src; \
enum md_fault_type _fault; \
\
_src = (word_t)(GPR(RA) & ULL(0xffffffff)); \
WRITE_WORD(_src, GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STL_C, 0x2e,
"stl_c (unimpl)", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
/* FIXME: not fully implemented... */
#define STQ_C_IMPL \
{ \
enum md_fault_type _fault; \
\
WRITE_QWORD(GPR(RA), GPR(RB) + SEXT(OFS), _fault); \
if (_fault != md_fault_none) \
DECLARE_FAULT(_fault); \
}
DEFINST(STQ_C, 0x2f,
"stq_c (unimpl)", "a,o(b)",
WrPort, F_MEM|F_STORE|F_DISP,
DNA, DNA, DGPR(RA), DGPR(RB), DNA)
#define BR_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
SET_GPR(RA, CPC + 4); \
}
DEFINST(BR, 0x30,
"br", "a,J",
IntALU, F_CTRL|F_UNCOND|F_DIRJMP,
DGPR(RA), DNA, DNA, DNA, DNA)
#define FBEQ_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (FPR(RA) == 0.0) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(FBEQ, 0x31,
"fbeq", "A,j",
FloatADD, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DFPR(RA), DNA, DNA)
#define FBLT_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (FPR(RA) < 0.0) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(FBLT, 0x32,
"fblt", "A,j",
FloatADD, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DFPR(RA), DNA, DNA)
#define FBLE_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (FPR(RA) <= 0.0) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(FBLE, 0x33,
"fble", "A,j",
FloatADD, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DFPR(RA), DNA, DNA)
/* NOTE: this is semantically equivalent to BR, the different opcode tips
off the predictor to use the return address stack... */
#define BSR_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
SET_GPR(RA, CPC + 4); \
}
DEFINST(BSR, 0x34,
"bsr", "a,J",
IntALU, F_CTRL|F_UNCOND|F_DIRJMP,
DGPR(RA), DNA, DNA, DNA, DNA)
#define FBNE_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (FPR(RA) != 0.0) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(FBNE, 0x35,
"fbne", "A,j",
FloatADD, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DFPR(RA), DNA, DNA)
#define FBGE_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (FPR(RA) >= 0.0) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(FBGE, 0x36,
"fbge", "A,j",
FloatADD, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DFPR(RA), DNA, DNA)
#define FBGT_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (FPR(RA) > 0.0) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(FBGT, 0x37,
"fbgt", "A,j",
FloatADD, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DFPR(RA), DNA, DNA)
#define BLBC_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (!(GPR(RA) & 1)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BLBC, 0x38,
"blbc", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BEQ_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (GPR(RA) == ULL(0)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BEQ, 0x39,
"beq", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BLT_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if ((sqword_t)GPR(RA) < LL(0)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BLT, 0x3a,
"blt", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BLE_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if ((sqword_t)GPR(RA) <= LL(0)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BLE, 0x3b,
"ble", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BLBS_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (GPR(RA) & 1) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BLBS, 0x3c,
"blbs", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BNE_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if (GPR(RA) != ULL(0)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BNE, 0x3d,
"bne", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BGE_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if ((sqword_t)GPR(RA) >= LL(0)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BGE, 0x3e,
"bge", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
#define BGT_IMPL \
{ \
SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \
if ((sqword_t)GPR(RA) > LL(0)) \
SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \
}
DEFINST(BGT, 0x3f,
"bgt", "a,j",
IntALU, F_CTRL|F_COND|F_DIRJMP,
DNA, DNA, DGPR(RA), DNA, DNA)
CONNECT(CALL_PAL)
#define PAL_CALLSYS_IMPL \
{ \
SYSCALL(inst); \
}
DEFINST(PAL_CALLSYS, 0x83,
"call_pal callsys", "",
NA, F_TRAP,
DNA, DNA, DNA, DNA, DNA)
#define PAL_RDUNIQ_IMPL \
{ \
SET_GPR(/* v0 */0, UNIQ); \
}
DEFINST(PAL_RDUNIQ, 0x9e,
"call_pal rduniq", "",
NA, F_TRAP,
DGPR(/* v0 */0), DNA, DUNIQ, DNA, DNA)
#define PAL_WRUNIQ_IMPL \
{ \
SET_UNIQ(GPR(/* a0 */16)); \
}
DEFINST(PAL_WRUNIQ, 0x9f,
"call_pal wruniq", "",
NA, F_TRAP,
DUNIQ, DNA, DGPR(/* a0 */16), DNA, DNA)
CONNECT(INTA)
DEFLINK(ADDL_LINK, 0x00, "addl_link", 12, 1)
DEFLINK(S4ADDL_LINK, 0x02, "s4addl_link", 12, 1)
DEFLINK(SUBL_LINK, 0x09, "subl_link", 12, 1)
DEFLINK(S4SUBL_LINK, 0x0b, "s4subl_link", 12, 1)
DEFLINK(CMPBGE_LINK, 0x0f, "cmpbge_link", 12, 1)
DEFLINK(S8ADDL_LINK, 0x12, "s8addl_link", 12, 1)
DEFLINK(S8SUBL_LINK, 0x1b, "s8subl_link", 12, 1)
DEFLINK(CMPULT_LINK, 0x1d, "cmpult_link", 12, 1)
DEFLINK(ADDQ_LINK, 0x20, "addq_link", 12, 1)
DEFLINK(S4ADDQ_LINK, 0x22, "s4addq_link", 12, 1)
DEFLINK(SUBQ_LINK, 0x29, "subq_link", 12, 1)
DEFLINK(S4SUBQ_LINK, 0x2b, "s4subq_link", 12, 1)
DEFLINK(CMPEQ_LINK, 0x2d, "cmpeq_link", 12, 1)
DEFLINK(S8ADDQ_LINK, 0x32, "s8addq_link", 12, 1)
DEFLINK(S8SUBQ_LINK, 0x3b, "s8subq_link", 12, 1)
DEFLINK(CMPULE_LINK, 0x3d, "cmpule_link", 12, 1)
DEFLINK(ADDLV_LINK, 0x40, "addlv_link", 12, 1)
DEFLINK(SUBLV_LINK, 0x49, "sublv_link", 12, 1)
DEFLINK(CMPLT_LINK, 0x4d, "cmplt_link", 12, 1)
DEFLINK(ADDQV_LINK, 0x60, "addqv_link", 12, 1)
DEFLINK(SUBQV_LINK, 0x69, "subqv_link", 12, 1)
DEFLINK(CMPLE_LINK, 0x6d, "cmple_link", 12, 1)
CONNECT(ADDL_LINK)
#define ADDL_IMPL \
{ \
SET_GPR(RC, SEXT32((GPR(RA) + GPR(RB)) & ULL(0xffffffff))); \
}
DEFINST(ADDL, 0x00,
"addl", "a,b,c",
IntALU, F_ICOMP,
DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA)
#define ADDLI_IMPL \
{ \
SET_GPR(RC, SEXT32((GPR(RA) + IMM) & ULL(0xffffffff))); \
}
DEFINST(ADDLI, 0x01,
"addl", "a,i,c",
IntALU, F_ICOMP|F_IMM,
DGPR(RC), DNA, DGPR(RA), DNA, DNA)
CONNECT(S4ADDL_LINK)
#define S4ADDL_IMPL \
{ \
SET_GPR(RC, SEXT32(((GPR(RA) << 2) + GPR(RB)) & ULL(0xffffffff))); \
}
DEFINST(S4ADDL, 0x00,
"s4addl", "a,b,c",
IntALU, F_ICOMP,
DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA)
#define S4ADDLI_IMPL \
{ \
SET_GPR(RC, SEXT32(((GPR(RA) << 2) + IMM) & ULL(0xffffffff))); \
}
DEFINST(S4ADDLI, 0x01,
"s4addl", "a,i,c",
IntALU, F_ICOMP|F_IMM,
DGPR(RC), DNA, DGPR(RA), DNA, DNA)
CONNECT(SUBL_LINK)
#define SUBL_IMPL \
{ \
SET_GPR(RC, SEXT32((GPR(RA) - GPR(RB)) & ULL(0xffffffff))); \
}
DEFINST(SUBL, 0x00,
"subl", "a,b,c",
IntALU, F_ICOMP,
DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA)
#define SUBLI_IMPL \
{ \
SET_GPR(RC, SEXT32((GPR(RA) - IMM) & ULL(0xffffffff))); \
}
DEFINST(SUBLI, 0x01,
"subl", "a,i,c",
IntALU, F_ICOMP|F_IMM,
DGPR(RC), DNA, DGPR(RA), DNA, DNA)
CONNECT(S4SUBL_LINK)
#define S4SUBL_IMPL \
{ \
SET_GPR(RC, SEXT32(((GPR(RA) << 2) - GPR(RB)) & ULL(0xffffffff))); \
}
DEFINST(S4SUBL, 0x00,
"s4subl", "a,b,c",
IntALU, F_ICOMP,
DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA)
#define S4SUBLI_IMPL \
{ \
SET_GPR(RC, SEXT32(((GPR(RA) << 2) - IMM) & ULL(0xffffffff))); \
}
DEFINST(S4SUBLI, 0x01,
"s4subl", "a,i,c",
IntALU, F_ICOMP|F_IMM,
DGPR(RC), DNA, DGPR(RA), DNA, DNA)
CONNECT(CMPBGE_LINK)
#define CMPBGE_IMPL \
{ \
int _i; \
qword_t _rav, _rbv; \
\
_rav = GPR(RA); \
_rbv = GPR(RB); \
SET_GPR(RC, 0); \
\
for (_i = 56; _i >= 0; _i -= 8) \
{ \
SET_GPR(RC, GPR(RC) << 1); \
SET_GPR(RC, (GPR(RC) \
| ((_rav >> _i & (sqword_t)0xff) >= \
(_rbv >> _i & (sqword_t)0xff)))); \
} \
}
DEFINST(CMPBGE, 0x00,
"cmpbge", "a,b,c",
IntALU, F_ICOMP,
DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA)
#define CMPBGEI_IMPL \
{ \
int _i; \
qword_t _rav, _rbv; \
\
_rav = GPR(RA); \
_rbv = IMM; \
SET_GPR(RC, 0); \
\
for (_i = 56; _i >= 0; _i -= 8) \
{ \
SET_GPR(RC, GPR(RC) << 1); \
SET_GPR(RC, (GPR(RC) \
| ((_rav >> _i & (sqword_t)0xff) >= \
(_rbv >> _i & (sqword_t)0xff)))); \
} \
}
DEFINST(CMPBGEI, 0x01,
"cmpbge", "a,i,c",
IntALU, F_ICOMP|F_IMM,
DGPR(RC), DNA, DGPR(RA), DNA, DNA)
CONNECT(S8ADDL_LINK)
#define S8ADDL_IMPL \
{ \
SET_GPR(RC, SEXT32(((GPR(RA) << 3) + GPR(RB)) & ULL(0xffffffff))); \
}
DEFINST(S8ADDL, 0x00,
"s8addl", "a,b,c",
IntALU, F_ICOMP,
DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA)
#define S8ADDLI_IMPL \
{ \
SET_GPR(RC, SEXT32(((GPR(RA) << 3) + IMM) & ULL(0xffffffff))); \
}
DEFINST(S8ADDLI, 0x01,
"s8addl", "a,i,c",
IntALU, F_ICOMP|F_IMM,
DGPR(RC), DNA, DGPR(RA), DNA, DNA)
CONNECT(S8SUBL_LINK)