Choosing FPGA

[marmeladapk]

Basically we have to choose between:

• Artix 7 100T, 484 package
  • This version is used in Kasli and Phaser, which means we'll have better prices
• Artix 7 100T, 676 package
  • Adds 4 GTP channels (total 8 RX + 8 TX)
  • Adds some missing pins from bank 13
• maybe Artix 7 200T in 676 package?
  • same as 100T in 676 package but 2 additional IO banks
  • we could add more SDRAM for example

With all of the above I can place pins so that LA gets two banks, and HA and HB each get their own bank, separate from non-FMC signals. This will allow us to enable/disable power supply to FMC and corresponding IO banks and set VADJ as we please (well, mostly).

There was an idea to allow placing a smaller FPGA (50T or even 15T) in 484 package which would support LPC signals and a subset of HPC, but I didn't find any configuration that would support all HPC signals and not share pins across IO banks in HPC variant. If we can put some HB signals in LA bank then we could make a LPC variant with a smaller FPGA.
Note that this is only possible in 484 package.

We could also drop SDRAM, which would allow us to make a HPC/LPC board.

There are few things to consider here:

• VREF
  • FMC card supplies VREF voltages
  • With Artix 100T 484 we can't support VREF on HA and on 1/2 of LA (VREF takes pins which are needed by HA/LA signals)
  • 100T 676 allows us to support VREF on all groups except HA
  • IMO not connecting VREF to FPGA pins should not be a problem, because we can use internal VREF. Internal VREF can be set to accommodate all IO standards that are supported by the FPGA. But it should be set when generating gateware for specific FMC
• Board support
  I looked at FMCs listed in the meta issue to check what signals are they using:

Board\Signals	LA (0-33)	HA (0-23)	HB (0-21)	CLK (0-3+GBT0-1)	MGT (0-9)	VADJ [V]
FMC CoaXPress 2.0	0-4, 11-12, 14, 16-26	-	-	GBT0 M2C	0-3	1,1-3,46
FMC ADC 100M 10B TDC 16cha	0-33	0-23	0-21	0-3	-	2,5 (LVDS)
FMC ADC 100M 14b 4cha	0-33	-	-	0-2	-	2,5
Shuttler	0-32	0-23	0-21	0-3	-	2,5 (LVDS)
FMC ADC 4 cha 1G 12b	0-33	-	-	GBT0	0-7	1,2-3,6, diff

I'm not sure if when the FMC uses differential signals we need to use LVDS, or maybe some other differential standard may work. Which brings me to:

• VADJ
  • Setting VADJ to only P2V5 will be the easiest option
  • Having VADJ be really adjustable in 1,2V-3,3V range is problematic:
    • 4 FMC clocks (2 inputs, 2 bidir) use LVDS standard which requires VCCO to be 2,5V for proper support
    • We could place 2 input clocks in a LA bank but we'll need external termination (AR 43989)
    • We could place 2 bidir clocks in a bank with EEM signals (which is fixed to 2V5 VCCO) to MRCC pins, however I'm not sure if they can drive banks that are far away (@sbourdeauducq, @jordens do you know this?)

My preliminary pinout proposition:

Notes:

• This is a 484 package

• No signals are shared in LA/HA/HB groups between IO banks

• FMC banks can be swapped between each other

• EEM signals should be in bank 14 since this is the only bank with fixed P2V5 voltage

• Bank 13 is only partially bonded out

IMO we should choose between configuration shown above or 100T in 676 package to get 8 GTPs in total. Keep in mind that Artix 7 GTPs run at max. 6,6 GBPS.

What are your thoughts?

@dhslichter @cjbe @sbourdeauducq @jordens @gkasprow

[dhslichter]

I am not that worried about pricing -- I think we will use enough of these that we will hit price breaks. A bigger issue that I can see right now is that all of these FPGAs seem to be out of stock, with roughly a 1-year lead time. Is there a supply on hand of Kasli/Phaser FPGAs?

[dhslichter]

Actually, I take that back: https://www.digikey.com/en/products/detail/xilinx-inc/XC7A200T-2FBG676C/3925779

I suggest we buy a bunch immediately @gkasprow @marmeladapk unless you have some other reliable supply avenue.

@sbourdeauducq @jordens can we use the -2 speed grade or do we need -3 to run at typical RTIO clock frequencies?

Any opinions on the C vs I temperature range? Do we have measurements on how hot the FPGAs get in e.g. Kasli?

[sbourdeauducq]

AFAIK Technosystem are getting 100T much faster than this.

[dhslichter]

If so, then that is good. I am only able to check standard vendors like Digikey etc, where lead times are horrendous.

[marmeladapk]

I asked Creotech for prices and availability of several Artix 7 options. But most probably 100T 484 will be the easiest to get.

I would prefer the 676 package so we make full use of the I/O and have more GTPs available.

@dhslichter 676 package in practice doesn't change I/O situation, it only gives us 4 additional GTPs. With 484 we can use whole FMC HPC except with 4 out of 10 gigabit links. We need to see if potentially lower availability and higher price is worth it.

BTW what FMCs do you have in mind that need 8 MGTs?

[dhslichter]

I don't need 8 MGTs, but it looks like the FMC ADC 4 cha 1G 12b listed above does? I was basing the 8 MGT idea on the idea of people wanting that card, but I don't have a need for that card.

As long as we can have SDRAM, plus full Shuttler connectivity, with the 484, it's OK with me. The 200 T gives ~2x the FPGA resources, which is nice if one has space-hungry gateware, but I think the 100T should be fine for running Shuttler. The idea of the 676 was that then one could place a 200T instead of a 100T if FPGA resources was a major concern.

Still, for me the main question is what chips are actually available and can be purchased. If we can buy 100T 484 and that's our best bet, then I don't have an objection.

[marmeladapk]

FMC ADC 4 cha 1G 12b wasn't mentioned by anyone. I just added it to the list as an example which might require more MGTs. So far nobody expressed any interest in using an FMC which would require more than 4 GTPs.

As for 200T, theoretically we can also get it in 484 package.

[dhslichter]

@marmeladapk any updates on availability?

[marmeladapk]

Well, availability of most electronic components right now is pretty bad. I went with 100T right now, as maybe it'll be easier to buy a larger batch of FPGAs that can be used in multiple sinara boards (phaser, kasli). The only thing we can do here is to also include 75T and 200T in various speed grades, but it'll complicate software support.