Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Changelog v1.1.1 #73

Open
8 tasks done
maciejprzybysz opened this issue Mar 2, 2023 · 0 comments
Open
8 tasks done

Changelog v1.1.1 #73

maciejprzybysz opened this issue Mar 2, 2023 · 0 comments

Comments

@maciejprzybysz
Copy link
Member

maciejprzybysz commented Mar 2, 2023 •
edited
Loading

Minor changes:

  • TOP level schematic document had invalid version number (v1.0)
  • Unnecessary "NO ERC" directive on Kasli-SOC_QUAD_BUCK.SchDoc X:50mil Y:6500mil
  • J25 is moved away from the board edge in v1.1 - no change in v1.1.1, just noticed here (no issue nor changelog about that found)
  • Validation errors/warnings corrected
  • IC4 hidden GND pin
  • synchronize ports and sheet entries on Kasli-SOC_top.SchDoc sheet symbols (harness types)
  • DRC errors (no net via + poly top/bot)
  • Changed version number on panel (was v1.0)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@maciejprzybysz