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Joe Britton edited this page Oct 16, 2023 · 8 revisions

As of 10/6/2023 support for building gateware, compiling firmware and flashing Kasli-SOC is not merged with ARTIQ master. What follows is context for these operations; it is a supplement to the information provided by M-Labs.

Three files are required to boot Kasli-SoC.

  • szl.elf-- A bootloader supplied by the M-Labs nix script. (Britton can't track down it's origin.)
  • runtime.bin -- This is user-defined firmware that runs on one of the hardcore ARM uP.
  • top.bin -- This is user-defined gateware that runs on the FPGA.

There are two routes for booting Kasli-SoC: 1) booting from the micro-SD flash and 2) booting from a combination of JTAG-over-USB plus ethernet (using artiq_netboot).

Compiling

The M-Labs supplied README.md and scripts are rough around the edges and provide little context for the prescribed steps. What follows fills in some gaps.

  • Pull from https://git.m-labs.hk/M-Labs/artiq-zynq and checkout release-7.
  • $ nix develop
  • Put your hardware description file variant.json in the src folder.
  • The following generates ../build/gateware/top.bit: $ gateware/kasli_soc.py -g ../build/gateware variant.json
  • The included Makefile nominally generates ../build/firmware.bin but it has some trivial bugs. When I fix the bugs the following works $ make TARGET=kasli_soc JSON=variant.json.

Booting from USB+Ethernet

This approach relies on openocd to install the szl boot loader onto the ARM uP using JTAG-over-USB, then top.bin and firmware.bin are transmitted to Kasli-SOC over Ethernet using artiq_netboot. Set the DIP switches on Kasli-SOC. There's a script that does this in the M-Labs repository called local_run.sh. It has some trivial path-related bugs that are easy to fix.

Between successive calls to local_run.sh the board must be reset using POR reset. See Issue #2250. Note that this requires setting the PS_POR_B jumper.

Booting from micro-SD

This requires two files to be installed at the root of a FAT32-formatted micro-SD card.

  • boot.bin : A file generated by the nix build system that combines slz.elf, runtime.bin and top.bin.
  • config.txt : A text file containing the Kasli-SOC IP address: eg "ip=192.168.1.45"

It is unclear how to trigger nix build to generate a user-specified boot.bin.

Set the DIP switches on Kasli-SOC.

Successful Boot

Following is what success looks like when booting from USB+Ethernet.

  • The "FPGA DONE" LED on the PCB should be illuminated.
  • The board responds to ping on the ETH port.
  • The following is observed from the second (of four) USB interfaces presented by Kasli-SOC.


                     __________   __
                    / ___/__  /  / /
                    \__ \  / /  / /
                   ___/ / / /__/ /___
                  /____/ /____/_____/

                 (C) 2020-2022 M-Labs

[     0.019992s]  INFO(szl): Simple Zynq Loader starting...
[     0.025198s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 2000000000 Hz
[     0.007040s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[     0.016259s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1066666666 Hz
[     0.023609s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 533333328/355555552
[     0.030778s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10062892 Hz (divisors=2*53)
[     0.042000s] DEBUG(libboard_zynq::sdio): Reset SDIO!
[     0.046870s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000
[     0.053896s]  INFO(szl): Card inserted. Mounting file system.
[     0.196690s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 25000000
[     0.203822s] DEBUG(libboard_zynq::sdio::sd_card): Getting bus width
[     0.212199s] DEBUG(libboard_zynq::sdio::sd_card): 4 bit support
[     0.218100s] DEBUG(libboard_zynq::sdio::sd_card): Changing bus width
[     0.226001s] DEBUG(libboard_zynq::sdio): Set block size to 512
[     0.235964s] DEBUG(libconfig::sd_reader): Partition ID: C
[     0.242222s]  INFO(szl::netboot): Preparing network for netboot
[     0.253323s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.288070s]  INFO(szl::netboot): Network addresses: MAC=fc-0f-e7-07-6b-8c IPv4=192.168.1.44 
[     0.296627s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998
[     0.306600s]  INFO(szl::netboot): Waiting for connections...
[     5.032611s]  INFO(szl::netboot): Received firmware load command
[     5.099255s]  INFO(szl::netboot): Firmware successfully downloaded
[     5.107080s]  INFO(szl::netboot): Received gateware load command
[     5.357741s]  INFO(szl::netboot): Preprocessing bitstream...
[     5.390516s] DEBUG(libboard_zynq::devc): Invalidate DCache for bitstream buffer
[     5.403743s] DEBUG(libboard_zynq::devc): Init preload FPGA
[     5.409209s] DEBUG(libboard_zynq::devc): Toggling PROG_B
[     5.437893s] DEBUG(libboard_zynq::devc): Waiting for done
[     5.443271s] DEBUG(libboard_zynq::devc): Init postload FPGA
[     5.448824s]  INFO(szl::netboot): Gateware successfully downloaded
[     5.454987s]  INFO(szl::netboot): Received boot command
[     5.460213s]  INFO(szl): Preparing for runtime execution
[     5.465850s]  INFO(szl): executing payload
[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005162s]  INFO(runtime): gateware ident: brittonlab-legacy-trap
[     0.016672s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.176190s]  WARN(runtime::rtio_clocking): error reading configuration. Falling back to default.
[     0.184972s]  WARN(runtime::rtio_clocking): Using default configuration - internal 125MHz RTIO clock.
[     0.194250s]  INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock
[     0.585119s]  INFO(libboard_artiq::si5324): waiting for Si5324 lock...
[     7.267819s]  INFO(libboard_artiq::si5324):   ...locked
[     7.274986s]  INFO(runtime::rtio_clocking): RTIO PLL locked
[     7.285744s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     7.321120s]  INFO(runtime::comms): network addresses: MAC=fc-0f-e7-07-6b-8c IPv4=192.168.1.44 IPv6-LL=fe80::fe0f:e7ff:fe07:6b8c IPv6: no configured address
[    11.339080s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[   125.616020s]  INFO(runtime::mgmt): received connection
  • The following is observed from artiq_coremgmt.
$ artiq_coremgmt log
[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005162s]  INFO(runtime): gateware ident: brittonlab-legacy-trap
[     0.016672s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.176190s]  WARN(runtime::rtio_clocking): error reading configuration. Falling back to default.
[     0.184972s]  WARN(runtime::rtio_clocking): Using default configuration - internal 125MHz RTIO clock.
[     0.194250s]  INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock
[     0.585119s]  INFO(libboard_artiq::si5324): waiting for Si5324 lock...
[     7.267819s]  INFO(libboard_artiq::si5324):   ...locked
[     7.274986s]  INFO(runtime::rtio_clocking): RTIO PLL locked
[     7.285744s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     7.321120s]  INFO(runtime::comms): network addresses: MAC=fc-0f-e7-07-6b-8c IPv4=192.168.1.44 IPv6-LL=fe80::fe0f:e7ff:fe07:6b8c IPv6: no configured address
[    11.339080s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[   125.616020s]  INFO(runtime::mgmt): received connection

Kasli-SOC

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