Merge pull request #1241 from slaclab/pre-release

Release Candidate v2.56.0

Author: ruck314

.github/workflows/surf_ci.yml

@@ -22,7 +22,7 @@ jobs:
 
   test_and_document:
     name: Test And Generate Documentation
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     steps:
 
       # This step checks out a copy of your repository.
@@ -32,24 +32,31 @@ jobs:
 
       - uses: actions/setup-python@v4
         with:
-          python-version: 3.11
+          python-version: 3.12
 
       - name: Install dependencies
         run: |
           sudo apt-get update
-          sudo apt-get install make python3 python3-pip tclsh
+          sudo apt-get install make python3 python3-pip tclsh ghdl
           sudo apt-get install doxygen doxygen-doc doxygen-latex doxygen-gui graphviz
           python -m pip install --upgrade pip
           pip install -r pip_requirements.txt
           git clone https://github.com/slaclab/ruckus.git
           pip install -r ruckus/scripts/pip_requirements.txt
 
-      - name: Check for trailing whitespace
+      - name: Check for trailing whitespace and tabs
         run: |
-          if grep -rnI '[[:blank:]]$' --include=\*.{vhd,v,tcl,py} .; then
+          # Check for trailing whitespace
+          if grep -rnI '[[:blank:]]$' --include=\*.{vhd,tcl,py} .; then
             echo "Error: Trailing whitespace found in the repository!"
             exit 1
           fi
+          
+          # Check for tab characters instead of spaces
+          if grep -rnI $'\t' --include=\*.{vhd,tcl,py} .; then
+            echo "Error: Tab characters found in the repository! Please use spaces for indentation."
+            exit 1
+          fi
 
       - name: Python Syntax and Linter Checking
         run: |
@@ -62,10 +69,8 @@ jobs:
 
       - name: VHDL Regression Testing
         run: |
-          ./ghdl-build.sh > /dev/null 2>&1
           make MODULES=$PWD
           python -m pytest --cov -v tests/
-          rm -rf ghdl-build
 
 #      # Code Coverage
 #      - name: Code Coverage

axi/axi4/rtl/AxiReadPathFifo.vhd

@@ -32,7 +32,7 @@ entity AxiReadPathFifo is
       GEN_SYNC_FIFO_G          : boolean                    := false;
 
       -- Bit Optimizations
-      ADDR_LSB_G               : natural range 0 to 31 := 0;
+      ADDR_LSB_G               : natural range 0 to 63 := 0;
       ID_FIXED_EN_G            : boolean := false;
       SIZE_FIXED_EN_G          : boolean := false;
       BURST_FIXED_EN_G         : boolean := false;