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1 parent d30abdb commit dcd2a60Copy full SHA for dcd2a60
axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd
@@ -286,7 +286,7 @@ architecture rtl of AxiStreamDmaV2Desc is
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begin
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assert (AXI_CONFIG_G.ADDR_WIDTH_C <= 40)
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- report "AXI_CONFIG_G.ADDR_WIDTH_C (" & str(AXI_CONFIG_G.ADDR_WIDTH_C) & ") must be <= 40" severity failure;
+ report "AXI_CONFIG_G.ADDR_WIDTH_C (" & integer'image(AXI_CONFIG_G.ADDR_WIDTH_C) & ") must be <= 40" severity failure;
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-----------------------------------------
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-- Write Free List FIFOs
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