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adding sy89297 to SURF
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‎devices/Microchip/ruckus.tcl

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Original file line numberDiff line numberDiff line change
@@ -3,3 +3,4 @@ source $::env(RUCKUS_PROC_TCL)
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# Load ruckus files
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loadRuckusTcl "$::DIR_PATH/sy56040"
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loadRuckusTcl "$::DIR_PATH/sy89297"

‎devices/Microchip/sy89297/rtl/Sy89297.vhd

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-------------------------------------------------------------------------------
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-- Company : SLAC National Accelerator Laboratory
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-------------------------------------------------------------------------------
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-- Description: This controller is designed around the Microchip SY89297UMH
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-------------------------------------------------------------------------------
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-- This file is part of 'SLAC Firmware Standard Library'.
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-- It is subject to the license terms in the LICENSE.txt file found in the
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-- top-level directory of this distribution and at:
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-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
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-- No part of 'SLAC Firmware Standard Library', including this file,
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-- may be copied, modified, propagated, or distributed except according to
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-- the terms contained in the LICENSE.txt file.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library surf;
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use surf.StdRtlPkg.all;
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use surf.AxiStreamPkg.all;
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use surf.AxiLitePkg.all;
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entity Sy89297 is
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generic (
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TPD_G : time := 1 ns;
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SIMULATION_G : boolean := false);
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port (
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-- Delay control signals
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enableL : out sl;
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enaL : out sl;
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enbL : out sl;
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sdata : out sl;
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sclk : out sl;
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sload : out sl;
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-- AXI-Lite Interface
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axilClk : in sl;
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axilRst : in sl;
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axilReadMaster : in AxiLiteReadMasterType;
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axilReadSlave : out AxiLiteReadSlaveType;
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axilWriteMaster : in AxiLiteWriteMasterType;
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axilWriteSlave : out AxiLiteWriteSlaveType);
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end Sy89297;
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architecture rtl of Sy89297 is
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type StateType is (
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IDLE_S,
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SEND_DATA_S,
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SLOAD_S);
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type RegType is record
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delayA : slv(9 downto 0);
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delayB : slv(9 downto 0);
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busy : sl;
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cnt : natural range 0 to 20;
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shiftReg : slv(19 downto 0);
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-- Serial Clock Generation
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sclkEn : sl;
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sclkCnt : slv(7 downto 0);
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sckHalfCycle : slv(7 downto 0);
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-- I/O Signals
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sclk : sl;
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sload : sl;
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-- AXIL and state machine
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axilReadSlave : AxiLiteReadSlaveType;
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axilWriteSlave : AxiLiteWriteSlaveType;
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state : StateType;
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end record RegType;
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constant REG_INIT_C : RegType := (
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delayA => (others => '0'),
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delayB => (others => '0'),
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busy => '0',
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cnt => 0,
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shiftReg => (others => '0'),
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-- Serial Clock Generation
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sclkEn => '0',
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sclkCnt => (others => '0'),
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sckHalfCycle => ite(SIMULATION_G, x"00", x"0F"),
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-- I/O Signals
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sclk => '0',
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sload => '1',
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-- AXIL and state machine
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axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
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axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C,
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state => IDLE_S);
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signal r : RegType := REG_INIT_C;
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signal rin : RegType;
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begin
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comb : process (axilReadMaster, axilRst, axilWriteMaster, r) is
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variable v : RegType;
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variable axilStatus : AxiLiteStatusType;
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variable axilWriteResp : slv(1 downto 0);
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variable axilReadResp : slv(1 downto 0);
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begin
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-- Latch the current value
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v := r;
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-- Reset strobes
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axilWriteResp := AXI_RESP_OK_C;
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axilReadResp := AXI_RESP_OK_C;
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-- Check for timeout
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if r.sclkCnt = 0 then
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-- Check if enabled
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if (r.sclkEn = '1') then
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-- Set the flag
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v.sclk := not(r.sclk);
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end if;
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-- Preset counter
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v.sclkCnt := r.sckHalfCycle;
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else
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-- Decreament counter
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v.sclkCnt := r.sclkCnt - 1;
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end if;
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-- Determine the transaction type
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axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axilStatus);
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case r.state is
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----------------------------------------------------------------------
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when IDLE_S =>
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-- Reset the signals in IDLE state
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v.busy := '0';
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v.sload := '1';
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v.sclk := '0';
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v.sclkEn := '0';
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v.sclkCnt := r.sckHalfCycle;
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v.cnt := 0;
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-- Check for a write request
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if (axilStatus.writeEnable = '1') then
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-- Decode address and perform write
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case (axilWriteMaster.awaddr(3 downto 0)) is
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--------------------------------------------------------
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when x"0" =>
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-- Set the value
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v.delayA := axilWriteMaster.wdata(9 downto 0);
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-- Set the flags
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v.busy := '1';
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v.sload := '0';
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v.sclkEn := '1';
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-- Next state
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v.state := SEND_DATA_S;
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--------------------------------------------------------
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when x"4" =>
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-- Set the value
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v.delayB := axilWriteMaster.wdata(9 downto 0);
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-- Set the flags
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v.busy := '1';
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v.sload := '0';
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v.sclkEn := '1';
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-- Next state
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v.state := SEND_DATA_S;
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--------------------------------------------------------
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when x"C" =>
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-- Set the value
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v.sckHalfCycle := axilWriteMaster.wdata(7 downto 0);
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-- Send AXI-Lite response
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axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp);
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--------------------------------------------------------
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when others =>
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axilWriteResp := AXI_RESP_DECERR_C;
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-- Send AXI-Lite response
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axiSlaveWriteResponse(v.axilWriteSlave, AXI_RESP_DECERR_C);
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--------------------------------------------------------
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end case;
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-- Check for a read request
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elsif (axilStatus.readEnable = '1') then
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case (axilReadMaster.araddr(3 downto 0)) is
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--------------------------------------------------------
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when x"0" =>
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v.axilReadSlave.rdata(9 downto 0) := r.delayA;
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--------------------------------------------------------
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when x"4" =>
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v.axilReadSlave.rdata(9 downto 0) := r.delayB;
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--------------------------------------------------------
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when x"C" =>
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v.axilReadSlave.rdata(7 downto 0) := r.sckHalfCycle;
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--------------------------------------------------------
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when others =>
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axilReadResp := AXI_RESP_DECERR_C;
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--------------------------------------------------------
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end case;
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-- Send AXI-Lite Response
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axiSlaveReadResponse(v.axilReadSlave, axilReadResp);
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end if;
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-- Update the shift Register value
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v.shiftReg := v.delayB & v.delayA;
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-------------------------------------------------
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when SEND_DATA_S =>
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-- Check for SCLK fallling edge
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if (r.sclk = '1') and (v.sclk = '0') then
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-- Update the shift register
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v.shiftReg := '0' & r.shiftReg(19 downto 1);
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-- Increment the counter
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v.cnt := r.cnt + 1;
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end if;
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-- Check for SCLK rising edge
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if (r.sclk = '0') and (v.sclk = '1') then
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-- Check for last serial bit
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if r.cnt = 19 then
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-- Reset counter
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v.cnt := 0;
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-- Next state
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v.state := SLOAD_S;
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end if;
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end if;
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-------------------------------------------------
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when SLOAD_S =>
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-- Check for timeout
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if r.sclkCnt = 0 then
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-- Increment the counter
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v.cnt := r.cnt + 1;
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if (r.cnt = 0) then
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-- Reset flag
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v.sclkEn := '0';
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elsif (r.cnt = 1) then
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-- Set flag
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v.sload := '1';
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else
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-- Send AXI-Lite response
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axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp);
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-- Next state
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v.state := IDLE_S;
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end if;
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end if;
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-------------------------------------------------
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end case;
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-- Outputs
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axilWriteSlave <= r.axilWriteSlave;
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axilReadSlave <= r.axilReadSlave;
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enableL <= r.busy; -- Active LOW
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enaL <= r.busy; -- Active LOW
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enbL <= r.busy; -- Active LOW
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sdata <= r.shiftReg(0);
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sclk <= r.sclk;
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sload <= r.sload;
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-- Reset
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if (axilRst = '1') then
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v := REG_INIT_C;
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end if;
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-- Register the variable for next clock cycle
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rin <= v;
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end process;
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seq : process (axilClk) is
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begin
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if rising_edge(axilClk) then
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r <= rin after TPD_G;
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end if;
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end process seq;
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end rtl;

‎devices/Microchip/sy89297/ruckus.tcl

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# Load RUCKUS library
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source $::env(RUCKUS_PROC_TCL)
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# Load Source Code
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loadSource -lib surf -dir "$::DIR_PATH/rtl"

‎python/surf/devices/microchip/_Sy89297.py

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##############################################################################
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## This file is part of 'SLAC Firmware Standard Library'.
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## It is subject to the license terms in the LICENSE.txt file found in the
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## top-level directory of this distribution and at:
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## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
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## No part of 'SLAC Firmware Standard Library', including this file,
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## may be copied, modified, propagated, or distributed except according to
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## the terms contained in the LICENSE.txt file.
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##############################################################################
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import pyrogue as pr
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class Sy89297(pr.Device):
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def __init__( self, **kwargs):
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super().__init__(**kwargs)
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self.add(pr.RemoteVariable(
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name = 'DelayA',
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description = 'Delay Channel A',
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offset = 0x0,
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bitSize = 10,
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mode = 'RW',
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units = '5ps/step',
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))
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self.add(pr.RemoteVariable(
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name = 'DelayB',
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description = 'Delay Channel B',
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offset = 0x4,
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bitSize = 10,
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mode = 'RW',
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units = '5ps/step',
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))
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self.add(pr.RemoteVariable(
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name = 'SckHalfPeriod',
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offset = 0xC,
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bitSize = 8,
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mode = 'RW',
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hidden = True,
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))
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def setDelay(self, delayA=None, delayB=None):
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if delayA is not None:
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if self.DelayB.value() != delayA:
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self.DelayA.set(delayA)
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if delayB is not None:
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if self.DelayB.value() != delayB:
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self.DelayB.set(delayB)

‎python/surf/devices/microchip/__init__.py

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from surf.devices.microchip._Axi24LC64FT import *
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from surf.devices.microchip._AxiSy56040 import *
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from surf.devices.microchip._Tcn75a import *
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from surf.devices.microchip._Sy89297 import *

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