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variant(u5): add Nucleo-U5A5ZJ-Q
Signed-off-by: patricklaf <[email protected]> Co-authored-by: Frederic Pillon <[email protected]>
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‎README.md

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@@ -121,6 +121,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32L4R5ZI-P | [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) | *1.4.0* | |
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| :green_heart: | STM32L552ZE-Q | [Nucleo L552ZE-Q](https://www.st.com/en/evaluation-tools/nucleo-l552ze-q.html) | *2.0.0* | |
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| :green_heart: | STM32U575ZI-Q | [NUCLEO-U575ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html) | *2.1.0* | |
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| :yellow_heart: | STM32U5A5ZJ-Q | [NUCLEO-U5A5ZJ-Q](https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html) | **2.11.0** | |
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### [Nucleo 64](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-nucleo-boards.html) boards
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‎boards.txt

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@@ -380,6 +380,22 @@ Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.peripheral_pins=-DCUSTOM_PERIPHERAL_P
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.openocd.target=stm32u5x
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U575.svd
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# NUCLEO_U5A5ZJ_Q board
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q=Nucleo U5A5ZJ-Q
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.node=NOD_U5A5ZJ
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.upload.maximum_size=4194304
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.upload.maximum_data_size=2555904
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.mcu=cortex-m33
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.fpu=-mfpu=fpv4-sp-d16
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.float-abi=-mfloat-abi=hard
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.board=NUCLEO_U5A5ZJ_Q
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.series=STM32U5xx
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.product_line=STM32U5A5xx
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.openocd.target=stm32u5x
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Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5A5.svd
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# Upload menu
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Nucleo_144.menu.upload_method.MassStorage=Mass Storage
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Nucleo_144.menu.upload_method.MassStorage.upload.protocol=

‎variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/variant_NUCLEO_U575ZI_Q.cpp

+39-27
Original file line numberDiff line numberDiff line change
@@ -174,43 +174,46 @@ WEAK void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
177-
RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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RCC_CRSInitTypeDef RCC_CRSInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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/*
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* Switch to SMPS regulator instead of LDO
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*/
183+
if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) {
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Error_Handler();
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}
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180187
/** Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
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Error_Handler();
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}
185-
/** Configure LSE Drive Capability
186-
*/
187-
HAL_PWR_EnableBkUpAccess();
188-
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
189-
/** Initializes the CPU, AHB and APB busses clocks
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
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| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
196+
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
197-
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
198-
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
199-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV4;
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RCC_OscInitStruct.PLL.PLLM = 3;
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RCC_OscInitStruct.PLL.PLLN = 10;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 20;
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RCC_OscInitStruct.PLL.PLLP = 8;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 1;
209+
RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
213-
/** Initializes the CPU, AHB and APB busses clocks
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
@@ -224,28 +227,37 @@ WEAK void SystemClock_Config(void)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
225228
Error_Handler();
226229
}
227-
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC1
228-
| RCC_PERIPHCLK_CLK48;
229-
PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSI;
230-
PeriphClkInit.Dac1ClockSelection = RCC_DAC1CLKSOURCE_LSE;
231-
PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
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233-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
234-
Error_Handler();
235-
}
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/** Enable the SYSCFG APB clock
237232
*/
238233
__HAL_RCC_CRS_CLK_ENABLE();
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239235
/** Configures CRS
240236
*/
241237
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
242-
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
238+
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_LSE;
243239
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
244-
RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
240+
RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 32768);
245241
RCC_CRSInitStruct.ErrorLimitValue = 34;
246242
RCC_CRSInitStruct.HSI48CalibrationValue = 32;
247243

248244
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
245+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_ADCDAC
246+
| RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_LPUART1
247+
| RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_CLK48
248+
| RCC_PERIPHCLK_USBPHY;
249+
PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_SYSCLK;
250+
PeriphClkInit.Dac1ClockSelection = RCC_DAC1CLKSOURCE_LSE;
251+
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
252+
PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
253+
PeriphClkInit.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_CLK48;
254+
PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
255+
256+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
257+
Error_Handler();
258+
}
259+
260+
249261
}
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251263
#ifdef __cplusplus

‎variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/CMakeLists.txt

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@@ -23,6 +23,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
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PeripheralPins.c
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PeripheralPins_NUCLEO_U5A5ZJ_Q.c
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variant_generic.cpp
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variant_NUCLEO_U5A5ZJ_Q.cpp
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)
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target_link_libraries(variant_bin PUBLIC variant_usage)
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