diff --git a/project/gtxl.xpr b/project/gtxl.xpr
index 2baca3f..48d46e1 100644
--- a/project/gtxl.xpr
+++ b/project/gtxl.xpr
@@ -44,7 +44,7 @@
-
+
diff --git a/src/hdl/control.vhd b/src/hdl/control.vhd
index fec06c2..9f58c70 100644
--- a/src/hdl/control.vhd
+++ b/src/hdl/control.vhd
@@ -26,6 +26,7 @@ library work; use work.tools_pkg.all;
entity control is
port( iClk : in sl;
+ iWrClk : in sl;
iInst : in slv(7 downto 0);
iCarry : in sl;
iSign : in sl;
@@ -180,7 +181,7 @@ begin
fullName <= opName & modeName(1 to 8) & modeName(9 to 12) when busDriveName = " MEM" else
opName & busDriveName & modeName(9 to 12);
- oRamWrN <= '0' when (iClk='0') and (opName=" ST") and (oMemDrive='1') else '1';
+ oRamWrN <= '0' when (iWrClk='0') and (opName=" ST") and (oMemDrive='1') else '1';
----------------------------------------------------------
------ Branch/Jump detection -------
diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd
index 138dcf0..1123c09 100644
--- a/src/hdl/cpu.vhd
+++ b/src/hdl/cpu.vhd
@@ -34,26 +34,41 @@ end entity cpu;
architecture ttl of cpu is
signal rstN : sl;
+ signal sysClk : sl;
+ signal wrClk : sl;
+ -- State signals
signal stateN : slv(7 downto 0);
signal stateOp : slv(1 downto 0);
signal instFetch : sl;
signal immFetch : sl;
signal execute : sl;
+
+ -- Program counter signals
+ signal PCReg : slv(15 downto 0);
signal pcClear : sl;
- signal pcCount : sl;
signal pcLoadLo : sl;
signal pcLoadHi : sl;
-
signal terminal0 : sl;
signal terminal1 : sl;
signal terminal2 : sl;
+ signal PCHold : slv(15 downto 0);
+ signal retI : sl;
+
+ -- Memory MUX signals
+ signal memAddr : slv(15 downto 0);
+ signal bankEn : slv(7 downto 0);
+ signal memDriveEn : sl;
+ signal xMemEn : sl;
+ signal immMemEn : sl;
+ -- Instruction/Immediate register signals
signal instReg : slv(7 downto 0);
signal immEn : sl;
signal immDriveEn : sl;
signal immReg : slv(7 downto 0);
+ -- ALU and Accumulator signals
signal aluOp : slv(4 downto 0);
signal aluData : slv(7 downto 0);
signal aluCarry : sl;
@@ -61,6 +76,7 @@ architecture ttl of cpu is
signal acLoad : sl;
signal acDriveEn : sl;
+ -- Y regsiter signals
signal yReg : slv(7 downto 0) := x"00";
signal yLoad : sl;
signal yDriven : sl;
@@ -68,44 +84,34 @@ architecture ttl of cpu is
signal yBusDriveEn : sl;
signal yBufDriveEn : sl;
+ -- X register signals
signal xReg : slv(7 downto 0) := x"00";
signal xCount : sl;
signal xLoad : sl;
signal xTermLo : sl;
+ signal interrupt : sl;
+ -- Video register signals
signal vidLoad : sl;
signal vidReg : slv(7 downto 0) := x"00";
- signal PCReg : slv(15 downto 0);
- signal mauEnLo : sl;
- signal mauEnHi : sl;
- signal mauSel : sl;
- signal mauDisableLo : sl;
- signal memAddr : slv(15 downto 0);
- signal bankEn : slv(7 downto 0);
- signal memDriveEn : sl;
-
+ -- Databus signals
signal dataRom : slv(7 downto 0);
signal ramWrN : sl;
signal dataRam : slv(7 downto 0);
signal dataRamDef : slv(7 downto 0);
signal dataBus : slv(7 downto 0);
-
- signal interrupt : sl;
- signal PCHold : slv(15 downto 0);
-
- signal retI : sl;
+ -- Peripheral signals
signal keyArray : slv(7 downto 0);
signal audioReg : slv(7 downto 0);
-
- signal xMemEn : sl;
- signal immMemEn : sl;
begin
rstN <= not iRst;
-
+ sysClk <= iClk after 10 ns;
+ wrClk <= iClk or sysClk;
+
----------------------------------------------------------
------ State Machine -------
----------------------------------------------------------
@@ -123,7 +129,7 @@ begin
-- State machine (shifter)
stateComp : entity work.sn74hct299(rtl)
- port map(clkIn => iClk,
+ port map(clkIn => sysClk,
rstNIn => '1',
modeSIn => stateOp,
serial0In => stateN(2),
@@ -139,44 +145,43 @@ begin
----------------------------------------------------------
------ Program Counter -------
----------------------------------------------------------
- pcClear <= '0' when (rstN='0') or (((interrupt='1') and (execute='0') and iClk='0')) else '1';
- pcCount <= execute;
+ pcClear <= '0' when (rstN='0') or (((interrupt='1') and (execute='0') and sysClk='0')) else '1';
pc0: entity work.sn74hct161
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iRstN => pcClear,
iLoadN => pcLoadLo, -- load PC when we jump or return from interrupt
- iCntEn => pcCount,
+ iCntEn => execute,
iTCntEn => '1',
iData => dataBus(3 downto 0),
oData => pcReg(3 downto 0),
oTerminal => terminal0);
pc1: entity work.sn74hct161
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iRstN => pcClear,
iLoadN => pcLoadLo,
- iCntEn => pcCount,
+ iCntEn => execute,
iTCntEn => terminal0,
iData => dataBus(7 downto 4),
oData => pcReg(7 downto 4),
oTerminal => terminal1);
pc2: entity work.sn74hct161
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iRstN => pcClear,
iLoadN => pcLoadHi,
- iCntEn => pcCount,
+ iCntEn => execute,
iTCntEn => terminal1,
iData => yBus(3 downto 0),
oData => pcReg(11 downto 8),
oTerminal => terminal2);
pc3: entity work.sn74hct161
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iRstN => pcClear,
iLoadN => pcLoadHi,
- iCntEn => pcCount,
+ iCntEn => execute,
iTCntEn => terminal2,
iData => yBus(7 downto 4),
oData => pcReg(15 downto 12),
@@ -185,14 +190,12 @@ begin
----------------------------------------------------------
------ Memory Address Selector -------
----------------------------------------------------------
- -- EnHi EnLo Sel Memory access
- -- 0 0 0 [ Ybus, Xbus] -- normal memory access
- -- 0 0 1 [PC,PC] -- fetch
+ -- Sel Memory access
+ -- 0 [ Ybus, Xbus] -- normal memory access
+ -- 1 [PC,PC] -- fetch
-- Ybus can be either Y register or 0x80
-- Xbus can be either X register or D register
- mauSel <= execute; -- only 1 during program counter access
-
mau0 : entity work.sn74hct244 -- tristate buffer
port map( iEnAN => immMemEn,
iEnBN => immMemEn,
@@ -217,14 +220,14 @@ begin
port map( iA => To_X01(yBus(3 downto 0)),
iB => pcReg(11 downto 8),
iEnableN => '0',
- iSelect => mauSel,
+ iSelect => execute,
oY => memAddr(11 downto 8));
mau4 : entity work.sn74hct157
port map( iA => To_X01(yBus(7 downto 4)),
iB => pcReg(15 downto 12),
iEnableN => '0',
- iSelect => mauSel,
+ iSelect => execute,
oY => memAddr(15 downto 12));
----------------------------------------------------------
@@ -280,7 +283,7 @@ begin
------ Instruction Register -------
----------------------------------------------------------
instComp : entity work.sn74hct377 -- FF with load enable
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iLoadN => instFetch,
iData => dataBus,
oData => instReg);
@@ -289,7 +292,8 @@ begin
------ Instruction Decoder -------
----------------------------------------------------------
controlComp: entity work.control
- port map( iClk => iClk,
+ port map( iClk => sysClk,
+ iWrClk => wrClk,
iInst => instReg,
iCarry => aluCarry,
iSign => acReg(7),
@@ -317,7 +321,7 @@ begin
------ Immediate Data Register -------
----------------------------------------------------------
immeComp : entity work.sn74hct377 -- FF with tristate output
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iLoadN => immFetch,
iData => dataBus,
oData => immReg);
@@ -342,7 +346,7 @@ begin
------ Accumulator Register and Buffer -------
----------------------------------------------------------
accComp : entity work.sn74hct377 -- FF with load enable
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iLoadN => acLoad,
iData => aluData,
oData => acReg);
@@ -373,7 +377,7 @@ begin
------ X Register -------
----------------------------------------------------------
xLoComp: entity work.sn74hct161
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iRstN => rstN,
iLoadN => xLoad,
iCntEn => xCount,
@@ -383,7 +387,7 @@ begin
oTerminal => xTermLo);
xHiComp: entity work.sn74hct161
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iRstN => rstN,
iLoadN => xLoad,
iCntEn => xCount,
@@ -396,7 +400,7 @@ begin
------ Video Register -------
----------------------------------------------------------
vidComp : entity work.sn74hct377 -- FF with load enable
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iLoadN => vidLoad,
iData => aluData,
oData => vidReg);
@@ -442,7 +446,7 @@ begin
-- Ground is second ring
-- Mic is sleeve. Maybe have jumpers to select second audio input connector, or from mic sleeve.
audioComp : entity work.sn74hct377 -- FF with load enable
- port map( iClk => iClk,
+ port map( iClk => sysClk,
iLoadN => (bankEn(4) and ramWrN),
iData => acReg,
oData => audioReg);
diff --git a/src/hdl/rom_synth.vhd b/src/hdl/rom_synth.vhd
index 509dcdd..e5a1624 100644
--- a/src/hdl/rom_synth.vhd
+++ b/src/hdl/rom_synth.vhd
@@ -33,37 +33,44 @@ architecture rtl of rom_synth is
type rom_type is array (0 to (2**iAddr'length)-1) of std_logic_vector(oData'range);
signal rom : rom_type := (
- 0 =>x"C2", 1=>x"00", -- st [80,D] AC-- store AC to 0x8000-- save register states
- 2 =>x"C3", 3=>x"01", -- st [80,D] Y-- store Y to 0x8001
- 4 =>x"10", 5=>x"38", -- ld X D-- Set X to 0x55--reload timer
- 6 =>x"01", 7=>x"03", -- ld [80,D] MEM-- Load BOOTCNT--check if booting finished
- 8 =>x"60", 9=>x"37", -- xor AC D--XOR compare 55 with BOOTCNT
- 10 =>x"EC", 11=>x"2E", -- bne 0 D-- branch to BOOT_VECTOR if not equal
- 12 =>x"00", 13=>x"00", -- ld AC D-- clear registers-- VIDEO_HANDLER
- 14 =>x"14", 15=>x"00", -- ld y D
- 16 =>x"01", 17=>x"00", -- ld [80,D],AC MEM--load AC--restore registers
- 18 =>x"15", 19=>x"01", -- ld [80,D],Y MEM-- load Y
- 20 =>x"E3", 21=>x"00", -- reti 0 0-- return from interrupt
- 22 =>x"02", 23=>x"00", -- nop 0 0
- 24 =>x"02", 25=>x"00", -- nop 0 0
- 26 =>x"02", 27=>x"00", -- nop 0 0
- 28 =>x"02", 29=>x"00", -- nop 0 0
- 30 =>x"02", 31=>x"00", -- nop 0 0
- 32 =>x"02", 33=>x"00", -- nop 0 0
- 34 =>x"02", 35=>x"00", -- nop 0 0
- 36 =>x"02", 37=>x"00", -- nop 0 0
- 38 =>x"02", 39=>x"00", -- nop 0 0
- 40 =>x"02", 41=>x"00", -- nop 0 0
- 42 =>x"02", 43=>x"00", -- nop 0 0
- 44 =>x"02", 45=>x"00", -- nop 0 0
- 46 =>x"00", 47=>x"37", -- ld AC D-- BOOT_VECTOR
- 48 =>x"C2", 49=>x"03", -- st [80,D] AC-- store 55 to BOOTCNT
- 50 =>x"00", 51=>x"00", -- ld AC D--initialize AC with 0-- main test program:store value to memory, load it back, add to it, repeat
- 52 =>x"C2", 53=>x"04", -- st [80,D] AC--store value-- MAIN_LOOP
- 54 =>x"01", 55=>x"04", -- ld [80,D] MEM--load value
- 56 =>x"80", 57=>x"01", -- add AC D--add 1
- 58 =>x"1A", 59=>x"00", -- ld VID AC-- copy result to VID output incrementing X for testing
- 60 =>x"FC", 61=>x"34", -- bra 0 D-- branch back to MAIN_LOOP
+ 0 =>x"C2",
+ 1 =>x"00",
+ 2 =>x"C3",
+ 3 =>x"01",
+ 4 =>x"10",
+ 5 =>x"38",
+ 6 =>x"01",
+ 7 =>x"03",
+ 8 =>x"60",
+ 9 =>x"37",
+ 10 =>x"EC",
+ 11 =>x"16",
+ 12 =>x"00",
+ 13 =>x"00",
+ 14 =>x"14",
+ 15 =>x"00",
+ 16 =>x"01",
+ 17 =>x"00",
+ 18 =>x"15",
+ 19 =>x"01",
+ 20 =>x"E3",
+ 21 =>x"00",
+ 22 =>x"00",
+ 23 =>x"37",
+ 24 =>x"C2",
+ 25 =>x"03",
+ 26 =>x"00",
+ 27 =>x"00",
+ 28 =>x"C2",
+ 29 =>x"04",
+ 30 =>x"01",
+ 31 =>x"04",
+ 32 =>x"80",
+ 33 =>x"01",
+ 34 =>x"1A",
+ 35 =>x"00",
+ 36 =>x"FC",
+ 37 =>x"1C",
----------------------------------------------------------
------ X Lookup Table -------
diff --git a/src/sim/tb_basys_demo_behav.wcfg b/src/sim/tb_basys_demo_behav.wcfg
index 59f67b8..d188169 100644
--- a/src/sim/tb_basys_demo_behav.wcfg
+++ b/src/sim/tb_basys_demo_behav.wcfg
@@ -13,15 +13,18 @@
-
-
-
+
+
+
-
+
-
+
+
+
+
clkSys
clkSys
@@ -30,6 +33,14 @@
iClk
iClk
+
+ sysClk
+ sysClk
+
+
+ wrClk
+ wrClk
+
iRst
iRst
@@ -54,10 +65,6 @@
PCReg[15:0]
PCReg[15:0]
-
- mauSel
- mauSel
-
memAddr[15:0]
memAddr[15:0]