From d5b9e4f2b93c995f8141337611322cb14a8d7af1 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Fri, 20 Dec 2024 17:05:47 -0500 Subject: [PATCH 01/14] Change interrupt polarity to eliminate gates --- src/hdl/control.vhd | 10 ++++------ src/hdl/cpu.vhd | 19 ++++--------------- src/sim/tb_basys_demo_behav.wcfg | 14 +++++++++----- 3 files changed, 17 insertions(+), 26 deletions(-) diff --git a/src/hdl/control.vhd b/src/hdl/control.vhd index d0f4331..e079255 100644 --- a/src/hdl/control.vhd +++ b/src/hdl/control.vhd @@ -68,9 +68,9 @@ begin ------ Operation decoding ------- ---------------------------------------------------------- operationDecoderComp : entity work.sn74hct138 - port map( iEn => iInterrupt, + port map( iEn => '1', iEnLo0 => iExecute, - iEnLo1 => '0', + iEnLo1 => iInterrupt, iA => iInst(5), iB => iInst(6), iC => iInst(7), @@ -114,12 +114,10 @@ begin -- 110- [80,X] , VID -- 111- [ Y,X++] , VID - modeEn <= operation(7) and iInterrupt; - modeDecoderComp : entity work.sn74hct138 - port map( iEn => modeEn, -- disable during Bcc iInterrupt + port map( iEn => operation(7), -- disable during Bcc iInterrupt iEnLo0 => iExecute, - iEnLo1 => '0', + iEnLo1 => iInterrupt, iA => iInst(2), iB => iInst(3), iC => iInst(4), diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd index edada3e..61fdbc1 100644 --- a/src/hdl/cpu.vhd +++ b/src/hdl/cpu.vhd @@ -109,7 +109,7 @@ begin rstN <= not iRst; - pcClear <= '0' when (iRst='1') or ((interrupt='0') and (execute='0')) else '1'; + pcClear <= '0' when (iRst='1') or ((interrupt='1') and (execute='0')) else '1'; ---------------------------------------------------------- ------ State Machine ------- ---------------------------------------------------------- @@ -419,25 +419,14 @@ begin oData => timerReg(7 downto 4), oTerminal => timerTC); - interrupt <= not timerTC; + interrupt <= timerTC; dataBus <= timerReg when ((bankEn(4)='0') and (memDriveEn='0')) else "ZZZZZZZZ"; ---------------------------------------------------------- ------ Interrupt Enable Register ------- ---------------------------------------------------------- - -- intStateProc: process (iClk) - -- begin - -- if (rising_edge(iClk)) then - -- if (interrupt='0') then - -- intEn <= '1'; -- after reset, interrupts disabled - -- elsif (retI='0') then - -- intEn <= '0'; -- after reti, interrupts enabled - -- end if; - -- end if; - -- end process intStateProc; - - intEnNext <= '1' when (interrupt='0') or ((intEn='1') and (retI='1')) else '0'; - + intEnNext <= '1' when (interrupt='1') or ((intEn='1') and (retI='1')) else '0'; + intStateComp : entity work.sn74hct74 port map( iClk => iClk, iRstN => '1', diff --git a/src/sim/tb_basys_demo_behav.wcfg b/src/sim/tb_basys_demo_behav.wcfg index e4ebc84..7267da8 100644 --- a/src/sim/tb_basys_demo_behav.wcfg +++ b/src/sim/tb_basys_demo_behav.wcfg @@ -13,15 +13,15 @@ - - - + + + - + - + clkSys clkSys @@ -226,6 +226,10 @@ interrupt interrupt + + oTerminal + oTerminal + intEn intEn From 8ab256ce5ea1811ebc7600e25dba3681ec77d1e9 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Mon, 23 Dec 2024 17:05:09 -0500 Subject: [PATCH 02/14] Replace timer buffer with chip --- src/hdl/cpu.vhd | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd index 61fdbc1..163168c 100644 --- a/src/hdl/cpu.vhd +++ b/src/hdl/cpu.vhd @@ -95,6 +95,7 @@ architecture ttl of cpu is signal timerTermLo : sl; signal timerReg : slv(7 downto 0) := x"00"; signal timerTC : sl; + signal timerDriveEn : sl; signal interrupt : sl; signal intEn : sl := '1'; signal intClear : sl; @@ -237,10 +238,10 @@ begin -- $8000-$FFFF RAM (32k) -- decoder divider addresses into: - -- $0000-$1FFF ROM - -- $1000-$2FFF ROM - -- $2000-$3FFF ROM - -- $3000-$4FFF ROM + -- $0000-$0FFF ROM + -- $1000-$1FFF ROM + -- $2000-$2FFF ROM + -- $3000-$3FFF ROM -- $4000-$4FFF Timer -- $5000-$5FFF I/O - shift register for controller? keyboard? -- $6000-$6FFF Expansion 1 @@ -420,7 +421,14 @@ begin oTerminal => timerTC); interrupt <= timerTC; - dataBus <= timerReg when ((bankEn(4)='0') and (memDriveEn='0')) else "ZZZZZZZZ"; + + -- Driving the timer to the databus may not be needed to save a chip + timerDriveEn <= '0 when ((bankEn(4)='0') and (memDriveEn='0')) else '1'; + timerBufComp : entity work.sn74hct244 -- tristate buffer + port map( iEnAN => timerDriveEn, + iEnBN => timerDriveEn, + iData => timerReg, + oData => dataBus); ---------------------------------------------------------- ------ Interrupt Enable Register ------- From 39e786aa4f50b1ec7a72b66fb2e1c7239219ba18 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Fri, 27 Dec 2024 17:33:49 -0500 Subject: [PATCH 03/14] switch interrupt to J/K FF to remove logic gates. swap data bus access modes (mem/AC) to match gigatron --- src/hdl/control.vhd | 14 ++------- src/hdl/cpu.vhd | 38 ++++++++++++----------- src/hdl/rom_synth.vhd | 28 ++++++++--------- src/hdl/sn74hct109.vhd | 69 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+), 44 deletions(-) create mode 100644 src/hdl/sn74hct109.vhd diff --git a/src/hdl/control.vhd b/src/hdl/control.vhd index e079255..22b24c8 100644 --- a/src/hdl/control.vhd +++ b/src/hdl/control.vhd @@ -104,16 +104,6 @@ begin ---------------------------------------------------------- ------ Memory MUX and Destination decoder ------- ---------------------------------------------------------- - -- IR4,3,2 - -- 000- [ Y,X] , AC - -- 001- [80,X] , AC - -- 010 [80,00] , AC - -- 011- [80,X] , X - -- 100- [80,X] , Y - -- 101 [ Y,00] , Y - -- 110- [80,X] , VID - -- 111- [ Y,X++] , VID - modeDecoderComp : entity work.sn74hct138 port map( iEn => operation(7), -- disable during Bcc iInterrupt iEnLo0 => iExecute, @@ -149,8 +139,8 @@ begin else '1'; oYBufDrive <= busSrc(3) when oPCLoadHi='1' else '1'; -- override during jump instruction - oMemDrive <= busSrc(2); - oAccDrive <= busSrc(1); + oAccDrive <= busSrc(2); + oMemDrive <= busSrc(1); oImmDrive <= busSrc(0); busDriveName <= " Y" when oYBufDrive='0' else diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd index 163168c..cea8276 100644 --- a/src/hdl/cpu.vhd +++ b/src/hdl/cpu.vhd @@ -84,6 +84,7 @@ architecture ttl of cpu is signal memAddr : slv(15 downto 0); signal bankEn : slv(7 downto 0); signal memDriveEn : sl; + signal memOn : sl; signal dataRom : slv(7 downto 0); signal ramWrN : sl; @@ -119,7 +120,7 @@ begin -- Second state: fetch Immediate Data -- enable PC counting, enable immediate register, set address MUX to PC -- Third state: execute - -- disable PC counting, set address MUX to execute + -- disable PC counting, set address MUX to instruction execution -- stateOp is 11 when loading (only on reset), 01 when shifting LSB to MSB stateOp(0) <= '1'; @@ -189,7 +190,6 @@ begin ---------------------------------------------------------- ------ Memory Address Selector ------- ---------------------------------------------------------- - -- En = 1 only for interrupt vector -- otherwise Sel = 0 for execute, 1 for fetch -- The only user mode is [Y,X] , but Y can also tristate for [80,X] @@ -197,9 +197,8 @@ begin -- 0 0 0 [ Y, X] -- normal memory access -- 0 0 1 [PC,PC] -- fetch -- 0 1 0 [ Y, 0] -- for restoring Y and AC - -- 1 1 X [00,00] -- interrupt vector - mauEnHi <= '0'; -- 1 during interrupt here - mauEnLo <= mauDisableLo; -- need to force to 1 during interrupt and during specific mode + mauEnHi <= '0'; + mauEnLo <= mauDisableLo; mauSel <= execute; -- only 1 during program counter access mau0 : entity work.sn74hct157 @@ -256,25 +255,29 @@ begin iC => memAddr(14), oY => bankEn(7 downto 0)); -- active low outputs + memOn <= instFetch and immFetch and memDriveEn; ---------------------------------------------------------- ------ ROM ------- ---------------------------------------------------------- romComp : entity work.rom_synth port map( iAddr => memAddr(13 downto 0), oData => dataRom); - dataBus <= dataRom when (and(bankEn(3 downto 0)) = '0') and ((memDriveEn='0') or (execute='1')) else "ZZZZZZZZ"; + -- CEn => and(bankEn(3 downto 0)) with diode and + -- OEn => memOn + dataBus <= dataRom when (and(bankEn(3 downto 0)) = '0') and (memOn='0') else "ZZZZZZZZ"; ---------------------------------------------------------- ------ RAM ------- ---------------------------------------------------------- ramComp : entity work.sp_ram_async port map( iWrEnN => ramWrN, - iRamEnN => '0', + iRamEnN => (not memAddr(15)), iAddr => memAddr(14 downto 0), iData => dataBus, oData => dataRam); + -- OEn => memOn dataRamDef <= "00000000" when dataRam="UUUUUUUU" else dataRam; -- fix for uninitialized RAM behavior - dataBus <= dataRamDef when (memAddr(15) = '1') and ((memDriveEn='0') or (execute='1')) else "ZZZZZZZZ"; + dataBus <= dataRamDef when (memAddr(15) = '1') and (memOn='0') else "ZZZZZZZZ"; ---------------------------------------------------------- ------ Instruction Register ------- @@ -385,7 +388,6 @@ begin oData => xReg(7 downto 4), oTerminal => open); - ---------------------------------------------------------- ------ Video Register ------- ---------------------------------------------------------- @@ -404,7 +406,7 @@ begin port map( iClk => iClk, iRstN => rstN, iLoadN => timerLoad, - iCntEn => (not execute), + iCntEn => (not execute), -- count once per instruction iTCntEn => '1', iData => dataBus(3 downto 0), oData => timerReg(3 downto 0), @@ -414,7 +416,7 @@ begin port map( iClk => iClk, iRstN => rstN, iLoadN => timerLoad, - iCntEn => (not execute), + iCntEn => (not execute), -- count once per instruction iTCntEn => timerTermLo, iData => dataBus(7 downto 4), oData => timerReg(7 downto 4), @@ -423,7 +425,8 @@ begin interrupt <= timerTC; -- Driving the timer to the databus may not be needed to save a chip - timerDriveEn <= '0 when ((bankEn(4)='0') and (memDriveEn='0')) else '1'; + timerDriveEn <= '0' when ((bankEn(4)='0') and (memDriveEn='0')) else '1'; -- could be memOn as well + timerBufComp : entity work.sn74hct244 -- tristate buffer port map( iEnAN => timerDriveEn, iEnBN => timerDriveEn, @@ -433,13 +436,12 @@ begin ---------------------------------------------------------- ------ Interrupt Enable Register ------- ---------------------------------------------------------- - intEnNext <= '1' when (interrupt='1') or ((intEn='1') and (retI='1')) else '0'; - - intStateComp : entity work.sn74hct74 + intStateComp : entity work.sn74hct109 port map( iClk => iClk, iRstN => '1', iSetN => rstN, - iD => intEnNext, + iJ => interrupt, -- set on interrupt (active high) + iKN => retI, -- reset on retI (active low) oQ => intEn, oQN => open); @@ -449,13 +451,13 @@ begin intEnClk <= iClk or intEn; pcHoldHiComp : entity work.sn74hct574 -- FF with tristate output - port map( iClk => intEnClk, -- can't just be intEn. won't clock every clock. maybe OR with clock? + port map( iClk => intEnClk, iEnN => retI, iData => pcReg(15 downto 8), oData => yBus); pcHoldLoComp : entity work.sn74hct574 -- FF with tristate output - port map( iClk => intEnClk, -- can't just be intEn. won't clock every clock. maybe OR with clock? + port map( iClk => intEnClk, iEnN => retI, iData => pcReg(7 downto 0), oData => dataBus); diff --git a/src/hdl/rom_synth.vhd b/src/hdl/rom_synth.vhd index bb2bf2f..392afac 100644 --- a/src/hdl/rom_synth.vhd +++ b/src/hdl/rom_synth.vhd @@ -33,44 +33,44 @@ architecture rtl of rom_synth is type rom_type is array (0 to (2**iAddr'length)-1) of std_logic_vector(oData'range); signal rom : rom_type := ( - 0 =>x"C9", 1=>x"00", -- st [80,00],AC AC-- store AC to 0x8000 + 0 =>x"CA", 1=>x"00", -- st [80,00],AC AC-- store AC to 0x8000 2 =>x"07", 3=>x"00", -- ld [Y,X],AC Y 4 =>x"10", 5=>x"81", -- ld [80,X],Y D - 6 =>x"D5", 7=>x"00", -- st [Y,00],Y AC-- store Y to 0x8100 + 6 =>x"D6", 7=>x"00", -- st [Y,00],Y AC-- store Y to 0x8100 8 =>x"10", 9=>x"3F", -- ld [80,X],Y D - 10 =>x"06", 11=>x"00", -- ld [Y,X],AC MEM-- load from ROM table at 0x3F00-3FFF + 10 =>x"05", 11=>x"00", -- ld [Y,X],AC MEM-- load from ROM table at 0x3F00-3FFF 12 =>x"0C", 13=>x"05", -- ld [80,X],X D - 14 =>x"C1", 15=>x"00", -- st [80,X],AC AC-- store X to 0x8005 + 14 =>x"C2", 15=>x"00", -- st [80,X],AC AC-- store X to 0x8005 16 =>x"10", 17=>x"40", -- ld [80,X],Y D-- Set Y to 0x4000 18 =>x"C4", 19=>x"38", -- st [Y,X],AC D-- Load timer with 200 20 =>x"0C", 21=>x"01", -- ld [80,X],X D--Load X with BOOTCNT (0x01) 22 =>x"00", 23=>x"37", -- ld [80,X],AC D--Load AC with 55 - 24 =>x"62", 25=>x"00", -- xor [80,X],AC MEM--XOR compare 55 with 0x8001 + 24 =>x"61", 25=>x"00", -- xor [80,X],AC MEM--XOR compare 55 with 0x8001 26 =>x"F0", 27=>x"28", -- beq 0 D--branch if equal 28 =>x"00", 29=>x"01", -- ld [80,X],AC D-- load AC with x01 - 30 =>x"62", 31=>x"00", -- xor [80,X],AC MEM--XOR compare x01 with 0x8001 + 30 =>x"61", 31=>x"00", -- xor [80,X],AC MEM--XOR compare x01 with 0x8001 32 =>x"F0", 33=>x"3A", -- beq 0 D-- branch if equal 34 =>x"00", 35=>x"01", -- ld [80,X],AC D - 36 =>x"C1", 37=>x"00", -- st [80,X],AC AC--store 0x01 to BOOTCNT + 36 =>x"C2", 37=>x"00", -- st [80,X],AC AC--store 0x01 to BOOTCNT 38 =>x"E3", 39=>x"00", -- reti 0 0-- reti to set interrupt enbale 40 =>x"00", 41=>x"00", -- ld [80,X],AC D-- clear registers-- temporary video handler vector 42 =>x"0C", 43=>x"00", -- ld [80,X],X D 44 =>x"10", 45=>x"00", -- ld [80,X],Y D-- restore registers from memory 46 =>x"10", 47=>x"81", -- ld [80,X],Y D-- load Y from 0x8100 - 48 =>x"16", 49=>x"00", -- ld [Y,00],Y MEM + 48 =>x"15", 49=>x"00", -- ld [Y,00],Y MEM 50 =>x"0C", 51=>x"05", -- ld [80,X],X D-- load X from 0x8005 - 52 =>x"0E", 53=>x"00", -- ld [80,X],X MEM - 54 =>x"0A", 55=>x"00", -- ld [80,00],AC MEM-- load AC from 0x8000 + 52 =>x"0D", 53=>x"00", -- ld [80,X],X MEM + 54 =>x"09", 55=>x"00", -- ld [80,00],AC MEM-- load AC from 0x8000 56 =>x"E3", 57=>x"00", -- reti 0 0 58 =>x"00", 59=>x"37", -- ld [80,X],AC D-- load BOOTCNT with 55-- temporary cold boot vector - 60 =>x"C1", 61=>x"00", -- st [80,X],AC AC-- end of booting + 60 =>x"C2", 61=>x"00", -- st [80,X],AC AC-- end of booting 62 =>x"0C", 63=>x"32", -- ld [80,X],X D-- test program:store value to memory, load it back, add to it, repeat 64 =>x"00", 65=>x"00", -- ld [80,X],AC D--initialize AC with 0 - 66 =>x"C1", 67=>x"00", -- st [80,X],AC AC--store value - 68 =>x"02", 69=>x"00", -- ld [80,X],AC MEM--load value + 66 =>x"C2", 67=>x"00", -- st [80,X],AC AC--store value + 68 =>x"01", 69=>x"00", -- ld [80,X],AC MEM--load value 70 =>x"80", 71=>x"01", -- add [80,X],AC D--add 1 72 =>x"10", 73=>x"80", -- ld [80,X],Y D-- setup Y for memory addressing - 74 =>x"1D", 75=>x"00", -- ld [Y,X++],VID AC-- load result to VID output incrementing X for testing + 74 =>x"1E", 75=>x"00", -- ld [Y,X++],VID AC-- load result to VID output incrementing X for testing 76 =>x"0C", 77=>x"32", -- ld [80,X],X D-- reload X 78 =>x"FC", 79=>x"42", -- bra 0 D-- branch back diff --git a/src/hdl/sn74hct109.vhd b/src/hdl/sn74hct109.vhd new file mode 100644 index 0000000..ef6221b --- /dev/null +++ b/src/hdl/sn74hct109.vhd @@ -0,0 +1,69 @@ +/* +-- @file sn74hct109.vhd +-- @brief Models the HCT109 chip - J/K FF +-- @author Justin Davis +-- + Copyright (C) 2024 Justin Davis + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU Affero General Public License as published + by the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Affero General Public License for more details. + + You should have received a copy of the GNU Affero General Public License + along with this program. If not, see . +------------------------------------------------------------------------------*/ +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; use work.tools_pkg.all; + use work.sys_description_pkg.all; + +entity sn74hct109 is + port( iClk : in sl; + iRstN : in sl; + iSetN : in sl; + iJ : in sl; + iKN : in sl; + oQ : out sl; + oQN : out sl); +end entity sn74hct109; + +architecture rtl of sn74hct109 is + + signal state : sl := '0'; + +begin + + -- J K Next state + -- 0 0 Reset + -- 0 1 Hold + -- 1 0 Toggle + -- 1 1 Set + + FFproc : process (iClk,iRstN,iSetN) + begin + if (iRstN='0') then + state <= '0'; + elsif (iSetN='0') then + state <= '1'; + elsif rising_edge(iClk) then + if (iJ='1') and (iKN='0') then + state <= not state; + elsif (iJ='1') then + state <= '1'; + elsif (iKN = '0') then + state <= '0'; + end if; + end if; + end process FFproc; + + oQ <= state; + oQN <= not state; + +end architecture rtl; From af44318b07201980c411057457c23abbf0395bb6 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Sun, 29 Dec 2024 21:49:51 -0500 Subject: [PATCH 04/14] push control for memory enable into control block --- src/hdl/control.vhd | 2 +- src/hdl/cpu.vhd | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/src/hdl/control.vhd b/src/hdl/control.vhd index 22b24c8..ef95dbb 100644 --- a/src/hdl/control.vhd +++ b/src/hdl/control.vhd @@ -140,7 +140,7 @@ begin oYBufDrive <= busSrc(3) when oPCLoadHi='1' else '1'; -- override during jump instruction oAccDrive <= busSrc(2); - oMemDrive <= busSrc(1); + oMemDrive <= busSrc(1) when iExecute='0' else '0'; -- instFetch and immFetch states always enable memory output oImmDrive <= busSrc(0); busDriveName <= " Y" when oYBufDrive='0' else diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd index cea8276..fb70810 100644 --- a/src/hdl/cpu.vhd +++ b/src/hdl/cpu.vhd @@ -41,7 +41,6 @@ architecture ttl of cpu is signal immFetch : sl; signal execute : sl; signal pcClear : sl; - signal loadPC : sl; signal pcCount : sl; signal pcLoadLo : sl; signal pcLoadHi : sl; @@ -84,7 +83,6 @@ architecture ttl of cpu is signal memAddr : slv(15 downto 0); signal bankEn : slv(7 downto 0); signal memDriveEn : sl; - signal memOn : sl; signal dataRom : slv(7 downto 0); signal ramWrN : sl; @@ -111,7 +109,6 @@ begin rstN <= not iRst; - pcClear <= '0' when (iRst='1') or ((interrupt='1') and (execute='0')) else '1'; ---------------------------------------------------------- ------ State Machine ------- ---------------------------------------------------------- @@ -142,11 +139,12 @@ begin immFetch <= stateN(1); execute <= stateN(2); - pcCount <= execute; - loadPC <= '1'; ---------------------------------------------------------- ------ Program Counter ------- ---------------------------------------------------------- + pcClear <= '0' when (rstN='0') or ((interrupt='1') and (execute='0')) else '1'; + pcCount <= execute; + pc0: entity work.sn74hct161 port map( iClk => iClk, iRstN => pcClear, @@ -255,7 +253,6 @@ begin iC => memAddr(14), oY => bankEn(7 downto 0)); -- active low outputs - memOn <= instFetch and immFetch and memDriveEn; ---------------------------------------------------------- ------ ROM ------- ---------------------------------------------------------- @@ -264,7 +261,7 @@ begin oData => dataRom); -- CEn => and(bankEn(3 downto 0)) with diode and -- OEn => memOn - dataBus <= dataRom when (and(bankEn(3 downto 0)) = '0') and (memOn='0') else "ZZZZZZZZ"; + dataBus <= dataRom when (and(bankEn(3 downto 0)) = '0') and (memDriveEn='0') else "ZZZZZZZZ"; ---------------------------------------------------------- ------ RAM ------- @@ -277,7 +274,7 @@ begin oData => dataRam); -- OEn => memOn dataRamDef <= "00000000" when dataRam="UUUUUUUU" else dataRam; -- fix for uninitialized RAM behavior - dataBus <= dataRamDef when (memAddr(15) = '1') and (memOn='0') else "ZZZZZZZZ"; + dataBus <= dataRamDef when (memAddr(15) = '1') and (memDriveEn='0') else "ZZZZZZZZ"; ---------------------------------------------------------- ------ Instruction Register ------- @@ -425,7 +422,7 @@ begin interrupt <= timerTC; -- Driving the timer to the databus may not be needed to save a chip - timerDriveEn <= '0' when ((bankEn(4)='0') and (memDriveEn='0')) else '1'; -- could be memOn as well + timerDriveEn <= '0' when ((bankEn(4)='0') and (memDriveEn='0')) else '1'; timerBufComp : entity work.sn74hct244 -- tristate buffer port map( iEnAN => timerDriveEn, From ab8e96e2d175618b8295d62c341345687b3ee90d Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Sun, 29 Dec 2024 21:50:55 -0500 Subject: [PATCH 05/14] Add PCB files --- pcb/gtxl/ALU.kicad_sch | 8013 +++++++++++++++++++++++++++++++ pcb/gtxl/MAU.kicad_sch | 5343 +++++++++++++++++++++ pcb/gtxl/MEM.kicad_sch | 5568 ++++++++++++++++++++++ pcb/gtxl/PC.kicad_sch | 6376 +++++++++++++++++++++++++ pcb/gtxl/REGS.kicad_sch | 9781 ++++++++++++++++++++++++++++++++++++++ pcb/gtxl/STATE.kicad_sch | 5649 ++++++++++++++++++++++ pcb/gtxl/TIMER.kicad_sch | 4514 ++++++++++++++++++ pcb/gtxl/gtxl.kicad_pcb | 2 + pcb/gtxl/gtxl.kicad_pro | 612 +++ pcb/gtxl/gtxl.kicad_sch | 279 ++ 10 files changed, 46137 insertions(+) create mode 100644 pcb/gtxl/ALU.kicad_sch create mode 100644 pcb/gtxl/MAU.kicad_sch create mode 100644 pcb/gtxl/MEM.kicad_sch create mode 100644 pcb/gtxl/PC.kicad_sch create mode 100644 pcb/gtxl/REGS.kicad_sch create mode 100644 pcb/gtxl/STATE.kicad_sch create mode 100644 pcb/gtxl/TIMER.kicad_sch create mode 100644 pcb/gtxl/gtxl.kicad_pcb create mode 100644 pcb/gtxl/gtxl.kicad_pro create mode 100644 pcb/gtxl/gtxl.kicad_sch diff --git a/pcb/gtxl/ALU.kicad_sch b/pcb/gtxl/ALU.kicad_sch new file mode 100644 index 0000000..9bf6ec1 --- /dev/null +++ b/pcb/gtxl/ALU.kicad_sch @@ -0,0 +1,8013 @@ +(kicad_sch + (version 20231120) + (generator "eeschema") + (generator_version "8.0") + (uuid "4f4fd7af-7e35-463d-9c82-5378184285ae") + (paper "B") + (lib_symbols + (symbol "74xx:74LS153" + (pin_names + (offset 1.016) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "U" + (at -7.62 21.59 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "74LS153" + (at -7.62 -24.13 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "http://www.ti.com/lit/gpn/sn74LS153" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Dual Multiplexer 4 to 1" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_locked" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "ki_keywords" "TTL Mux4" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_fp_filters" "DIP?16*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) 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"cc03b095-3dfc-4266-bd94-b97941070679") + (property "Sheetname" "ALU" + (at 158.115 168.1984 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + ) + (property "Sheetfile" "ALU.kicad_sch" + (at 158.115 185.3696 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + ) + (instances + (project "gtxl" + (path "/2dd80149-0e94-4467-bb5a-52cd819c450a" + (page "8") + ) + ) + ) + ) + (sheet + (at 110.49 170.815) + (size 31.75 15.24) + (fields_autoplaced yes) + (stroke + (width 0.1524) + (type solid) + ) + (fill + (color 0 0 0 0.0000) + ) + (uuid "cd1db4eb-8be3-4e84-92f5-edf1d9781240") + (property "Sheetname" "Registers" + (at 110.49 170.1034 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + ) + (property "Sheetfile" "REGS.kicad_sch" + (at 110.49 186.6396 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + ) + (instances + (project "gtxl" + (path "/2dd80149-0e94-4467-bb5a-52cd819c450a" + (page "6") + ) + ) + ) + ) + (sheet + (at 46.99 145.415) + (size 36.83 14.605) + (fields_autoplaced yes) + (stroke + (width 0.1524) + (type solid) + ) + (fill + (color 0 0 0 0.0000) + ) + (uuid "cfc3f233-b18f-4fff-833a-4cc277cf255e") + (property "Sheetname" "Program Counter" + (at 46.99 144.7034 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + ) + (property "Sheetfile" "PC.kicad_sch" + (at 46.99 160.6046 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + ) + (instances + (project "gtxl" + (path "/2dd80149-0e94-4467-bb5a-52cd819c450a" + (page "2") + ) + ) + ) + ) + (sheet_instances + (path "/" + (page "1") + ) + ) +) From c401420912ff644496db0daa03000627333bda63 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Mon, 30 Dec 2024 17:00:53 -0500 Subject: [PATCH 06/14] Add keyboard and audio blocks --- project/gtxl.xpr | 14 ++++++++---- resources/Assembly.xlsx | Bin 56364 -> 56315 bytes src/hdl/cpu.vhd | 38 ++++++++++++++++++++++++++++--- src/sim/tb_basys_demo_behav.wcfg | 17 +++++++------- 4 files changed, 54 insertions(+), 15 deletions(-) diff --git a/project/gtxl.xpr b/project/gtxl.xpr index 1f064b1..d093004 100644 --- a/project/gtxl.xpr +++ b/project/gtxl.xpr @@ -44,7 +44,7 @@ - - loadPC - loadPC - PCReg[15:0] PCReg[15:0] @@ -69,6 +65,7 @@ bankEn[7:0] bankEn[7:0] + dataRom[7:0] @@ -218,6 +215,10 @@ timerTC timerTC + + timerLoad + timerLoad + rstN rstN From cc2cf089903070b446eecc80a97a2ade6c277980 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Tue, 31 Dec 2024 17:02:33 -0500 Subject: [PATCH 07/14] Reorganize some control assignments. improve formatting. --- src/hdl/control.vhd | 50 ++++++++++++++++++------------------- src/hdl/cpu.vhd | 61 +++++++++++++++++++++++---------------------- 2 files changed, 56 insertions(+), 55 deletions(-) diff --git a/src/hdl/control.vhd b/src/hdl/control.vhd index ef95dbb..9eecbc5 100644 --- a/src/hdl/control.vhd +++ b/src/hdl/control.vhd @@ -113,8 +113,8 @@ begin iC => iInst(4), oY => mode); - modeName <= "[80,X] , AC" when mode="11111110" else --Y Bus on - "[ Y,X] , AC" when mode="11111101" else --Y Bus off + modeName <= "[80,X] , AC" when mode="11111110" else --Y Bus off + "[ Y,X] , AC" when mode="11111101" else --Y Bus on "[80,00] , AC" when mode="11111011" else --Y Bus off "[80,X] , X" when mode="11110111" else --Y Bus off "[80,X] , Y" when mode="11101111" else --Y Bus off @@ -123,14 +123,6 @@ begin "[ Y,X++],VID" when mode="01111111" else --Y Bus on "Disabled,Bcc" when mode="11111111" else "ERROR ,ERR"; - - ---------------------------------------------------------- - ------ Data Bus Source Selector ------- - ---------------------------------------------------------- - sourceBus : entity work.sn74hct139 - port map( iEnN => iExecute, - iData => iInst(1 downto 0), - oData => busSrc); oYBusDrive <= '0' when (modeName="[ Y,X] , AC" or modeName="[ Y,00] , Y" @@ -138,21 +130,6 @@ begin and oRetI='1' else '1'; - oYBufDrive <= busSrc(3) when oPCLoadHi='1' else '1'; -- override during jump instruction - oAccDrive <= busSrc(2); - oMemDrive <= busSrc(1) when iExecute='0' else '0'; -- instFetch and immFetch states always enable memory output - oImmDrive <= busSrc(0); - - busDriveName <= " Y" when oYBufDrive='0' else - " MEM" when oMemDrive='0' else - " AC" when oAccDrive='0' else - " D" when oImmDrive='0' else - " off" when busSrc="0000" else - " ERR"; - - fullName <= opName & modeName(1 to 8) & modeName(9 to 12) when busDriveName = " MEM" else - opName & busDriveName & modeName(9 to 12); - oXLoad <= '0' when modeName="[80,X] , X" else '1'; oYLoad <= '0' when modeName="[80,X] , Y" or @@ -170,6 +147,29 @@ begin oMauLoDis <= '1' when modeName="[80,00] , AC" or modeName="[ Y,00] , Y" else '0'; + ---------------------------------------------------------- + ------ Data Bus Source Selector ------- + ---------------------------------------------------------- + sourceBus : entity work.sn74hct139 + port map( iEnN => iExecute, + iData => iInst(1 downto 0), + oData => busSrc); + + oYBufDrive <= busSrc(3) when oPCLoadHi='1' else '1'; -- override during jump instruction + oAccDrive <= busSrc(2); + oMemDrive <= busSrc(1) when iExecute='0' else '0'; -- instFetch and immFetch states always enable memory output + oImmDrive <= busSrc(0); + + busDriveName <= " Y" when oYBufDrive='0' else + " MEM" when oMemDrive='0' else + " AC" when oAccDrive='0' else + " D" when oImmDrive='0' else + " off" when busSrc="0000" else + " ERR"; + + fullName <= opName & modeName(1 to 8) & modeName(9 to 12) when busDriveName = " MEM" else + opName & busDriveName & modeName(9 to 12); + oRamWrN <= '0' when (iClk='0') and (opName=" ST") and (oMemDrive='1') else '1'; ---------------------------------------------------------- diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd index 8959ead..11f6f3c 100644 --- a/src/hdl/cpu.vhd +++ b/src/hdl/cpu.vhd @@ -291,28 +291,28 @@ begin ------ Instruction Decoder ------- ---------------------------------------------------------- controlComp: entity work.control - port map( iClk => iClk, - iInst => instReg, - iCarry => aluCarry, - iSign => acReg(7), - iExecute => execute, - iInterrupt => interrupt, - oAluOp => aluOp, - oXLoad => xLoad, - oYLoad => yLoad, - oIncX => xCount, - oPCLoadLo => pcLoadLo, - oPCLoadHi => pcLoadHi, - oacLoad => acLoad, - oVidLoad => vidLoad, - oMemDrive => memDriveEn, - oImmDrive => immDriveEn, - oAccDrive => acDriveEn, - oYBusDrive => yBusDriveEn, - oYBufDrive => yBufDriveEn, - oRamWrN => ramWrN, - oMauLoDis => mauDisableLo, - oRetI => retI); + port map( iClk => iClk, + iInst => instReg, + iCarry => aluCarry, + iSign => acReg(7), + iExecute => execute, + iInterrupt => interrupt, + oAluOp => aluOp, + oXLoad => xLoad, + oYLoad => yLoad, + oIncX => xCount, + oPCLoadLo => pcLoadLo, + oPCLoadHi => pcLoadHi, + oacLoad => acLoad, + oVidLoad => vidLoad, + oMemDrive => memDriveEn, + oImmDrive => immDriveEn, + oAccDrive => acDriveEn, + oYBusDrive => yBusDriveEn, + oYBufDrive => yBufDriveEn, + oRamWrN => ramWrN, + oMauLoDis => mauDisableLo, + oRetI => retI); ---------------------------------------------------------- ------ Immediate Data Register ------- @@ -327,11 +327,11 @@ begin ------ Arithmetic Logic Unit ------- ---------------------------------------------------------- aluComp : entity work.alu - port map( iDataA => dataBus, - iDataB => acReg, - iOp => aluOp, - oData => aluData, - oCarry => aluCarry); + port map( iDataA => dataBus, + iDataB => acReg, + iOp => aluOp, + oData => aluData, + oCarry => aluCarry); ---------------------------------------------------------- ------ Accumulator Register and Buffer ------- @@ -464,8 +464,9 @@ begin ---------------------------------------------------------- ------ Keyboard $5000-$5FFF ------- ---------------------------------------------------------- - -- Address lines 8 downto 0 to keyboard array (11 downto 0 is available) - -- keyArray 6 downto 0 is from keyboard + -- Address lines 10 downto 0 to keyboard array (11 downto 0 is available) + -- keyArray 5 downto 0 from keyboard + -- keyArray 6 from audio input -- keyArray 7 from serial port input keyArray <= "11111111"; @@ -476,7 +477,7 @@ begin oData => dataBus); ---------------------------------------------------------- - ------ Audio ------- + ------ Audio Out ------- ---------------------------------------------------------- -- Keep writing access to XOUT with video output? -- or switch to memory bus access? From 31d1144919b7c64f658cd055844c0c3d074a12a6 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Fri, 3 Jan 2025 15:08:59 -0500 Subject: [PATCH 08/14] Add immediate value memory access mode. Make all address modes the same as original gigatron. Change assembly worksheet to match and update test code. --- project/gtxl.xpr | 6 +-- resources/Assembly.xlsx | Bin 56315 -> 56545 bytes src/hdl/control.vhd | 41 +++++++++--------- src/hdl/cpu.vhd | 50 ++++++++++++++++------ src/hdl/rom_synth.vhd | 71 ++++++++++++++----------------- src/sim/tb_basys_demo_behav.wcfg | 32 +++++++------- 6 files changed, 110 insertions(+), 90 deletions(-) diff --git a/project/gtxl.xpr b/project/gtxl.xpr index d093004..f7450d2 100644 --- a/project/gtxl.xpr +++ b/project/gtxl.xpr @@ -44,7 +44,7 @@ y=qJF$3C8}Y)n9v-7EXTDZ7JjMyqE>y} zM8`YxXm?Jedqs=VsF8JL>$g^O?5|$ctKp_ID!kID?Q4)u z2gY`-^Tp=5MUYAx`_FPuN(O{KtsSW6AoX8v^2?*&9)Q7NchTRp@j{g+4XufHSu{U! ztZM$YF$G5XG=w&fRA2w?!=st&#@j$%Sdci$tWeqJ!in9$iRB4Kh*DB2Y7$Y_9W)FW ze}A0HYPZ|FMf3d506tk`J27z3w=nL$chtyP<2*^I`MefWzJxodh|fdw^!NVqBNlIk zfEdu6f&mx}fN8-X^9dQX5x$9I`?bKJ26gEz!{OXMg%2vm+Z}GV8(tckYkeZ06qU&w zb5N6rKTPv*qoBq#dDL0-t?|dN`O=GlPOHSXQ$v;u%6l|-x9T^s0+zau=S_r*KQ9T{ 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z2obfM{(w!_eUF7XZo zIC0aF9p9Jl4q!4a-Au~I9XiTK>U_=;(TtE5wKKq}>>120guxh2Qc@Ygv7Kewk|IHe z<8?wAv;pBCVLHF*|CzGcH>5?+@XrifJpY&pZ5ZBTOosp8shhMkywoPmf3IQek9U|*pzBJfE=BPT z6HvO|_juL!l6cT0lx{eax`f~zCVBY(yHoUET2uJMNfG{kKtW4G^PG-`hU?!=>gqSX Te-cI)K8)v_0y7$qo$vh*sX)zx diff --git a/src/hdl/control.vhd b/src/hdl/control.vhd index ab8d23f..fec06c2 100644 --- a/src/hdl/control.vhd +++ b/src/hdl/control.vhd @@ -155,7 +155,7 @@ begin oVidLoad <= '0' when (modeName="[80,D] ,VID" or modeName="[ Y,X++],VID") and opName/=" ST" else '1'; - oIncX <= not iExecute; + oIncX <= not iExecute; ---------------------------------------------------------- ------ Data Bus Source Selector ------- diff --git a/src/hdl/cpu.vhd b/src/hdl/cpu.vhd index 048e8b1..138dcf0 100644 --- a/src/hdl/cpu.vhd +++ b/src/hdl/cpu.vhd @@ -392,24 +392,6 @@ begin oData => xReg(7 downto 4), oTerminal => interrupt); - ---------------------------------------------------------- - ------ X Bus ------- - ---------------------------------------------------------- - -- 0 for X, 1 for D - xBusLoComp : entity work.sn74hct157 - port map( iA => xReg(3 downto 0), - iB => immReg(3 downto 0), - iEnableN => '0', - iSelect => xBusSel, - oY => xBus(3 downto 0)); - - xBusHiComp : entity work.sn74hct157 - port map( iA => xReg(7 downto 4), - iB => immReg(7 downto 4), - iEnableN => '0', - iSelect => xBusSel, - oY => xBus(7 downto 4)); - ---------------------------------------------------------- ------ Video Register ------- ---------------------------------------------------------- diff --git a/src/hdl/rom_synth.vhd b/src/hdl/rom_synth.vhd index de040ee..509dcdd 100644 --- a/src/hdl/rom_synth.vhd +++ b/src/hdl/rom_synth.vhd @@ -36,26 +36,26 @@ architecture rtl of rom_synth is 0 =>x"C2", 1=>x"00", -- st [80,D] AC-- store AC to 0x8000-- save register states 2 =>x"C3", 3=>x"01", -- st [80,D] Y-- store Y to 0x8001 4 =>x"10", 5=>x"38", -- ld X D-- Set X to 0x55--reload timer - 6 =>x"02", 7=>x"00", -- nop 0 0 - 8 =>x"02", 9=>x"00", -- nop 0 0 - 10 =>x"02", 11=>x"00", -- nop 0 0 - 12 =>x"02", 13=>x"00", -- nop 0 0 - 14 =>x"01", 15=>x"03", -- ld [80,D] MEM-- Load BOOTCNT--check if booting finished - 16 =>x"60", 17=>x"37", -- xor AC D--XOR compare 55 with BOOTCNT - 18 =>x"F0", 19=>x"20", -- beq 0 D--branch if equal to VIDEO_HANDLER - 20 =>x"01", 21=>x"03", -- ld [80,D] MEM-- Load BOOTCNT - 22 =>x"60", 23=>x"01", -- xor AC D-- xor compare with 1--check if first boot - 24 =>x"F0", 25=>x"2E", -- beq 0 D-- branch to BOOT_VECTOR if equal - 26 =>x"00", 27=>x"01", -- ld AC D--first boot - 28 =>x"C2", 29=>x"03", -- st [80,D] AC--store 0x01 to BOOTCNT - 30 =>x"E3", 31=>x"00", -- reti 0 0-- reti to set interrupt enbale-- reti to clear interrupt disable for normal booting - 32 =>x"00", 33=>x"00", -- ld AC D-- clear registers-- VIDEO_HANDLER + 6 =>x"01", 7=>x"03", -- ld [80,D] MEM-- Load BOOTCNT--check if booting finished + 8 =>x"60", 9=>x"37", -- xor AC D--XOR compare 55 with BOOTCNT + 10 =>x"EC", 11=>x"2E", -- bne 0 D-- branch to BOOT_VECTOR if not equal + 12 =>x"00", 13=>x"00", -- ld AC D-- clear registers-- VIDEO_HANDLER + 14 =>x"14", 15=>x"00", -- ld y D + 16 =>x"01", 17=>x"00", -- ld [80,D],AC MEM--load AC--restore registers + 18 =>x"15", 19=>x"01", -- ld [80,D],Y MEM-- load Y + 20 =>x"E3", 21=>x"00", -- reti 0 0-- return from interrupt + 22 =>x"02", 23=>x"00", -- nop 0 0 + 24 =>x"02", 25=>x"00", -- nop 0 0 + 26 =>x"02", 27=>x"00", -- nop 0 0 + 28 =>x"02", 29=>x"00", -- nop 0 0 + 30 =>x"02", 31=>x"00", -- nop 0 0 + 32 =>x"02", 33=>x"00", -- nop 0 0 34 =>x"02", 35=>x"00", -- nop 0 0 - 36 =>x"14", 37=>x"00", -- ld Y D - 38 =>x"01", 39=>x"00", -- ld [80,D],AC MEM--load AC--restore registers + 36 =>x"02", 37=>x"00", -- nop 0 0 + 38 =>x"02", 39=>x"00", -- nop 0 0 40 =>x"02", 41=>x"00", -- nop 0 0 - 42 =>x"15", 43=>x"02", -- ld [80,D],Y MEM-- load Y - 44 =>x"E3", 45=>x"00", -- reti 0 0-- return from interrupt + 42 =>x"02", 43=>x"00", -- nop 0 0 + 44 =>x"02", 45=>x"00", -- nop 0 0 46 =>x"00", 47=>x"37", -- ld AC D-- BOOT_VECTOR 48 =>x"C2", 49=>x"03", -- st [80,D] AC-- store 55 to BOOTCNT 50 =>x"00", 51=>x"00", -- ld AC D--initialize AC with 0-- main test program:store value to memory, load it back, add to it, repeat diff --git a/src/sim/tb_basys_demo_behav.wcfg b/src/sim/tb_basys_demo_behav.wcfg index fca6c87..59f67b8 100644 --- a/src/sim/tb_basys_demo_behav.wcfg +++ b/src/sim/tb_basys_demo_behav.wcfg @@ -15,13 +15,13 @@ - + - + clkSys clkSys @@ -87,14 +87,6 @@ yBus[7:0] yBus[7:0] - - xBusSel - xBusSel - - - xBus[7:0] - xBus[7:0] - instReg[7:0] instReg[7:0] From e633f16d0d41e4dba2a927d30dc50e3cff316235 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Fri, 10 Jan 2025 16:59:45 -0500 Subject: [PATCH 13/14] Add assembler ruleset for instruction set --- resources/Assembly.xlsx | Bin 56120 -> 59762 bytes src/asm/ruledef.txt | 272 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 272 insertions(+) create mode 100644 src/asm/ruledef.txt diff --git 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=> 0x15 @ value[7:0] + ldy {value :i8} => 0x15 @ value + ldy ac => 0x16 @ 0x00 + + ldv #{value: i8} => 0x18 @ value + ldv {value: i16} => 0x19 @ value[7:0] + ldv {value :i8} => 0x19 @ value + ldv ac => 0x1A @ 0x00 + ldv y => 0x1B @ 0x00 + ldv (y,x) => 0x1D @ 0x00 + + anda #{value: i8} => 0x20 @ value + anda {value: i16} => 0x21 @ value[7:0] + anda {value :i8} => 0x21 @ value + anda y => 0x23 @ 0x00 + anda (x) => 0x25 @ 0x00 + anda (y,#{value :i8}) => 0x29 @ value + anda (y,x) => 0x2d @ 0x00 + + andx #{value: i8} => 0x30 @ value + andx {value: i16} => 0x31 @ value[7:0] + andx {value :i8} => 0x31 @ value + andx y => 0x33 @ 0x00 ; and ac with y, store into x + + andy #{value: i8} => 0x34 @ value + andy {value: i16} => 0x35 @ value[7:0] + andy {value :i8} => 0x35 @ value + andy ac => 0x36 @ 0x00 ; move ac to y + andy y => 0x37 @ 0x00 ; and ac with y, store into y + + andv #{value: i8} => 0x38 @ value + andv {value: i16} => 0x39 @ value[7:0] + andv {value :i8} => 0x39 @ value + andv (y,x) => 0x3D @ 0x00 + + ora #{value: i8} => 0x40 @ value + ora {value: i16} => 0x41 @ value[7:0] + ora {value :i8} => 0x41 @ value + ora y => 0x43 @ 0x00 + ora (x) => 0x45 @ 0x00 + ora (y,#{value :i8}) => 0x49 @ value + ora (y,x) => 0x4d @ 0x00 + + orx #{value: i8} => 0x50 @ value + orx {value: i16} => 0x51 @ value[7:0] + orx {value :i8} => 0x51 @ value + orx y => 0x53 @ 0x00 ; or ac with y, store into x + + ory #{value: i8} => 0x54 @ value + ory {value: i16} => 0x55 @ value[7:0] + ory {value :i8} => 0x55 @ value + ory ac => 0x56 @ 0x00 ; move ac to y + ory y => 0x57 @ 0x00 ; or ac with y, store into y + + orv #{value: i8} => 0x58 @ value + orv {value: i16} => 0x59 @ value[7:0] + orv {value :i8} => 0x59 @ value + orv (y,x) => 0x5D @ 0x00 + + xora #{value: i8} => 0x60 @ value + xora {value: i16} => 0x61 @ value[7:0] + xora {value :i8} => 0x61 @ value + xora ac => 0x62 @ 0x00 ; clr ac + clra => 0x62 @ 0x00 + xora y => 0x63 @ 0x00 + xora (x) => 0x65 @ 0x00 + xora (y,#{value :i8}) => 0x69 @ value + xora (y,x) => 0x6d @ 0x00 + + xorx #{value: i8} => 0x70 @ value + xorx {value: i16} => 0x71 @ value[7:0] + xorx {value :i8} => 0x71 @ value + xorx y => 0x73 @ 0x00 ; xor ac with y, store into x + + xory #{value: i8} => 0x74 @ value + xory {value: i16} => 0x75 @ value[7:0] + xory {value :i8} => 0x75 @ value + xory ac => 0x76 @ 0x00 ; clr y + clry => 0x76 @ 0x00 + xory y => 0x77 @ 0x00 ; xor ac with y, store into y + + xorv #{value: i8} => 0x78 @ value + xorv {value: i16} => 0x79 @ value[7:0] + xorv {value :i8} => 0x79 @ value + xorv (y,x) => 0x7D @ 0x00 + + adda #{value: i8} => 0x80 @ value + adda {value: i16} => 0x81 @ value[7:0] + adda {value :i8} => 0x81 @ value + adda ac => 0x82 @ 0x00 ; shl ac + shl => 0x82 & 0x00 + adda y => 0x83 @ 0x00 + adda (x) => 0x85 @ 0x00 + adda (y,#{value :i8}) => 0x89 @ value + adda (y,x) => 0x8d @ 0x00 + + addx #{value: i8} => 0x90 @ value + addx {value: i16} => 0x91 @ value[7:0] + addx {value :i8} => 0x91 @ value + addx y => 0x93 @ 0x00 ; add ac with y, store into x + + addy #{value: i8} => 0x94 @ value + addy {value: i16} => 0x95 @ value[7:0] + addy {value :i8} => 0x95 @ value + addy ac => 0x96 @ 0x00 ; shl ac and store in y + addy y => 0x97 @ 0x00 ; add ac with y, store into y + + addv #{value: i8} => 0x98 @ value + addv {value: i16} => 0x99 @ value[7:0] + addv {value :i8} => 0x99 @ value + addv (y,x) => 0x9D @ 0x00 + + suba #{value: i8} => 0xa0 @ value + suba {value: i16} => 0xa1 @ value[7:0] + suba {value :i8} => 0xa1 @ value + suba y => 0xa3 @ 0x00 + suba (x) => 0xa5 @ 0x00 + suba (y,#{value :i8}) => 0xa9 @ value + suba (y,x) => 0xad @ 0x00 + + subx #{value: i8} => 0xb0 @ value + subx {value: i16} => 0xb1 @ value[7:0] + subx {value :i8} => 0xb1 @ value + subx y => 0xb3 @ 0x00 ; subtract ac with y, store into x + + suby #{value: i8} => 0xb4 @ value + suby {value: i16} => 0xb5 @ value[7:0] + suby {value :i8} => 0xb5 @ value + suby ac => 0xb6 @ 0x00 + suby y => 0xb7 @ 0x00 ; subtract ac with y, store into y + + subv #{value: i8} => 0xb8 @ value + subv {value: i16} => 0xb9 @ value[7:0] + subv {value :i8} => 0xb9 @ value + subv (y,x) => 0xbD @ 0x00 + + sti #{value: i8},({value2: i8}) => 0xc0 @ value + sta {value: i8} => 0xc2 @ value + sta {value: i16} => 0xc2 @ value[7:0] + sty {value: i8} => 0xc3 @ value + sty {value: i16} => 0xc3 @ value[7:0] + + sti #{value: i8},(x) => 0xc4 @ value + sta (x) => 0xc6 @ 0x00 + sty (x) => 0xc7 @ 0x00 + + sti #{value: i8},(y,{value2: i8}) => 0xc8 @ value + sta (y,{value: i8}) => 0xca @ value + sty (y,{value: i8}) => 0xcb @ value + + sti #{value: i8},(y,x) => 0xcc @ value + sta (y,x) => 0xce @ 0x00 + sty (y,x) => 0xcf @ 0x00 + + sti #{value: i8},({value2: i8}),x => 0xd0 @ value + sta {value: i8},x => 0xd2 @ value + sty {value: i8},x => 0xd3 @ value + + sti #{value: i8},({value2: i8}),y => 0xd4 @ value + sta {value: i8},y => 0xd6 @ value + sty {value: i8},y => 0xd7 @ value + + jmp {value: i8} => 0xe0 @ value + jmp ({value: i8}) => 0xe1 @ value + jmp ac => 0xe200 + reti => 0xe300 + + bgt {value: i8} => 0xe4 @ value + bgt ({value: i8}) => 0xe5 @ value + bgt ac => 0xe600 + bgt y => 0xe700 + + blt {value: i8} => 0xe8 @ value + blt ({value: i8}) => 0xe9 @ value + blt ac => 0xea00 + blt y => 0xeb00 + + bne {value: i8} => 0xec @ value + bne ({value: i8}) => 0xed @ value + bne ac => 0xee00 + bne y => 0xef00 + + beq {value: i8} => 0xf0 @ value + beq ({value: i8}) => 0xf1 @ value + beq ac => 0xf200 + beq y => 0xf300 + + bge {value: i8} => 0xf4 @ value + bge ({value: i8}) => 0xf5 @ value + bge ac => 0xf600 + bge y => 0xf700 + + ble {value: i8} => 0xf8 @ value + ble ({value: i8}) => 0xf9 @ value + ble ac => 0xfa00 + ble y => 0xfb00 + + bra {value: i8} => 0xfc @ value + bra ({value: i8}) => 0xfd @ value + bra ac => 0xfe00 + bra y => 0xff00 + +} + +#bank zeropage + +acStore: #res 1 +yStore: #res 1 +xStore: #res 1 +bootCheck: #res 1 +testCount: #res 1 + +#bank prg + +interrupt: + ; store registers and reload timer + sta acStore + sty yStore + ldx #56 + + ; check for cold boot + lda bootCheck + xora #55 + bne .boot + + ; clear registers to test / emulate video drawing + lda #0 + ldy #0 + + ; end of interrupt routine - restore registers + lda acStore + ldy yStore + reti + +.boot: + ; record that we have booted + lda #55 + sta bootCheck + +.main: + lda #0 + .loop: + sta testCount ; test memory by saving and restoring variable + lda testCount + adda #1 + ldv ac + bra .loop + \ No newline at end of file From e388ea860c00ac0bae8488073d3f81bc9e4e64b3 Mon Sep 17 00:00:00 2001 From: Justin Davis Date: Fri, 10 Jan 2025 17:01:47 -0500 Subject: [PATCH 14/14] Change ram write signal to ensure no overrun. Remove stale signals. --- project/gtxl.xpr | 2 +- src/hdl/control.vhd | 3 +- src/hdl/cpu.vhd | 96 +++++++++++++++++--------------- src/hdl/rom_synth.vhd | 69 ++++++++++++----------- src/sim/tb_basys_demo_behav.wcfg | 25 ++++++--- 5 files changed, 107 insertions(+), 88 deletions(-) diff --git a/project/gtxl.xpr b/project/gtxl.xpr index 2baca3f..48d46e1 100644 --- a/project/gtxl.xpr +++ b/project/gtxl.xpr @@ -44,7 +44,7 @@