diff --git a/.github/actions/run-tests/action.yml b/.github/actions/run-tests/action.yml
index fbfd4649de..38d002431e 100644
--- a/.github/actions/run-tests/action.yml
+++ b/.github/actions/run-tests/action.yml
@@ -19,6 +19,7 @@ runs:
     - name: Init submodules (since only the RTL is cached)
       run: |
         conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)
+        git submodule sync
         ./scripts/init-submodules-no-riscv-tools.sh
       shell: bash -leo pipefail {0}
 
diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
index e906ac29b2..c92d10a173 100755
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -46,7 +46,7 @@ search () {
 }
 
 
-submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn")
 dir="generators"
 branches=("master" "main" "dev")
 search
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 5e448be447..5526eb2041 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -27,7 +27,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
-grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc"
+grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
@@ -71,6 +71,8 @@ mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
 mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
 mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
 mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig"
+mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig"
+mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig"
 
 mapping["constellation"]=" SUB_PROJECT=constellation"
 mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig"
diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh
index 7a9888407e..54734096d5 100755
--- a/.github/scripts/remote-do-rtl-build.sh
+++ b/.github/scripts/remote-do-rtl-build.sh
@@ -15,6 +15,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
 source $SCRIPT_DIR/defaults.sh
 
 cd $REMOTE_CHIPYARD_DIR
+git submodule sync
 ./scripts/init-submodules-no-riscv-tools.sh
 
 # Constellation can run without espresso, but this improves
diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index 6855e15a2b..d70a479c17 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -135,6 +135,12 @@ case $1 in
         make -C $LOCAL_CHIPYARD_DIR/generators/rerocc/tests
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/rerocc/tests/rerocc.riscv LOADMEM=1
         ;;
+    chipyard-rocketvector|chipyard-shuttlevector)
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;
diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml
index 0ecc29504c..1ccc548d7b 100644
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -18,6 +18,7 @@ env:
   # temporary directories should be located in /scratch (since it's larger)
   REMOTE_WORK_DIR: /scratch/buildbot/cy-ci-shared/cy-workdir-${{ github.sha }}
   JAVA_TMP_DIR: /scratch/buildbot/cy-ci-shared/cy-javatmpdir-${{ github.sha }}
+  GIT_SSH_COMMAND: "ssh -v"
 
 jobs:
   cancel-prior-workflows:
@@ -84,6 +85,7 @@ jobs:
           eval "$(conda shell.bash hook)"
           mkdir ${{ env.JAVA_TMP_DIR }}
           export MAKEFLAGS="-j32"
+          git submodule sync
           ./build-setup.sh -v
       - name: Run config finder
         run: |
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index 9afbf5aee6..6de3f9e66c 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -798,6 +798,52 @@ jobs:
           group-key: "group-accels"
           project-key: "chipyard-rerocc"
 
+  chipyard-rocketvector-run-tests:
+    name: chipyard-rocketvector-run-tests
+    needs: prepare-chipyard-accels
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-accels"
+          project-key: "chipyard-rocketvector"
+
+  chipyard-shuttlevector-run-tests:
+    name: chipyard-shuttlevector-run-tests
+    needs: prepare-chipyard-accels
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-accels"
+          project-key: "chipyard-shuttlevector"
+
   chipyard-gemmini-run-tests:
     name: chipyard-gemmini-run-tests
     needs: prepare-chipyard-accels
@@ -1188,6 +1234,8 @@ jobs:
             chipyard-symmetric-run-tests,
             chipyard-llcchiplet-run-tests,
             chipyard-rerocc-run-tests,
+            chipyard-rocketvector-run-tests,
+            chipyard-shuttlevector-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
             chipyard-prefetchers-run-tests,
diff --git a/.gitmodules b/.gitmodules
index 6ff8ac86f1..014d09bb67 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -147,4 +147,7 @@
 	url = https://github.com/ucb-bar/rerocc.git
 [submodule "generators/compress-acc"]
 	path = generators/compress-acc
-  url = https://github.com/ucb-bar/compress-acc.git
+	url = https://github.com/ucb-bar/compress-acc.git
+[submodule "generators/saturn"]
+	path = generators/saturn
+	url = https://github.com/ucb-bar/saturn-vectors.git
diff --git a/build.sbt b/build.sbt
index c5602ab3e3..db68f56a95 100644
--- a/build.sbt
+++ b/build.sbt
@@ -176,7 +176,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
-    compressacc)
+    compressacc, saturn)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(
     libraryDependencies ++= Seq(
@@ -201,6 +201,11 @@ lazy val barf = (project in file("generators/bar-fetchers"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+lazy val saturn = (project in file("generators/saturn"))
+  .dependsOn(rocketchip, shuttle)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
 lazy val constellation = (project in file("generators/constellation"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
diff --git a/docs/Generators/Saturn.rst b/docs/Generators/Saturn.rst
new file mode 100644
index 0000000000..bbf2988f12
--- /dev/null
+++ b/docs/Generators/Saturn.rst
@@ -0,0 +1,18 @@
+Saturn
+========
+
+Saturn is a parameterized RISC-V Vector Unit generator currently supporting integration with the Rocket and Shuttle cores.
+Saturn implements a compact short-vector-length vector microarchitecture suitable for deployment in a DSP-optimized core or area-efficient general-purpose core.
+
+More documentation on Saturn will be released in the future.
+
+ * Full support for `V` application-profile RVV 1.0
+ * Precise traps with virtual memory
+ * Indexed/strided/segmented loads and stores
+ * Mask operations
+ * Register-gather + reductions
+ * `Zvfh` support for vector half-precision floating-point (FP16)
+ * `Zve64d` support for vector FP32 and FP64
+ * Configurable vector length, from `Zvl64b` up (tested to `Zvl4096b`)
+ * Configurable datapath width, from 64b up (tested to 512b)
+
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
index d55dce0cc8..25d4d24430 100644
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -23,6 +23,7 @@ so changes to the generators themselves will automatically be used when building
    BOOM
    Constellation
    Gemmini
+   Saturn
    IceNet
    TestChipIP
    Rocket-Chip-Generators
diff --git a/generators/chipyard/src/main/scala/config/SaturnConfigs.scala b/generators/chipyard/src/main/scala/config/SaturnConfigs.scala
new file mode 100644
index 0000000000..4ff761c1bf
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/SaturnConfigs.scala
@@ -0,0 +1,171 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import saturn.common.{VectorParams}
+
+// Rocket-integrated configs
+class MINV64D64RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(64, 64, VectorParams.minParams) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class MINV128D64RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class MINV256D64RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.minParams) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV128D128RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(128, 128, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV256D64RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.refParams) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV256D128RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(256, 128, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV512D128RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(512, 128, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV512D256RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(512, 256, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class DMAV256D256RocketConfig extends Config(
+  new saturn.rocket.WithRocketVectorUnit(256, 256, VectorParams.dmaParams) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// Shuttle-integrated configs
+class GENV128D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(128, 128, VectorParams.genParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV256D64ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(256, 64, VectorParams.refParams) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV256D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class DSPV256D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.dspParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithSGTCM(address=0x78000000, size=(8L << 10), banks=16) ++
+  new shuttle.common.WithTCM ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class GENV256D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.genParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV512D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(512, 128, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class DSPV512D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(512, 128, VectorParams.dspParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class GENV512D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(512, 128, VectorParams.genParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class GENV512D256ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(512, 256, VectorParams.genParams) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new shuttle.common.WithShuttleTileBeatBytes(32) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class GENV1024D128ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(1024, 128, VectorParams.genParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV256D256ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(256, 256, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new shuttle.common.WithShuttleTileBeatBytes(32) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV512D256ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(512, 256, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new shuttle.common.WithShuttleTileBeatBytes(32) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class REFV512D512ShuttleConfig extends Config(
+  new saturn.shuttle.WithShuttleVectorUnit(512, 512, VectorParams.refParams) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new shuttle.common.WithShuttleTileBeatBytes(64) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+
+// Cosim configs
+
+class MINV128D64RocketCosimConfig extends Config(
+  new chipyard.harness.WithCospike ++
+  new chipyard.config.WithTraceIO ++
+  new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++
+  new freechips.rocketchip.rocket.WithCease(false) ++
+  new freechips.rocketchip.rocket.WithDebugROB ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class GENV256D128ShuttleCosimConfig extends Config(
+  new chipyard.harness.WithCospike ++
+  new chipyard.config.WithTraceIO ++
+  new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.genParams) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new shuttle.common.WithShuttleDebugROB ++
+  new shuttle.common.WithShuttleTileBeatBytes(16) ++
+  new shuttle.common.WithNShuttleCores(1) ++
+  new chipyard.config.AbstractConfig)
+
diff --git a/generators/saturn b/generators/saturn
new file mode 160000
index 0000000000..cca7877f59
--- /dev/null
+++ b/generators/saturn
@@ -0,0 +1 @@
+Subproject commit cca7877f59a2c9a8f01685b7877ad7b665c02a09