diff --git a/verilator/README.md b/verilator/README.md
index 5eb1f34..d1ff1b9 100644
--- a/verilator/README.md
+++ b/verilator/README.md
@@ -1,5 +1,8 @@
 # Verilator Simulation Control Module
 
+>[!WARNING]
+>EXPERIMENTAL
+
 The Verilator simulor control module is a _VProc_ wrapper that allows control of the running simulation on the console command line from where
 the test bench with the module instnatiated is run. It consists of a SystemVerilog module defined in `verilator/verilator_sim_ctrl.sv` with a 
 single clock input (`clk`) and a clock count output (`clk_count`) for use by the test bench if desired. The only other inputs to the module are
@@ -35,7 +38,7 @@ static const int node = 0;
 
 extern "C" void VUserMain0 (void)
 {
-    VerilatorSimCtrl();
+    VerilatorSimCtrl(node);
 
     SLEEPFOREVER;
 }
@@ -43,7 +46,7 @@ extern "C" void VUserMain0 (void)
 
 ## Commands
 
-The code above makes a simple call to a function `VerilatorSimCtrl()` that starts the Verilator Simulation Control features and prints some
+The code above makes a simple call to a function `VerilatorSimCtrl()`, with the _VProc_ node number, that starts the Verilator Simulation Control features and prints some
 information about the configuration and then a prompt. The user can then enter commands to run the simulation for a given time, relative to
 current time, or to a given absolute time in the future. The list below shows the form of the commands available
 
diff --git a/verilator/src/VerilatorSimCtrl.cpp b/verilator/src/VerilatorSimCtrl.cpp
index e0dc697..e536f18 100644
--- a/verilator/src/VerilatorSimCtrl.cpp
+++ b/verilator/src/VerilatorSimCtrl.cpp
@@ -23,9 +23,6 @@
 #include "VProcClass.h"
 #include "VerilatorSimCtrl.h"
 
-// I'm node 0
-static const int node = 0;
-
 // ---------------------------------------------
 // advance_relative_cycles()
 // ---------------------------------------------
@@ -291,7 +288,7 @@ void rungtkwave (void)
 // function
 // ---------------------------------------------
 
-void VerilatorSimCtrl (void)
+void VerilatorSimCtrl (const uint32_t node)
 {
     uint32_t    clk_period_ps;
     uint32_t    cyc_count_now;
diff --git a/verilator/src/VerilatorSimCtrl.h b/verilator/src/VerilatorSimCtrl.h
index 7a3e1a9..5d7cbda 100644
--- a/verilator/src/VerilatorSimCtrl.h
+++ b/verilator/src/VerilatorSimCtrl.h
@@ -64,6 +64,6 @@
                                                         1000000000000.0))
 
 extern void flushfst (void);
-extern void VerilatorSimCtrl(void);
+extern void VerilatorSimCtrl(const uint32_t node);
 
 #endif
\ No newline at end of file
diff --git a/verilator/test/usercode/VUserMain0.cpp b/verilator/test/usercode/VUserMain0.cpp
index 405a73f..f327fc2 100644
--- a/verilator/test/usercode/VUserMain0.cpp
+++ b/verilator/test/usercode/VUserMain0.cpp
@@ -31,7 +31,7 @@ static const int node = 0;
 
 extern "C" void VUserMain0 (void)
 {
-    VerilatorSimCtrl();
+    VerilatorSimCtrl(node);
 
     SLEEPFOREVER;
 }
\ No newline at end of file