VHDL (VHSIC Hardware Description Language) Projects for FPGA (Field-Programmable Gate Array) Synthesis Laboratory
This repository contains various sample VHDL projects. These projects were created for and under the
instruction/guidance of the FPGA Synthesis Laboratory course at JHU.
An advanced laboratory course in the application of FPGA technology to digital systems, using VHDL synthesis methods
for hardware development. The student will use commercial CAD software for VHDL simulation and synthesis, and will
implement their circuits on development boards containing XILINX Spartan-3 FPGA devices.
The lab will consist of a series of digital hardware projects demonstrating VHDL design and synthesis methodology,
building up to final projects at least the size of a 16-bit RISC computer or a Digital Phase-Locked Loop. Projects
will encompass such things as system clocking, flip-flop registers, state-machine control, and arithmetic.
Note that I do not own all of the code/materials contained in this repository. Some code/materials were provided by the course/university. Some code/materials were created with fellow classmates.