From 919a19cf2f36dff07a3393b090491343802d8f7b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E6=98=8E=E5=BE=B7=E6=97=A0=E6=95=8C=E8=B5=B5=E6=99=93?=
=?UTF-8?q?=E8=96=87?= <1755923166@qq.com>
Date: Wed, 26 Jun 2019 22:05:54 +0800
Subject: [PATCH] inti code
inti code
---
README.md | 12 +
app/init.c | 142 +
app/init.h | 14 +
app/main.c | 22 +
bsp/include/DSP2833x_Adc.h | 285 +
bsp/include/DSP2833x_CpuTimers.h | 255 +
bsp/include/DSP2833x_DMA.h | 397 ++
bsp/include/DSP2833x_DefaultIsr.h | 206 +
bsp/include/DSP2833x_DevEmu.h | 131 +
bsp/include/DSP2833x_Device.h | 239 +
bsp/include/DSP2833x_Dma_defines.h | 139 +
bsp/include/DSP2833x_ECan.h | 1287 ++++
bsp/include/DSP2833x_ECap.h | 179 +
bsp/include/DSP2833x_EPwm.h | 465 ++
bsp/include/DSP2833x_EPwm_defines.h | 243 +
bsp/include/DSP2833x_EQep.h | 270 +
bsp/include/DSP2833x_Examples.h | 167 +
bsp/include/DSP2833x_GlobalPrototypes.h | 291 +
bsp/include/DSP2833x_Gpio.h | 493 ++
bsp/include/DSP2833x_I2c.h | 233 +
bsp/include/DSP2833x_I2c_defines.h | 179 +
bsp/include/DSP2833x_Mcbsp.h | 807 +++
bsp/include/DSP2833x_PieCtrl.h | 195 +
bsp/include/DSP2833x_PieVect.h | 265 +
bsp/include/DSP2833x_SWPrioritizedIsrLevels.h | 5999 +++++++++++++++++
bsp/include/DSP2833x_Sci.h | 251 +
bsp/include/DSP2833x_Spi.h | 208 +
bsp/include/DSP2833x_SysCtrl.h | 484 ++
bsp/include/DSP2833x_XIntrupt.h | 109 +
bsp/include/DSP2833x_Xintf.h | 154 +
bsp/include/DSP28x_Project.h | 53 +
bsp/source/DSP2833x_ADC_cal.asm | 74 +
bsp/source/DSP2833x_Adc.c | 99 +
bsp/source/DSP2833x_CSMPasswords.asm | 95 +
bsp/source/DSP2833x_CodeStartBranch.asm | 117 +
bsp/source/DSP2833x_CpuTimers.c | 195 +
bsp/source/DSP2833x_DBGIER.asm | 59 +
bsp/source/DSP2833x_DMA.c | 1316 ++++
bsp/source/DSP2833x_DisInt.asm | 96 +
bsp/source/DSP2833x_ECan.c | 495 ++
bsp/source/DSP2833x_ECap.c | 304 +
bsp/source/DSP2833x_EPwm.c | 407 ++
bsp/source/DSP2833x_EQep.c | 191 +
bsp/source/DSP2833x_GlobalVariableDefs.c | 407 ++
bsp/source/DSP2833x_Gpio.c | 108 +
bsp/source/DSP2833x_I2C.c | 110 +
bsp/source/DSP2833x_Mcbsp.c | 552 ++
bsp/source/DSP2833x_MemCopy.c | 81 +
bsp/source/DSP2833x_PieCtrl.c | 126 +
bsp/source/DSP2833x_SWPrioritizedDefaultIsr.c | 2670 ++++++++
bsp/source/DSP2833x_SWPrioritizedPieVect.c | 573 ++
bsp/source/DSP2833x_Sci.c | 224 +
bsp/source/DSP2833x_Spi.c | 144 +
bsp/source/DSP2833x_SysCtrl.c | 453 ++
bsp/source/DSP2833x_Xintf.c | 334 +
bsp/source/DSP2833x_usDelay.asm | 107 +
cmd/DSP2833x_Headers_nonBIOS.cmd | 214 +
cmd/F28335.cmd | 235 +
drivers/mcbsp.c | 144 +
drivers/mcbsp.h | 15 +
drivers/spi.c | 34 +
drivers/spi.h | 15 +
drivers/sx1255.c | 99 +
drivers/sx1255.h | 14 +
drivers/sx1255_rx.c | 40 +
drivers/sx1255_rx.h | 15 +
drivers/sx1255_tx.c | 42 +
drivers/sx1255_tx.h | 16 +
libs/complex/complex.h | 18 +
libs/crc/crc32.c | 60 +
libs/crc/crc32.h | 14 +
libs/fsk/fsk_ang.c | 37 +
libs/fsk/fsk_ang.h | 14 +
libs/fsk/fsk_corr.c | 79 +
libs/fsk/fsk_corr.h | 15 +
libs/fsk/fsk_dc.c | 65 +
libs/fsk/fsk_dc.h | 16 +
libs/fsk/fsk_decode.c | 75 +
libs/fsk/fsk_decode.h | 14 +
libs/fsk/fsk_demod.c | 120 +
libs/fsk/fsk_demod.h | 16 +
libs/fsk/fsk_est.c | 59 +
libs/fsk/fsk_est.h | 14 +
libs/fsk/fsk_filter.c | 79 +
libs/fsk/fsk_filter.h | 15 +
libs/fsk/fsk_frame.h | 19 +
libs/fsk/fsk_gen.c | 49 +
libs/fsk/fsk_gen.h | 14 +
libs/fsk/fsk_mod.c | 88 +
libs/fsk/fsk_mod.h | 16 +
libs/fsk/fsk_norm.c | 39 +
libs/fsk/fsk_norm.h | 14 +
libs/fsk/fsk_pack.c | 37 +
libs/fsk/fsk_pack.h | 14 +
libs/fsk/fsk_table.c | 214 +
libs/fsk/fsk_table.h | 19 +
libs/fsk/fsk_unpack.c | 46 +
libs/fsk/fsk_unpack.h | 14 +
libs/link/link_rx.c | 44 +
libs/link/link_rx.h | 16 +
libs/link/link_tx.c | 74 +
libs/link/link_tx.h | 16 +
libs/safepipe/safepipe.c | 77 +
libs/safepipe/safepipe.h | 38 +
104 files changed, 25952 insertions(+)
create mode 100644 app/init.c
create mode 100644 app/init.h
create mode 100644 app/main.c
create mode 100644 bsp/include/DSP2833x_Adc.h
create mode 100644 bsp/include/DSP2833x_CpuTimers.h
create mode 100644 bsp/include/DSP2833x_DMA.h
create mode 100644 bsp/include/DSP2833x_DefaultIsr.h
create mode 100644 bsp/include/DSP2833x_DevEmu.h
create mode 100644 bsp/include/DSP2833x_Device.h
create mode 100644 bsp/include/DSP2833x_Dma_defines.h
create mode 100644 bsp/include/DSP2833x_ECan.h
create mode 100644 bsp/include/DSP2833x_ECap.h
create mode 100644 bsp/include/DSP2833x_EPwm.h
create mode 100644 bsp/include/DSP2833x_EPwm_defines.h
create mode 100644 bsp/include/DSP2833x_EQep.h
create mode 100644 bsp/include/DSP2833x_Examples.h
create mode 100644 bsp/include/DSP2833x_GlobalPrototypes.h
create mode 100644 bsp/include/DSP2833x_Gpio.h
create mode 100644 bsp/include/DSP2833x_I2c.h
create mode 100644 bsp/include/DSP2833x_I2c_defines.h
create mode 100644 bsp/include/DSP2833x_Mcbsp.h
create mode 100644 bsp/include/DSP2833x_PieCtrl.h
create mode 100644 bsp/include/DSP2833x_PieVect.h
create mode 100644 bsp/include/DSP2833x_SWPrioritizedIsrLevels.h
create mode 100644 bsp/include/DSP2833x_Sci.h
create mode 100644 bsp/include/DSP2833x_Spi.h
create mode 100644 bsp/include/DSP2833x_SysCtrl.h
create mode 100644 bsp/include/DSP2833x_XIntrupt.h
create mode 100644 bsp/include/DSP2833x_Xintf.h
create mode 100644 bsp/include/DSP28x_Project.h
create mode 100644 bsp/source/DSP2833x_ADC_cal.asm
create mode 100644 bsp/source/DSP2833x_Adc.c
create mode 100644 bsp/source/DSP2833x_CSMPasswords.asm
create mode 100644 bsp/source/DSP2833x_CodeStartBranch.asm
create mode 100644 bsp/source/DSP2833x_CpuTimers.c
create mode 100644 bsp/source/DSP2833x_DBGIER.asm
create mode 100644 bsp/source/DSP2833x_DMA.c
create mode 100644 bsp/source/DSP2833x_DisInt.asm
create mode 100644 bsp/source/DSP2833x_ECan.c
create mode 100644 bsp/source/DSP2833x_ECap.c
create mode 100644 bsp/source/DSP2833x_EPwm.c
create mode 100644 bsp/source/DSP2833x_EQep.c
create mode 100644 bsp/source/DSP2833x_GlobalVariableDefs.c
create mode 100644 bsp/source/DSP2833x_Gpio.c
create mode 100644 bsp/source/DSP2833x_I2C.c
create mode 100644 bsp/source/DSP2833x_Mcbsp.c
create mode 100644 bsp/source/DSP2833x_MemCopy.c
create mode 100644 bsp/source/DSP2833x_PieCtrl.c
create mode 100644 bsp/source/DSP2833x_SWPrioritizedDefaultIsr.c
create mode 100644 bsp/source/DSP2833x_SWPrioritizedPieVect.c
create mode 100644 bsp/source/DSP2833x_Sci.c
create mode 100644 bsp/source/DSP2833x_Spi.c
create mode 100644 bsp/source/DSP2833x_SysCtrl.c
create mode 100644 bsp/source/DSP2833x_Xintf.c
create mode 100644 bsp/source/DSP2833x_usDelay.asm
create mode 100644 cmd/DSP2833x_Headers_nonBIOS.cmd
create mode 100644 cmd/F28335.cmd
create mode 100644 drivers/mcbsp.c
create mode 100644 drivers/mcbsp.h
create mode 100644 drivers/spi.c
create mode 100644 drivers/spi.h
create mode 100644 drivers/sx1255.c
create mode 100644 drivers/sx1255.h
create mode 100644 drivers/sx1255_rx.c
create mode 100644 drivers/sx1255_rx.h
create mode 100644 drivers/sx1255_tx.c
create mode 100644 drivers/sx1255_tx.h
create mode 100644 libs/complex/complex.h
create mode 100644 libs/crc/crc32.c
create mode 100644 libs/crc/crc32.h
create mode 100644 libs/fsk/fsk_ang.c
create mode 100644 libs/fsk/fsk_ang.h
create mode 100644 libs/fsk/fsk_corr.c
create mode 100644 libs/fsk/fsk_corr.h
create mode 100644 libs/fsk/fsk_dc.c
create mode 100644 libs/fsk/fsk_dc.h
create mode 100644 libs/fsk/fsk_decode.c
create mode 100644 libs/fsk/fsk_decode.h
create mode 100644 libs/fsk/fsk_demod.c
create mode 100644 libs/fsk/fsk_demod.h
create mode 100644 libs/fsk/fsk_est.c
create mode 100644 libs/fsk/fsk_est.h
create mode 100644 libs/fsk/fsk_filter.c
create mode 100644 libs/fsk/fsk_filter.h
create mode 100644 libs/fsk/fsk_frame.h
create mode 100644 libs/fsk/fsk_gen.c
create mode 100644 libs/fsk/fsk_gen.h
create mode 100644 libs/fsk/fsk_mod.c
create mode 100644 libs/fsk/fsk_mod.h
create mode 100644 libs/fsk/fsk_norm.c
create mode 100644 libs/fsk/fsk_norm.h
create mode 100644 libs/fsk/fsk_pack.c
create mode 100644 libs/fsk/fsk_pack.h
create mode 100644 libs/fsk/fsk_table.c
create mode 100644 libs/fsk/fsk_table.h
create mode 100644 libs/fsk/fsk_unpack.c
create mode 100644 libs/fsk/fsk_unpack.h
create mode 100644 libs/link/link_rx.c
create mode 100644 libs/link/link_rx.h
create mode 100644 libs/link/link_tx.c
create mode 100644 libs/link/link_tx.h
create mode 100644 libs/safepipe/safepipe.c
create mode 100644 libs/safepipe/safepipe.h
diff --git a/README.md b/README.md
index 6050dd1..e10dd88 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,13 @@
# C2000 SDR
+
+This is a FSK transreceiver based on SDR.
+I use a DSP from TI, which is called F28335, a series of C2000 DSP.
+The IQ modulator/demodulator is SX1255, a very cheap chip originally used in LORA.
+
+Due to the limit of CPU load and the ugly performance of the SX1255,the system can only achieved 9600bps using 433.9M ± 9K.
+
+Maybe when using a better MCU such as RT1052 or F28388D can do a little bit better.
+
+Square root rasied cosine filter is used both in tx and rx to reduce side lobe leakage and maxim the SNR.
+
+At burst mode, the signal in frequency domain looks like this:
\ No newline at end of file
diff --git a/app/init.c b/app/init.c
new file mode 100644
index 0000000..0f6badc
--- /dev/null
+++ b/app/init.c
@@ -0,0 +1,142 @@
+#include "DSP28x_Project.h"
+#include "drivers/sx1255.h"
+
+void Gpio_init(void)
+{
+ EALLOW;
+// GPIO (GENERAL PURPOSE I/O) CONFIG
+//--------------------------------------------------------------------------------------
+//--------------------------------------------------------------------------------------
+// QUICK NOTES on GPIO CONFIG USAGE:
+//----------------------------------
+// If GpioCtrlRegs.GP?MUX?bit.GPIO?= 1, 2 or 3 (i.e. Non GPIO func), then leave
+// rest of lines commented
+// If GpioCtrlRegs.GP?MUX?bit.GPIO?= 0 (i.e. GPIO func), then:
+// 1) uncomment GpioCtrlRegs.GP?DIR.bit.GPIO? = ? and choose pin to be IN or OUT direc.
+// 2) If IN, can leave next two lines commented
+// 3) If OUT, uncomment line with ..GPACLEAR.. to force pin LOW or
+// uncomment line with ..GPASET.. to force pin HIGH
+//--------------------------------------------------------------------------------------
+//--------------------------------------------------------------------------------------
+// GPIO-08 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // 0=GPIO, 1=EPWM5A, 2=CANTX-B, 3=ADCSOC-A
+ GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO8 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-16 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // 0=GPIO, 1=SPISIMO-A, 2=CANTX-B, 3=TZ5
+// GpioCtrlRegs.GPADIR.bit.GPIO16 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO16 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO16 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-17 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // 0=GPIO, 1=SPISOMI-A, 2=CANRX-B, 3=TZ6
+// GpioCtrlRegs.GPADIR.bit.GPIO17 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO17 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO17 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-18 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // 0=GPIO, 1=SPICLK-A, 2=SCITX-B, 3=CANRX-A
+// GpioCtrlRegs.GPADIR.bit.GPIO18 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO18 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO18 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-19 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // 0=GPIO, 1=SPISTE-A, 2=SCIRX-B, 3=CANTX-A
+// GpioCtrlRegs.GPADIR.bit.GPIO19 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO19 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO19 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-20 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // 0=GPIO, 1=EQEPA-1, 2=MDX-A, 3=CANTX-B
+// GpioCtrlRegs.GPADIR.bit.GPIO20 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO20 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO20 = 1; // uncomment if --> Set High initially
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Asynch only
+//--------------------------------------------------------------------------------------
+// GPIO-21 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // 0=GPIO, 1=EQEPB-1, 2=MDR-A, 3=CANRX-B
+// GpioCtrlRegs.GPADIR.bit.GPIO21 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO21 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO21 = 1; // uncomment if --> Set High initially
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch only
+//--------------------------------------------------------------------------------------
+// GPIO-22 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // 0=GPIO, 1=EQEPS-1, 2=MCLKX-A, 3=SCITX-B
+// GpioCtrlRegs.GPADIR.bit.GPIO22 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO22 = 1; // uncomment if --> Set High initially
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch only
+//--------------------------------------------------------------------------------------
+// GPIO-23 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // 0=GPIO, 1=EQEPI-1, 2=MFSX-A, 3=SCIRX-B
+// GpioCtrlRegs.GPADIR.bit.GPIO23 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO23 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO23 = 1; // uncomment if --> Set High initially
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch only
+//--------------------------------------------------------------------------------------
+// GPIO-28 - PIN FUNCTION = SCIRX-A
+ GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // 0=GPIO, 1=SCIRX-A, 2=Resv, 3=Resv
+// GpioCtrlRegs.GPADIR.bit.GPIO28 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO28 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO28 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-29 - PIN FUNCTION = SCITX-A
+ GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // 0=GPIO, 1=SCITXD-A, 2=XA19, 3=Resv
+// GpioCtrlRegs.GPADIR.bit.GPIO29 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO29 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO29 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-30 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // 0=GPIO, 1=CANRX-A, 2=XA18, 3=Resv
+// GpioCtrlRegs.GPADIR.bit.GPIO30 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO30 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO30 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-31 - PIN FUNCTION = LED2 (for Release 1 and up F2833x controlCARDs)
+ GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // 0=GPIO, 1=CANTX-A, 2=XA17, 3=Resv
+// GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; // 1=OUTput, 0=INput
+// GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPASET.bit.GPIO31 = 1; // uncomment if --> Set High initially
+//--------------------------------------------------------------------------------------
+// GPIO-58 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // 0=GPIO, 1=MCLKR-A, 2=XD21, 3=Resv
+// GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPBSET.bit.GPIO58 = 1; // uncomment if --> Set High initially
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch only
+//--------------------------------------------------------------------------------------
+// GPIO-59 - PIN FUNCTION = --Spare--
+ GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // 0=GPIO, 1=MFSR-A, 2=XD20, 3=Resv
+// GpioCtrlRegs.GPBDIR.bit.GPIO59 = 0; // 1=OUTput, 0=INput
+// GpioDataRegs.GPBCLEAR.bit.GPIO59 = 1; // uncomment if --> Set Low initially
+// GpioDataRegs.GPBSET.bit.GPIO59 = 1; // uncomment if --> Set High initially
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch only
+//--------------------------------------------------------------------------------------
+
+ EDIS;
+}
+
+void DeviceInit(void)
+{
+ InitSysCtrl();
+
+ DINT;
+ // Global Disable all Interrupts
+ IER = 0x0000; // Disable CPU interrupts
+ IFR = 0x0000; // Clear all CPU interrupt flags
+
+ MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
+
+ InitPieCtrl();
+
+ InitPieVectTable();
+
+ Gpio_init();
+
+ sx1255_init();
+
+ EINT;
+ ERTM;
+}
diff --git a/app/init.h b/app/init.h
new file mode 100644
index 0000000..3de146a
--- /dev/null
+++ b/app/init.h
@@ -0,0 +1,14 @@
+#ifndef APP_INIT_H_
+#define APP_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void DeviceInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* APP_INIT_H_ */
diff --git a/app/main.c b/app/main.c
new file mode 100644
index 0000000..349db76
--- /dev/null
+++ b/app/main.c
@@ -0,0 +1,22 @@
+#include "DSP28x_Project.h"
+#include "app/init.h"
+#include "libs/safepipe/safepipe.h"
+#include "libs/fsk/fsk_mod.h"
+#include "libs/fsk/fsk_demod.h"
+#include "libs/fsk/fsk_frame.h"
+#include "libs/link/link_rx.h"
+#include "libs/link/link_tx.h"
+
+void main(void)
+{
+ DeviceInit();
+ link_rx_layer_init();
+ link_tx_layer_init();
+ while(1)
+ {
+ link_rx_loop();
+ link_tx_loop();
+ fsk_demod_loop();
+ fsk_mod_loop();
+ }
+}
diff --git a/bsp/include/DSP2833x_Adc.h b/bsp/include/DSP2833x_Adc.h
new file mode 100644
index 0000000..c5294f9
--- /dev/null
+++ b/bsp/include/DSP2833x_Adc.h
@@ -0,0 +1,285 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:51:50 $
+//###########################################################################
+//
+// FILE: DSP2833x_Adc.h
+//
+// TITLE: DSP2833x Device ADC Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_ADC_H
+#define DSP2833x_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// ADC Individual Register Bit Definitions:
+//
+struct ADCTRL1_BITS { // bits description
+ Uint16 rsvd1:4; // 3:0 reserved
+ Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
+ Uint16 SEQ_OVRD:1; // 5 Sequencer override
+ Uint16 CONT_RUN:1; // 6 Continuous run
+ Uint16 CPS:1; // 7 ADC core clock pre-scalar
+ Uint16 ACQ_PS:4; // 11:8 Acquisition window size
+ Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
+ Uint16 RESET:1; // 14 ADC reset
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union ADCTRL1_REG {
+ Uint16 all;
+ struct ADCTRL1_BITS bit;
+};
+
+struct ADCTRL2_BITS { // bits description
+ Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
+ Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
+ Uint16 rsvd2:1; // 4 reserved
+ Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
+ Uint16 RST_SEQ2:1; // 6 Reset SEQ2
+ Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
+ Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
+ Uint16 rsvd3:1; // 9 reserved
+ Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
+ Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
+ Uint16 rsvd4:1; // 12 reserved
+ Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
+ Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
+ Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
+};
+
+union ADCTRL2_REG {
+ Uint16 all;
+ struct ADCTRL2_BITS bit;
+};
+
+struct ADCASEQSR_BITS { // bits description
+ Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
+ Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
+ Uint16 rsvd1:1; // 7 reserved
+ Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+union ADCASEQSR_REG {
+ Uint16 all;
+ struct ADCASEQSR_BITS bit;
+};
+
+struct ADCMAXCONV_BITS { // bits description
+ Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
+ Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
+ Uint16 rsvd1:9; // 15:7 reserved
+};
+
+union ADCMAXCONV_REG {
+ Uint16 all;
+ struct ADCMAXCONV_BITS bit;
+};
+
+struct ADCCHSELSEQ1_BITS { // bits description
+ Uint16 CONV00:4; // 3:0 Conversion selection 00
+ Uint16 CONV01:4; // 7:4 Conversion selection 01
+ Uint16 CONV02:4; // 11:8 Conversion selection 02
+ Uint16 CONV03:4; // 15:12 Conversion selection 03
+};
+
+union ADCCHSELSEQ1_REG{
+ Uint16 all;
+ struct ADCCHSELSEQ1_BITS bit;
+};
+
+struct ADCCHSELSEQ2_BITS { // bits description
+ Uint16 CONV04:4; // 3:0 Conversion selection 04
+ Uint16 CONV05:4; // 7:4 Conversion selection 05
+ Uint16 CONV06:4; // 11:8 Conversion selection 06
+ Uint16 CONV07:4; // 15:12 Conversion selection 07
+};
+
+union ADCCHSELSEQ2_REG{
+ Uint16 all;
+ struct ADCCHSELSEQ2_BITS bit;
+};
+
+struct ADCCHSELSEQ3_BITS { // bits description
+ Uint16 CONV08:4; // 3:0 Conversion selection 08
+ Uint16 CONV09:4; // 7:4 Conversion selection 09
+ Uint16 CONV10:4; // 11:8 Conversion selection 10
+ Uint16 CONV11:4; // 15:12 Conversion selection 11
+};
+
+union ADCCHSELSEQ3_REG{
+ Uint16 all;
+ struct ADCCHSELSEQ3_BITS bit;
+};
+
+struct ADCCHSELSEQ4_BITS { // bits description
+ Uint16 CONV12:4; // 3:0 Conversion selection 12
+ Uint16 CONV13:4; // 7:4 Conversion selection 13
+ Uint16 CONV14:4; // 11:8 Conversion selection 14
+ Uint16 CONV15:4; // 15:12 Conversion selection 15
+};
+
+union ADCCHSELSEQ4_REG {
+ Uint16 all;
+ struct ADCCHSELSEQ4_BITS bit;
+};
+
+struct ADCTRL3_BITS { // bits description
+ Uint16 SMODE_SEL:1; // 0 Sampling mode select
+ Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
+ Uint16 ADCPWDN:1; // 5 ADC powerdown
+ Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union ADCTRL3_REG {
+ Uint16 all;
+ struct ADCTRL3_BITS bit;
+};
+
+struct ADCST_BITS { // bits description
+ Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
+ Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
+ Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
+ Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
+ Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
+ Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
+ Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
+ Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union ADCST_REG {
+ Uint16 all;
+ struct ADCST_BITS bit;
+};
+
+struct ADCREFSEL_BITS { // bits description
+ Uint16 rsvd1:14; // 13:0 reserved
+ Uint16 REF_SEL:2; // 15:14 Reference select
+};
+union ADCREFSEL_REG {
+ Uint16 all;
+ struct ADCREFSEL_BITS bit;
+};
+
+struct ADCOFFTRIM_BITS{ // bits description
+ int16 OFFSET_TRIM:9; // 8:0 Offset Trim
+ Uint16 rsvd1:7; // 15:9 reserved
+};
+
+union ADCOFFTRIM_REG{
+ Uint16 all;
+ struct ADCOFFTRIM_BITS bit;
+};
+
+struct ADC_REGS {
+ union ADCTRL1_REG ADCTRL1; //ADC Control 1
+ union ADCTRL2_REG ADCTRL2; //ADC Control 2
+ union ADCMAXCONV_REG ADCMAXCONV; //Max conversions
+ union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1
+ union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2
+ union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3
+ union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4
+ union ADCASEQSR_REG ADCASEQSR; //Autosequence status register
+ Uint16 ADCRESULT0; //Conversion Result Buffer 0
+ Uint16 ADCRESULT1; //Conversion Result Buffer 1
+ Uint16 ADCRESULT2; //Conversion Result Buffer 2
+ Uint16 ADCRESULT3; //Conversion Result Buffer 3
+ Uint16 ADCRESULT4; //Conversion Result Buffer 4
+ Uint16 ADCRESULT5; //Conversion Result Buffer 5
+ Uint16 ADCRESULT6; //Conversion Result Buffer 6
+ Uint16 ADCRESULT7; //Conversion Result Buffer 7
+ Uint16 ADCRESULT8; //Conversion Result Buffer 8
+ Uint16 ADCRESULT9; //Conversion Result Buffer 9
+ Uint16 ADCRESULT10; //Conversion Result Buffer 10
+ Uint16 ADCRESULT11; //Conversion Result Buffer 11
+ Uint16 ADCRESULT12; //Conversion Result Buffer 12
+ Uint16 ADCRESULT13; //Conversion Result Buffer 13
+ Uint16 ADCRESULT14; //Conversion Result Buffer 14
+ Uint16 ADCRESULT15; //Conversion Result Buffer 15
+ union ADCTRL3_REG ADCTRL3; //ADC Control 3
+ union ADCST_REG ADCST; //ADC Status Register
+ Uint16 rsvd1;
+ Uint16 rsvd2;
+ union ADCREFSEL_REG ADCREFSEL; //Reference Select Register
+ union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register
+};
+
+struct ADC_RESULT_MIRROR_REGS
+{
+ Uint16 ADCRESULT0; // Conversion Result Buffer 0
+ Uint16 ADCRESULT1; // Conversion Result Buffer 1
+ Uint16 ADCRESULT2; // Conversion Result Buffer 2
+ Uint16 ADCRESULT3; // Conversion Result Buffer 3
+ Uint16 ADCRESULT4; // Conversion Result Buffer 4
+ Uint16 ADCRESULT5; // Conversion Result Buffer 5
+ Uint16 ADCRESULT6; // Conversion Result Buffer 6
+ Uint16 ADCRESULT7; // Conversion Result Buffer 7
+ Uint16 ADCRESULT8; // Conversion Result Buffer 8
+ Uint16 ADCRESULT9; // Conversion Result Buffer 9
+ Uint16 ADCRESULT10; // Conversion Result Buffer 10
+ Uint16 ADCRESULT11; // Conversion Result Buffer 11
+ Uint16 ADCRESULT12; // Conversion Result Buffer 12
+ Uint16 ADCRESULT13; // Conversion Result Buffer 13
+ Uint16 ADCRESULT14; // Conversion Result Buffer 14
+ Uint16 ADCRESULT15; // Conversion Result Buffer 15
+};
+
+//
+// ADC External References & Function Declarations:
+//
+extern volatile struct ADC_REGS AdcRegs;
+extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_ADC_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_CpuTimers.h b/bsp/include/DSP2833x_CpuTimers.h
new file mode 100644
index 0000000..25da78c
--- /dev/null
+++ b/bsp/include/DSP2833x_CpuTimers.h
@@ -0,0 +1,255 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: March 20, 2007 15:33:42 $
+//###########################################################################
+//
+// FILE: DSP2833x_CpuTimers.h
+//
+// TITLE: DSP2833x CPU 32-bit Timers Register Definitions.
+//
+// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
+// other realtime operating systems.
+//
+// Do not use these two timers in your application if you ever plan
+// on integrating DSP-BIOS or another realtime OS.
+//
+// For this reason, comment out the code to manipulate these two
+// timers if using DSP-BIOS or another realtime OS.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_CPU_TIMERS_H
+#define DSP2833x_CPU_TIMERS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// CPU Timer Register Bit Definitions
+//
+
+//
+// TCR: Control register bit definitions
+//
+struct TCR_BITS { // bits description
+ Uint16 rsvd1:4; // 3:0 reserved
+ Uint16 TSS:1; // 4 Timer Start/Stop
+ Uint16 TRB:1; // 5 Timer reload
+ Uint16 rsvd2:4; // 9:6 reserved
+ Uint16 SOFT:1; // 10 Emulation modes
+ Uint16 FREE:1; // 11
+ Uint16 rsvd3:2; // 12:13 reserved
+ Uint16 TIE:1; // 14 Output enable
+ Uint16 TIF:1; // 15 Interrupt flag
+};
+
+union TCR_REG {
+ Uint16 all;
+ struct TCR_BITS bit;
+};
+
+//
+// TPR: Pre-scale low bit definitions
+//
+struct TPR_BITS { // bits description
+ Uint16 TDDR:8; // 7:0 Divide-down low
+ Uint16 PSC:8; // 15:8 Prescale counter low
+};
+
+union TPR_REG {
+ Uint16 all;
+ struct TPR_BITS bit;
+};
+
+//
+// TPRH: Pre-scale high bit definitions
+//
+struct TPRH_BITS { // bits description
+ Uint16 TDDRH:8; // 7:0 Divide-down high
+ Uint16 PSCH:8; // 15:8 Prescale counter high
+};
+
+union TPRH_REG {
+ Uint16 all;
+ struct TPRH_BITS bit;
+};
+
+//
+// TIM, TIMH: Timer register definitions
+//
+struct TIM_REG {
+ Uint16 LSW;
+ Uint16 MSW;
+};
+
+union TIM_GROUP {
+ Uint32 all;
+ struct TIM_REG half;
+};
+
+//
+// PRD, PRDH: Period register definitions
+//
+struct PRD_REG {
+ Uint16 LSW;
+ Uint16 MSW;
+};
+
+union PRD_GROUP {
+ Uint32 all;
+ struct PRD_REG half;
+};
+
+//
+// CPU Timer Register File
+//
+struct CPUTIMER_REGS {
+ union TIM_GROUP TIM; // Timer counter register
+ union PRD_GROUP PRD; // Period register
+ union TCR_REG TCR; // Timer control register
+ Uint16 rsvd1; // reserved
+ union TPR_REG TPR; // Timer pre-scale low
+ union TPRH_REG TPRH; // Timer pre-scale high
+};
+
+//
+// CPU Timer Support Variables
+//
+struct CPUTIMER_VARS {
+ volatile struct CPUTIMER_REGS *RegsAddr;
+ Uint32 InterruptCount;
+ float CPUFreqInMHz;
+ float PeriodInUSec;
+};
+
+//
+// Function prototypes and external definitions
+//
+void InitCpuTimers(void);
+void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
+
+extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
+extern struct CPUTIMER_VARS CpuTimer0;
+
+//
+// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS.
+// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS
+//
+extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
+extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
+
+extern struct CPUTIMER_VARS CpuTimer1;
+extern struct CPUTIMER_VARS CpuTimer2;
+
+//
+// Defines for useful Timer Operations:
+//
+
+//
+// Start Timer
+//
+#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
+
+//
+// Stop Timer
+//
+#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
+
+//
+// Reload Timer With period Value
+//
+#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
+
+//
+// Read 32-Bit Timer Value
+//
+#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
+
+//
+// Read 32-Bit Period Value
+//
+#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
+
+//
+// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
+// Do not use these two timers if you ever plan on integrating
+// DSP-BIOS or another realtime OS.
+//
+// For this reason, comment out the code to manipulate these two timers
+// if using DSP-BIOS or another realtime OS.
+//
+
+//
+// Start Timer
+//
+#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
+#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
+
+//
+// Stop Timer
+//
+#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
+#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
+
+//
+// Reload Timer With period Value
+//
+#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
+#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
+
+//
+// Read 32-Bit Timer Value
+//
+#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
+#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
+
+//
+// Read 32-Bit Period Value
+//
+#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
+#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_CPU_TIMERS_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_DMA.h b/bsp/include/DSP2833x_DMA.h
new file mode 100644
index 0000000..4c0ac14
--- /dev/null
+++ b/bsp/include/DSP2833x_DMA.h
@@ -0,0 +1,397 @@
+// TI File $Revision: /main/11 $
+// Checkin $Date: June 23, 2008 11:34:15 $
+//###########################################################################
+//
+// FILE: DSP2833x_DMA.h
+//
+// TITLE: DSP2833x DMA Module Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_DMA_H
+#define DSP2833x_DMA_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Channel MODE register bit definitions
+//
+struct MODE_BITS { // bits description
+ Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
+ // 0 no interrupt
+ // 1 SEQ1INT & ADCSYNC
+ // 2 SEQ2INT
+ // 3 XINT1
+ // 4 XINT2
+ // 5 XINT3
+ // 6 XINT4
+ // 7 XINT5
+ // 8 XINT6
+ // 9 XINT7
+ // 10 XINT13
+ // 11 TINT0
+ // 12 TINT1
+ // 13 TINT2
+ // 14 MXEVTA & MXSYNCA
+ // 15 MREVTA & MRSYNCA
+ // 16 MXEVTB & MXSYNCB
+ // 17 MREVTB & MRSYNCB
+ // 18 ePWM1SOCA
+ // 19 ePWM1SOCB
+ // 20 ePWM2SOCA
+ // 21 ePWM2SOCB
+ // 22 ePWM3SOCA
+ // 23 ePWM3SOCB
+ // 24 ePWM4SOCA
+ // 25 ePWM4SOCB
+ // 26 ePWM5SOCA
+ // 27 ePWM5SOCB
+ // 28 ePWM6SOCA
+ // 29 ePWM6SOCB
+ // 30:31 no interrupt
+ Uint16 rsvd1:2; // 6:5 (R=0:0)
+ Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
+ // 0 overflow interrupt disabled
+ // 1 overflow interrupt enabled
+ Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
+ // 0 peripheral interrupt disabled
+ // 1 peripheral interrupt enabled
+ Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
+ // 0 generate interrupt at beginning of new
+ // transfer
+ // 1 generate interrupt at end of transfer
+ Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
+ // 0 only interrupt event triggers single
+ // burst transfer
+ // 1 first interrupt triggers burst,
+ // continue until transfer count is zero
+ Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W):
+ // 0 stop when transfer count is zero
+ // 1 re-initialize when transfer count is
+ // zero
+ Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
+ // 0 ignore selected interrupt sync signal
+ // 1 enable selected interrupt sync signal
+ Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
+ // 0 sync signal controls source wrap
+ // counter
+ // 1 sync signal controls destination wrap
+ // counter
+ Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
+ // 0 16-bit data transfer size
+ // 1 32-bit data transfer size
+ Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
+ // 0 channel interrupt disabled
+ // 1 channel interrupt enabled
+};
+
+union MODE_REG {
+ Uint16 all;
+ struct MODE_BITS bit;
+};
+
+//
+// Channel CONTROL register bit definitions
+//
+struct CONTROL_BITS { // bits description
+ Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
+ Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
+ Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
+ Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
+ Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
+ Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
+ Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
+ Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
+ Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
+ // 0 no interrupt pending
+ // 1 interrupt pending
+ Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
+ // 0 no sync pending
+ // 1 sync pending
+ Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
+ // 0 no sync error
+ // 1 sync error detected
+ Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
+ // 0 no transfer in progress or pending
+ // 1 transfer in progress or pending
+ Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
+ // 0 no burst in progress or pending
+ // 1 burst in progress or pending
+ Uint16 RUNSTS:1; // 13 Run Status Bit (R):
+ // 0 channel not running or halted
+ // 1 channel running
+ Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
+ // 0 no overflow event
+ // 1 overflow event
+ Uint16 rsvd1:1; // 15 (R=0)
+};
+
+union CONTROL_REG {
+ Uint16 all;
+ struct CONTROL_BITS bit;
+};
+
+//
+// DMACTRL register bit definitions
+//
+struct DMACTRL_BITS { // bits description
+ Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
+ Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
+ Uint16 rsvd1:14; // 15:2 (R=0:0)
+};
+
+union DMACTRL_REG {
+ Uint16 all;
+ struct DMACTRL_BITS bit;
+};
+
+//
+// DEBUGCTRL register bit definitions
+//
+struct DEBUGCTRL_BITS { // bits description
+ Uint16 rsvd1:15; // 14:0 (R=0:0)
+ Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
+ // 0 halt after current read-write operation
+ // 1 continue running
+};
+
+union DEBUGCTRL_REG {
+ Uint16 all;
+ struct DEBUGCTRL_BITS bit;
+};
+
+//
+// PRIORITYCTRL1 register bit definitions
+//
+struct PRIORITYCTRL1_BITS { // bits description
+ Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
+ // 0 same priority as all other channels
+ // 1 highest priority channel
+ Uint16 rsvd1:15; // 15:1 (R=0:0)
+};
+
+union PRIORITYCTRL1_REG {
+ Uint16 all;
+ struct PRIORITYCTRL1_BITS bit;
+};
+
+//
+// PRIORITYSTAT register bit definitions:
+//
+struct PRIORITYSTAT_BITS { // bits description
+ Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
+ // 0,0,0 no channel active
+ // 0,0,1 Ch1 channel active
+ // 0,1,0 Ch2 channel active
+ // 0,1,1 Ch3 channel active
+ // 1,0,0 Ch4 channel active
+ // 1,0,1 Ch5 channel active
+ // 1,1,0 Ch6 channel active
+ Uint16 rsvd1:1; // 3 (R=0)
+ Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
+ // 0,0,0 no channel active & interrupted by Ch1
+ // 0,0,1 cannot occur
+ // 0,1,0 Ch2 was active and interrupted by Ch1
+ // 0,1,1 Ch3 was active and interrupted by Ch1
+ // 1,0,0 Ch4 was active and interrupted by Ch1
+ // 1,0,1 Ch5 was active and interrupted by Ch1
+ // 1,1,0 Ch6 was active and interrupted by Ch1
+ Uint16 rsvd2:9; // 15:7 (R=0:0)
+};
+
+union PRIORITYSTAT_REG {
+ Uint16 all;
+ struct PRIORITYSTAT_BITS bit;
+};
+
+//
+// Burst Size
+//
+struct BURST_SIZE_BITS { // bits description
+ Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
+ Uint16 rsvd1:11; // 15:5 reserved
+};
+
+union BURST_SIZE_REG {
+ Uint16 all;
+ struct BURST_SIZE_BITS bit;
+};
+
+//
+// Burst Count
+//
+struct BURST_COUNT_BITS { // bits description
+ Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
+ Uint16 rsvd1:11; // 15:5 reserved
+};
+
+union BURST_COUNT_REG {
+ Uint16 all;
+ struct BURST_COUNT_BITS bit;
+};
+
+//
+// DMA Channel Registers:
+//
+struct CH_REGS {
+ union MODE_REG MODE; // Mode Register
+ union CONTROL_REG CONTROL; // Control Register
+
+ union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
+ union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
+
+ //
+ // Source Burst Step Register
+ //
+ int16 SRC_BURST_STEP;
+
+ //
+ // Destination Burst Step Register
+ //
+ int16 DST_BURST_STEP;
+
+ Uint16 TRANSFER_SIZE; // Transfer Size Register
+ Uint16 TRANSFER_COUNT; // Transfer Count Register
+
+ //
+ // Source Transfer Step Register
+ //
+ int16 SRC_TRANSFER_STEP;
+
+ //
+ // Destination Transfer Step Register
+ //
+ int16 DST_TRANSFER_STEP;
+
+ Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
+ Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
+ int16 SRC_WRAP_STEP; // Source Wrap Step Register
+
+ //
+ // Destination Wrap Size Register
+ //
+ Uint16 DST_WRAP_SIZE;
+
+ //
+ // Destination Wrap Count Register
+ //
+ Uint16 DST_WRAP_COUNT;
+
+ //
+ // Destination Wrap Step Register
+ //
+ int16 DST_WRAP_STEP;
+
+ //
+ // Source Begin Address Shadow Register
+ //
+ Uint32 SRC_BEG_ADDR_SHADOW;
+
+ //
+ // Source Address Shadow Register
+ //
+ Uint32 SRC_ADDR_SHADOW;
+
+ //
+ // Source Begin Address Active Register
+ //
+ Uint32 SRC_BEG_ADDR_ACTIVE;
+
+ //
+ // Source Address Active Register
+ //
+ Uint32 SRC_ADDR_ACTIVE;
+
+ //
+ // Destination Begin Address Shadow Register
+ //
+ Uint32 DST_BEG_ADDR_SHADOW;
+
+ //
+ // Destination Address Shadow Register
+ //
+ Uint32 DST_ADDR_SHADOW;
+
+ //
+ // Destination Begin Address Active Register
+ //
+ Uint32 DST_BEG_ADDR_ACTIVE;
+
+ //
+ // Destination Address Active Register
+ //
+ Uint32 DST_ADDR_ACTIVE;
+};
+
+//
+// DMA Registers
+//
+struct DMA_REGS {
+ union DMACTRL_REG DMACTRL; // DMA Control Register
+ union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
+ Uint16 rsvd0; // reserved
+ Uint16 rsvd1; //
+ union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
+ Uint16 rsvd2; //
+ union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
+ Uint16 rsvd3[25]; //
+ struct CH_REGS CH1; // DMA Channel 1 Registers
+ struct CH_REGS CH2; // DMA Channel 2 Registers
+ struct CH_REGS CH3; // DMA Channel 3 Registers
+ struct CH_REGS CH4; // DMA Channel 4 Registers
+ struct CH_REGS CH5; // DMA Channel 5 Registers
+ struct CH_REGS CH6; // DMA Channel 6 Registers
+};
+
+//
+// External References & Function Declarations
+//
+extern volatile struct DMA_REGS DmaRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_DMA_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_DefaultIsr.h b/bsp/include/DSP2833x_DefaultIsr.h
new file mode 100644
index 0000000..ff6c336
--- /dev/null
+++ b/bsp/include/DSP2833x_DefaultIsr.h
@@ -0,0 +1,206 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:45:37 $
+//###########################################################################
+//
+// FILE: DSP2833x_DefaultIsr.h
+//
+// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_DEFAULT_ISR_H
+#define DSP2833x_DEFAULT_ISR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Default Interrupt Service Routine Declarations:
+//
+// The following function prototypes are for the
+// default ISR routines used with the default PIE vector table.
+// This default vector table is found in the DSP2833x_PieVect.h
+// file.
+//
+
+//
+// Non-Peripheral Interrupts
+//
+interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
+interrupt void INT14_ISR(void); // CPU-Timer2
+interrupt void DATALOG_ISR(void); // Datalogging interrupt
+interrupt void RTOSINT_ISR(void); // RTOS interrupt
+interrupt void EMUINT_ISR(void); // Emulation interrupt
+interrupt void NMI_ISR(void); // Non-maskable interrupt
+interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
+interrupt void USER1_ISR(void); // User Defined trap 1
+interrupt void USER2_ISR(void); // User Defined trap 2
+interrupt void USER3_ISR(void); // User Defined trap 3
+interrupt void USER4_ISR(void); // User Defined trap 4
+interrupt void USER5_ISR(void); // User Defined trap 5
+interrupt void USER6_ISR(void); // User Defined trap 6
+interrupt void USER7_ISR(void); // User Defined trap 7
+interrupt void USER8_ISR(void); // User Defined trap 8
+interrupt void USER9_ISR(void); // User Defined trap 9
+interrupt void USER10_ISR(void); // User Defined trap 10
+interrupt void USER11_ISR(void); // User Defined trap 11
+interrupt void USER12_ISR(void); // User Defined trap 12
+
+//
+// Group 1 PIE Interrupt Service Routines
+//
+interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
+interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
+interrupt void XINT1_ISR(void); // External interrupt 1
+interrupt void XINT2_ISR(void); // External interrupt 2
+interrupt void ADCINT_ISR(void); // ADC
+interrupt void TINT0_ISR(void); // Timer 0
+interrupt void WAKEINT_ISR(void); // WD
+
+//
+// Group 2 PIE Interrupt Service Routines
+//
+interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
+interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
+interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
+interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
+interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
+interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
+
+//
+// Group 3 PIE Interrupt Service Routines
+//
+interrupt void EPWM1_INT_ISR(void); // EPWM-1
+interrupt void EPWM2_INT_ISR(void); // EPWM-2
+interrupt void EPWM3_INT_ISR(void); // EPWM-3
+interrupt void EPWM4_INT_ISR(void); // EPWM-4
+interrupt void EPWM5_INT_ISR(void); // EPWM-5
+interrupt void EPWM6_INT_ISR(void); // EPWM-6
+
+//
+// Group 4 PIE Interrupt Service Routines
+//
+interrupt void ECAP1_INT_ISR(void); // ECAP-1
+interrupt void ECAP2_INT_ISR(void); // ECAP-2
+interrupt void ECAP3_INT_ISR(void); // ECAP-3
+interrupt void ECAP4_INT_ISR(void); // ECAP-4
+interrupt void ECAP5_INT_ISR(void); // ECAP-5
+interrupt void ECAP6_INT_ISR(void); // ECAP-6
+
+//
+// Group 5 PIE Interrupt Service Routines
+//
+interrupt void EQEP1_INT_ISR(void); // EQEP-1
+interrupt void EQEP2_INT_ISR(void); // EQEP-2
+
+//
+// Group 6 PIE Interrupt Service Routines
+//
+interrupt void SPIRXINTA_ISR(void); // SPI-A
+interrupt void SPITXINTA_ISR(void); // SPI-A
+interrupt void MRINTA_ISR(void); // McBSP-A
+interrupt void MXINTA_ISR(void); // McBSP-A
+interrupt void MRINTB_ISR(void); // McBSP-B
+interrupt void MXINTB_ISR(void); // McBSP-B
+
+//
+// Group 7 PIE Interrupt Service Routines
+//
+interrupt void DINTCH1_ISR(void); // DMA-Channel 1
+interrupt void DINTCH2_ISR(void); // DMA-Channel 2
+interrupt void DINTCH3_ISR(void); // DMA-Channel 3
+interrupt void DINTCH4_ISR(void); // DMA-Channel 4
+interrupt void DINTCH5_ISR(void); // DMA-Channel 5
+interrupt void DINTCH6_ISR(void); // DMA-Channel 6
+
+//
+// Group 8 PIE Interrupt Service Routines
+//
+interrupt void I2CINT1A_ISR(void); // I2C-A
+interrupt void I2CINT2A_ISR(void); // I2C-A
+interrupt void SCIRXINTC_ISR(void); // SCI-C
+interrupt void SCITXINTC_ISR(void); // SCI-C
+
+//
+// Group 9 PIE Interrupt Service Routines
+//
+interrupt void SCIRXINTA_ISR(void); // SCI-A
+interrupt void SCITXINTA_ISR(void); // SCI-A
+interrupt void SCIRXINTB_ISR(void); // SCI-B
+interrupt void SCITXINTB_ISR(void); // SCI-B
+interrupt void ECAN0INTA_ISR(void); // eCAN-A
+interrupt void ECAN1INTA_ISR(void); // eCAN-A
+interrupt void ECAN0INTB_ISR(void); // eCAN-B
+interrupt void ECAN1INTB_ISR(void); // eCAN-B
+
+//
+// Group 10 PIE Interrupt Service Routines
+//
+
+//
+// Group 11 PIE Interrupt Service Routines
+//
+
+//
+// Group 12 PIE Interrupt Service Routines
+//
+interrupt void XINT3_ISR(void); // External interrupt 3
+interrupt void XINT4_ISR(void); // External interrupt 4
+interrupt void XINT5_ISR(void); // External interrupt 5
+interrupt void XINT6_ISR(void); // External interrupt 6
+interrupt void XINT7_ISR(void); // External interrupt 7
+interrupt void LVF_ISR(void); // Latched overflow flag
+interrupt void LUF_ISR(void); // Latched underflow flag
+
+//
+// Catch-all for Reserved Locations For testing purposes
+//
+interrupt void PIE_RESERVED(void); // Reserved for test
+interrupt void rsvd_ISR(void); // for test
+interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_DEFAULT_ISR_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_DevEmu.h b/bsp/include/DSP2833x_DevEmu.h
new file mode 100644
index 0000000..b18a75a
--- /dev/null
+++ b/bsp/include/DSP2833x_DevEmu.h
@@ -0,0 +1,131 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: April 15, 2009 10:05:17 $
+//###########################################################################
+//
+// FILE: DSP2833x_DevEmu.h
+//
+// TITLE: DSP2833x Device Emulation Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_DEV_EMU_H
+#define DSP2833x_DEV_EMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Device Emulation Register Bit Definitions:
+//
+
+//
+// Device Configuration Register Bit Definitions
+//
+struct DEVICECNF_BITS { // bits description
+ Uint16 rsvd1:3; // 2:0 reserved
+ Uint16 VMAPS:1; // 3 VMAP Status
+ Uint16 rsvd2:1; // 4 reserved
+ Uint16 XRSn:1; // 5 XRSn Signal Status
+ Uint16 rsvd3:10; // 15:6
+ Uint16 rsvd4:3; // 18:16
+ Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
+ Uint16 rsvd5:7; // 26:20 reserved
+ Uint16 TRSTN:1; // 27 Status of TRSTn signal
+ Uint16 rsvd6:4; // 31:28 reserved
+};
+
+union DEVICECNF_REG {
+ Uint32 all;
+ struct DEVICECNF_BITS bit;
+};
+
+//
+// CLASSID
+//
+struct CLASSID_BITS { // bits description
+ Uint16 CLASSNO:8; // 7:0 Class Number
+ Uint16 PARTTYPE:8; // 15:8 Part Type
+};
+
+union CLASSID_REG {
+ Uint16 all;
+ struct CLASSID_BITS bit;
+};
+
+struct DEV_EMU_REGS {
+ union DEVICECNF_REG DEVICECNF; // device configuration
+ union CLASSID_REG CLASSID; // Class ID
+ Uint16 REVID; // Device ID
+ Uint16 PROTSTART; // Write-Read protection start
+ Uint16 PROTRANGE; // Write-Read protection range
+ Uint16 rsvd2[202];
+};
+
+//
+// PARTID
+//
+struct PARTID_BITS { // bits description
+ Uint16 PARTNO:8; // 7:0 Part Number
+ Uint16 PARTTYPE:8; // 15:8 Part Type
+};
+
+union PARTID_REG {
+ Uint16 all;
+ struct PARTID_BITS bit;
+};
+
+struct PARTID_REGS {
+ union PARTID_REG PARTID; // Part ID
+};
+
+//
+// Device Emulation Register References & Function Declarations
+//
+extern volatile struct DEV_EMU_REGS DevEmuRegs;
+extern volatile struct PARTID_REGS PartIdRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_DEV_EMU_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Device.h b/bsp/include/DSP2833x_Device.h
new file mode 100644
index 0000000..2db3f8a
--- /dev/null
+++ b/bsp/include/DSP2833x_Device.h
@@ -0,0 +1,239 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: January 22, 2008 16:55:35 $
+//###########################################################################
+//
+// FILE: DSP2833x_Device.h
+//
+// TITLE: DSP2833x Device Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_DEVICE_H
+#define DSP2833x_DEVICE_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Defines
+//
+#define TARGET 1
+
+//
+// User To Select Target Device
+//
+#define DSP28_28335 TARGET // Selects '28335/'28235
+#define DSP28_28334 0 // Selects '28334/'28234
+#define DSP28_28333 0 // Selects '28333/'
+#define DSP28_28332 0 // Selects '28332/'28232
+
+//
+// Common CPU Definitions
+//
+extern cregister volatile unsigned int IFR;
+extern cregister volatile unsigned int IER;
+
+#define EINT asm(" clrc INTM")
+#define DINT asm(" setc INTM")
+#define ERTM asm(" clrc DBGM")
+#define DRTM asm(" setc DBGM")
+#define EALLOW asm(" EALLOW")
+#define EDIS asm(" EDIS")
+#define ESTOP0 asm(" ESTOP0")
+
+#define M_INT1 0x0001
+#define M_INT2 0x0002
+#define M_INT3 0x0004
+#define M_INT4 0x0008
+#define M_INT5 0x0010
+#define M_INT6 0x0020
+#define M_INT7 0x0040
+#define M_INT8 0x0080
+#define M_INT9 0x0100
+#define M_INT10 0x0200
+#define M_INT11 0x0400
+#define M_INT12 0x0800
+#define M_INT13 0x1000
+#define M_INT14 0x2000
+#define M_DLOG 0x4000
+#define M_RTOS 0x8000
+
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+
+//
+// For Portability, User Is Recommended To Use Following Data Type Size
+// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
+//
+#ifndef DSP28_DATA_TYPES
+#define DSP28_DATA_TYPES
+typedef int int16;
+typedef long int32;
+typedef long long int64;
+typedef unsigned int Uint16;
+typedef unsigned long Uint32;
+typedef unsigned long long Uint64;
+typedef float float32;
+typedef long double float64;
+#endif
+
+//
+// Included Peripheral Header Files
+//
+#include "DSP2833x_Adc.h" // ADC Registers
+#include "DSP2833x_DevEmu.h" // Device Emulation Registers
+#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers
+#include "DSP2833x_ECan.h" // Enhanced eCAN Registers
+#include "DSP2833x_ECap.h" // Enhanced Capture
+#include "DSP2833x_DMA.h" // DMA Registers
+#include "DSP2833x_EPwm.h" // Enhanced PWM
+#include "DSP2833x_EQep.h" // Enhanced QEP
+#include "DSP2833x_Gpio.h" // General Purpose I/O Registers
+#include "DSP2833x_I2c.h" // I2C Registers
+#include "DSP2833x_Mcbsp.h" // McBSP
+#include "DSP2833x_PieCtrl.h" // PIE Control Registers
+#include "DSP2833x_PieVect.h" // PIE Vector Table
+#include "DSP2833x_Spi.h" // SPI Registers
+#include "DSP2833x_Sci.h" // SCI Registers
+#include "DSP2833x_SysCtrl.h" // System Control/Power Modes
+#include "DSP2833x_XIntrupt.h" // External Interrupts
+#include "DSP2833x_Xintf.h" // XINTF External Interface
+
+#if DSP28_28335 || DSP28_28333
+#define DSP28_EPWM1 1
+#define DSP28_EPWM2 1
+#define DSP28_EPWM3 1
+#define DSP28_EPWM4 1
+#define DSP28_EPWM5 1
+#define DSP28_EPWM6 1
+#define DSP28_ECAP1 1
+#define DSP28_ECAP2 1
+#define DSP28_ECAP3 1
+#define DSP28_ECAP4 1
+#define DSP28_ECAP5 1
+#define DSP28_ECAP6 1
+#define DSP28_EQEP1 1
+#define DSP28_EQEP2 1
+#define DSP28_ECANA 1
+#define DSP28_ECANB 1
+#define DSP28_MCBSPA 1
+#define DSP28_MCBSPB 1
+#define DSP28_SPIA 1
+#define DSP28_SCIA 1
+#define DSP28_SCIB 1
+#define DSP28_SCIC 1
+#define DSP28_I2CA 1
+#endif // end DSP28_28335 || DSP28_28333
+
+#if DSP28_28334
+#define DSP28_EPWM1 1
+#define DSP28_EPWM2 1
+#define DSP28_EPWM3 1
+#define DSP28_EPWM4 1
+#define DSP28_EPWM5 1
+#define DSP28_EPWM6 1
+#define DSP28_ECAP1 1
+#define DSP28_ECAP2 1
+#define DSP28_ECAP3 1
+#define DSP28_ECAP4 1
+#define DSP28_ECAP5 0
+#define DSP28_ECAP6 0
+#define DSP28_EQEP1 1
+#define DSP28_EQEP2 1
+#define DSP28_ECANA 1
+#define DSP28_ECANB 1
+#define DSP28_MCBSPA 1
+#define DSP28_MCBSPB 1
+#define DSP28_SPIA 1
+#define DSP28_SCIA 1
+#define DSP28_SCIB 1
+#define DSP28_SCIC 1
+#define DSP28_I2CA 1
+#endif // end DSP28_28334
+
+#if DSP28_28332
+#define DSP28_EPWM1 1
+#define DSP28_EPWM2 1
+#define DSP28_EPWM3 1
+#define DSP28_EPWM4 1
+#define DSP28_EPWM5 1
+#define DSP28_EPWM6 1
+#define DSP28_ECAP1 1
+#define DSP28_ECAP2 1
+#define DSP28_ECAP3 1
+#define DSP28_ECAP4 1
+#define DSP28_ECAP5 0
+#define DSP28_ECAP6 0
+#define DSP28_EQEP1 1
+#define DSP28_EQEP2 1
+#define DSP28_ECANA 1
+#define DSP28_ECANB 1
+#define DSP28_MCBSPA 1
+#define DSP28_MCBSPB 0
+#define DSP28_SPIA 1
+#define DSP28_SCIA 1
+#define DSP28_SCIB 1
+#define DSP28_SCIC 0
+#define DSP28_I2CA 1
+#endif // end DSP28_28332
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_DEVICE_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Dma_defines.h b/bsp/include/DSP2833x_Dma_defines.h
new file mode 100644
index 0000000..f898f15
--- /dev/null
+++ b/bsp/include/DSP2833x_Dma_defines.h
@@ -0,0 +1,139 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: August 14, 2007 16:32:29 $
+//###########################################################################
+//
+// FILE: DSP2833x_Dma_defines.h
+//
+// TITLE: #defines used in DMA examples
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_DMA_DEFINES_H
+#define DSP2833x_DMA_DEFINES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// MODE
+//
+// PERINTSEL bits
+//
+#define DMA_SEQ1INT 1
+#define DMA_SEQ2INT 2
+#define DMA_XINT1 3
+#define DMA_XINT2 4
+#define DMA_XINT3 5
+#define DMA_XINT4 6
+#define DMA_XINT5 7
+#define DMA_XINT6 8
+#define DMA_XINT7 9
+#define DMA_XINT13 10
+#define DMA_TINT0 11
+#define DMA_TINT1 12
+#define DMA_TINT2 13
+#define DMA_MXEVTA 14
+#define DMA_MREVTA 15
+#define DMA_MXREVTB 16
+#define DMA_MREVTB 17
+
+//
+// OVERINTE bit
+//
+#define OVRFLOW_DISABLE 0x0
+#define OVEFLOW_ENABLE 0x1
+
+//
+// PERINTE bit
+//
+#define PERINT_DISABLE 0x0
+#define PERINT_ENABLE 0x1
+
+//
+// CHINTMODE bits
+//
+#define CHINT_BEGIN 0x0
+#define CHINT_END 0x1
+
+//
+// ONESHOT bits
+//
+#define ONESHOT_DISABLE 0x0
+#define ONESHOT_ENABLE 0x1
+
+//
+// CONTINOUS bit
+//
+#define CONT_DISABLE 0x0
+#define CONT_ENABLE 0x1
+
+//
+// SYNCE bit
+//
+#define SYNC_DISABLE 0x0
+#define SYNC_ENABLE 0x1
+
+//
+// SYNCSEL bit
+//
+#define SYNC_SRC 0x0
+#define SYNC_DST 0x1
+
+//
+// DATASIZE bit
+//
+#define SIXTEEN_BIT 0x0
+#define THIRTYTWO_BIT 0x1
+
+//
+// CHINTE bit
+//
+#define CHINT_DISABLE 0x0
+#define CHINT_ENABLE 0x1
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // - end of DSP2833x_EPWM_DEFINES_H
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_ECan.h b/bsp/include/DSP2833x_ECan.h
new file mode 100644
index 0000000..196b746
--- /dev/null
+++ b/bsp/include/DSP2833x_ECan.h
@@ -0,0 +1,1287 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: May 7, 2007 16:05:39 $
+//###########################################################################
+//
+// FILE: DSP2833x_ECan.h
+//
+// TITLE: DSP2833x Device eCAN Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_ECAN_H
+#define DSP2833x_ECAN_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// eCAN Control & Status Registers
+//
+
+//
+// eCAN Mailbox enable register (CANME) bit definitions
+//
+struct CANME_BITS { // bit description
+ Uint16 ME0:1; // 0 Enable Mailbox 0
+ Uint16 ME1:1; // 1 Enable Mailbox 1
+ Uint16 ME2:1; // 2 Enable Mailbox 2
+ Uint16 ME3:1; // 3 Enable Mailbox 3
+ Uint16 ME4:1; // 4 Enable Mailbox 4
+ Uint16 ME5:1; // 5 Enable Mailbox 5
+ Uint16 ME6:1; // 6 Enable Mailbox 6
+ Uint16 ME7:1; // 7 Enable Mailbox 7
+ Uint16 ME8:1; // 8 Enable Mailbox 8
+ Uint16 ME9:1; // 9 Enable Mailbox 9
+ Uint16 ME10:1; // 10 Enable Mailbox 10
+ Uint16 ME11:1; // 11 Enable Mailbox 11
+ Uint16 ME12:1; // 12 Enable Mailbox 12
+ Uint16 ME13:1; // 13 Enable Mailbox 13
+ Uint16 ME14:1; // 14 Enable Mailbox 14
+ Uint16 ME15:1; // 15 Enable Mailbox 15
+ Uint16 ME16:1; // 16 Enable Mailbox 16
+ Uint16 ME17:1; // 17 Enable Mailbox 17
+ Uint16 ME18:1; // 18 Enable Mailbox 18
+ Uint16 ME19:1; // 19 Enable Mailbox 19
+ Uint16 ME20:1; // 20 Enable Mailbox 20
+ Uint16 ME21:1; // 21 Enable Mailbox 21
+ Uint16 ME22:1; // 22 Enable Mailbox 22
+ Uint16 ME23:1; // 23 Enable Mailbox 23
+ Uint16 ME24:1; // 24 Enable Mailbox 24
+ Uint16 ME25:1; // 25 Enable Mailbox 25
+ Uint16 ME26:1; // 26 Enable Mailbox 26
+ Uint16 ME27:1; // 27 Enable Mailbox 27
+ Uint16 ME28:1; // 28 Enable Mailbox 28
+ Uint16 ME29:1; // 29 Enable Mailbox 29
+ Uint16 ME30:1; // 30 Enable Mailbox 30
+ Uint16 ME31:1; // 31 Enable Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANME_REG {
+ Uint32 all;
+ struct CANME_BITS bit;
+};
+
+//
+// eCAN Mailbox direction register (CANMD) bit definitions
+//
+struct CANMD_BITS { // bit description
+ Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx
+ Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx
+ Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx
+ Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx
+ Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx
+ Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx
+ Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx
+ Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx
+ Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx
+ Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx
+ Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx
+ Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx
+ Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx
+ Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx
+ Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx
+ Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx
+ Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx
+ Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx
+ Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx
+ Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx
+ Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx
+ Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx
+ Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx
+ Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx
+ Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx
+ Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx
+ Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx
+ Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx
+ Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx
+ Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx
+ Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx
+ Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMD_REG {
+ Uint32 all;
+ struct CANMD_BITS bit;
+};
+
+//
+// eCAN Transmit Request Set register (CANTRS) bit definitions
+//
+struct CANTRS_BITS { // bit description
+ Uint16 TRS0:1; // 0 TRS for Mailbox 0
+ Uint16 TRS1:1; // 1 TRS for Mailbox 1
+ Uint16 TRS2:1; // 2 TRS for Mailbox 2
+ Uint16 TRS3:1; // 3 TRS for Mailbox 3
+ Uint16 TRS4:1; // 4 TRS for Mailbox 4
+ Uint16 TRS5:1; // 5 TRS for Mailbox 5
+ Uint16 TRS6:1; // 6 TRS for Mailbox 6
+ Uint16 TRS7:1; // 7 TRS for Mailbox 7
+ Uint16 TRS8:1; // 8 TRS for Mailbox 8
+ Uint16 TRS9:1; // 9 TRS for Mailbox 9
+ Uint16 TRS10:1; // 10 TRS for Mailbox 10
+ Uint16 TRS11:1; // 11 TRS for Mailbox 11
+ Uint16 TRS12:1; // 12 TRS for Mailbox 12
+ Uint16 TRS13:1; // 13 TRS for Mailbox 13
+ Uint16 TRS14:1; // 14 TRS for Mailbox 14
+ Uint16 TRS15:1; // 15 TRS for Mailbox 15
+ Uint16 TRS16:1; // 16 TRS for Mailbox 16
+ Uint16 TRS17:1; // 17 TRS for Mailbox 17
+ Uint16 TRS18:1; // 18 TRS for Mailbox 18
+ Uint16 TRS19:1; // 19 TRS for Mailbox 19
+ Uint16 TRS20:1; // 20 TRS for Mailbox 20
+ Uint16 TRS21:1; // 21 TRS for Mailbox 21
+ Uint16 TRS22:1; // 22 TRS for Mailbox 22
+ Uint16 TRS23:1; // 23 TRS for Mailbox 23
+ Uint16 TRS24:1; // 24 TRS for Mailbox 24
+ Uint16 TRS25:1; // 25 TRS for Mailbox 25
+ Uint16 TRS26:1; // 26 TRS for Mailbox 26
+ Uint16 TRS27:1; // 27 TRS for Mailbox 27
+ Uint16 TRS28:1; // 28 TRS for Mailbox 28
+ Uint16 TRS29:1; // 29 TRS for Mailbox 29
+ Uint16 TRS30:1; // 30 TRS for Mailbox 30
+ Uint16 TRS31:1; // 31 TRS for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTRS_REG {
+ Uint32 all;
+ struct CANTRS_BITS bit;
+};
+
+//
+// eCAN Transmit Request Reset register (CANTRR) bit definitions
+//
+struct CANTRR_BITS { // bit description
+ Uint16 TRR0:1; // 0 TRR for Mailbox 0
+ Uint16 TRR1:1; // 1 TRR for Mailbox 1
+ Uint16 TRR2:1; // 2 TRR for Mailbox 2
+ Uint16 TRR3:1; // 3 TRR for Mailbox 3
+ Uint16 TRR4:1; // 4 TRR for Mailbox 4
+ Uint16 TRR5:1; // 5 TRR for Mailbox 5
+ Uint16 TRR6:1; // 6 TRR for Mailbox 6
+ Uint16 TRR7:1; // 7 TRR for Mailbox 7
+ Uint16 TRR8:1; // 8 TRR for Mailbox 8
+ Uint16 TRR9:1; // 9 TRR for Mailbox 9
+ Uint16 TRR10:1; // 10 TRR for Mailbox 10
+ Uint16 TRR11:1; // 11 TRR for Mailbox 11
+ Uint16 TRR12:1; // 12 TRR for Mailbox 12
+ Uint16 TRR13:1; // 13 TRR for Mailbox 13
+ Uint16 TRR14:1; // 14 TRR for Mailbox 14
+ Uint16 TRR15:1; // 15 TRR for Mailbox 15
+ Uint16 TRR16:1; // 16 TRR for Mailbox 16
+ Uint16 TRR17:1; // 17 TRR for Mailbox 17
+ Uint16 TRR18:1; // 18 TRR for Mailbox 18
+ Uint16 TRR19:1; // 19 TRR for Mailbox 19
+ Uint16 TRR20:1; // 20 TRR for Mailbox 20
+ Uint16 TRR21:1; // 21 TRR for Mailbox 21
+ Uint16 TRR22:1; // 22 TRR for Mailbox 22
+ Uint16 TRR23:1; // 23 TRR for Mailbox 23
+ Uint16 TRR24:1; // 24 TRR for Mailbox 24
+ Uint16 TRR25:1; // 25 TRR for Mailbox 25
+ Uint16 TRR26:1; // 26 TRR for Mailbox 26
+ Uint16 TRR27:1; // 27 TRR for Mailbox 27
+ Uint16 TRR28:1; // 28 TRR for Mailbox 28
+ Uint16 TRR29:1; // 29 TRR for Mailbox 29
+ Uint16 TRR30:1; // 30 TRR for Mailbox 30
+ Uint16 TRR31:1; // 31 TRR for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTRR_REG {
+ Uint32 all;
+ struct CANTRR_BITS bit;
+};
+
+//
+// eCAN Transmit Acknowledge register (CANTA) bit definitions
+//
+struct CANTA_BITS { // bit description
+ Uint16 TA0:1; // 0 TA for Mailbox 0
+ Uint16 TA1:1; // 1 TA for Mailbox 1
+ Uint16 TA2:1; // 2 TA for Mailbox 2
+ Uint16 TA3:1; // 3 TA for Mailbox 3
+ Uint16 TA4:1; // 4 TA for Mailbox 4
+ Uint16 TA5:1; // 5 TA for Mailbox 5
+ Uint16 TA6:1; // 6 TA for Mailbox 6
+ Uint16 TA7:1; // 7 TA for Mailbox 7
+ Uint16 TA8:1; // 8 TA for Mailbox 8
+ Uint16 TA9:1; // 9 TA for Mailbox 9
+ Uint16 TA10:1; // 10 TA for Mailbox 10
+ Uint16 TA11:1; // 11 TA for Mailbox 11
+ Uint16 TA12:1; // 12 TA for Mailbox 12
+ Uint16 TA13:1; // 13 TA for Mailbox 13
+ Uint16 TA14:1; // 14 TA for Mailbox 14
+ Uint16 TA15:1; // 15 TA for Mailbox 15
+ Uint16 TA16:1; // 16 TA for Mailbox 16
+ Uint16 TA17:1; // 17 TA for Mailbox 17
+ Uint16 TA18:1; // 18 TA for Mailbox 18
+ Uint16 TA19:1; // 19 TA for Mailbox 19
+ Uint16 TA20:1; // 20 TA for Mailbox 20
+ Uint16 TA21:1; // 21 TA for Mailbox 21
+ Uint16 TA22:1; // 22 TA for Mailbox 22
+ Uint16 TA23:1; // 23 TA for Mailbox 23
+ Uint16 TA24:1; // 24 TA for Mailbox 24
+ Uint16 TA25:1; // 25 TA for Mailbox 25
+ Uint16 TA26:1; // 26 TA for Mailbox 26
+ Uint16 TA27:1; // 27 TA for Mailbox 27
+ Uint16 TA28:1; // 28 TA for Mailbox 28
+ Uint16 TA29:1; // 29 TA for Mailbox 29
+ Uint16 TA30:1; // 30 TA for Mailbox 30
+ Uint16 TA31:1; // 31 TA for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTA_REG {
+ Uint32 all;
+ struct CANTA_BITS bit;
+};
+
+//
+// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions
+//
+struct CANAA_BITS { // bit description
+ Uint16 AA0:1; // 0 AA for Mailbox 0
+ Uint16 AA1:1; // 1 AA for Mailbox 1
+ Uint16 AA2:1; // 2 AA for Mailbox 2
+ Uint16 AA3:1; // 3 AA for Mailbox 3
+ Uint16 AA4:1; // 4 AA for Mailbox 4
+ Uint16 AA5:1; // 5 AA for Mailbox 5
+ Uint16 AA6:1; // 6 AA for Mailbox 6
+ Uint16 AA7:1; // 7 AA for Mailbox 7
+ Uint16 AA8:1; // 8 AA for Mailbox 8
+ Uint16 AA9:1; // 9 AA for Mailbox 9
+ Uint16 AA10:1; // 10 AA for Mailbox 10
+ Uint16 AA11:1; // 11 AA for Mailbox 11
+ Uint16 AA12:1; // 12 AA for Mailbox 12
+ Uint16 AA13:1; // 13 AA for Mailbox 13
+ Uint16 AA14:1; // 14 AA for Mailbox 14
+ Uint16 AA15:1; // 15 AA for Mailbox 15
+ Uint16 AA16:1; // 16 AA for Mailbox 16
+ Uint16 AA17:1; // 17 AA for Mailbox 17
+ Uint16 AA18:1; // 18 AA for Mailbox 18
+ Uint16 AA19:1; // 19 AA for Mailbox 19
+ Uint16 AA20:1; // 20 AA for Mailbox 20
+ Uint16 AA21:1; // 21 AA for Mailbox 21
+ Uint16 AA22:1; // 22 AA for Mailbox 22
+ Uint16 AA23:1; // 23 AA for Mailbox 23
+ Uint16 AA24:1; // 24 AA for Mailbox 24
+ Uint16 AA25:1; // 25 AA for Mailbox 25
+ Uint16 AA26:1; // 26 AA for Mailbox 26
+ Uint16 AA27:1; // 27 AA for Mailbox 27
+ Uint16 AA28:1; // 28 AA for Mailbox 28
+ Uint16 AA29:1; // 29 AA for Mailbox 29
+ Uint16 AA30:1; // 30 AA for Mailbox 30
+ Uint16 AA31:1; // 31 AA for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANAA_REG {
+ Uint32 all;
+ struct CANAA_BITS bit;
+};
+
+//
+// eCAN Received Message Pending register (CANRMP) bit definitions
+//
+struct CANRMP_BITS { // bit description
+ Uint16 RMP0:1; // 0 RMP for Mailbox 0
+ Uint16 RMP1:1; // 1 RMP for Mailbox 1
+ Uint16 RMP2:1; // 2 RMP for Mailbox 2
+ Uint16 RMP3:1; // 3 RMP for Mailbox 3
+ Uint16 RMP4:1; // 4 RMP for Mailbox 4
+ Uint16 RMP5:1; // 5 RMP for Mailbox 5
+ Uint16 RMP6:1; // 6 RMP for Mailbox 6
+ Uint16 RMP7:1; // 7 RMP for Mailbox 7
+ Uint16 RMP8:1; // 8 RMP for Mailbox 8
+ Uint16 RMP9:1; // 9 RMP for Mailbox 9
+ Uint16 RMP10:1; // 10 RMP for Mailbox 10
+ Uint16 RMP11:1; // 11 RMP for Mailbox 11
+ Uint16 RMP12:1; // 12 RMP for Mailbox 12
+ Uint16 RMP13:1; // 13 RMP for Mailbox 13
+ Uint16 RMP14:1; // 14 RMP for Mailbox 14
+ Uint16 RMP15:1; // 15 RMP for Mailbox 15
+ Uint16 RMP16:1; // 16 RMP for Mailbox 16
+ Uint16 RMP17:1; // 17 RMP for Mailbox 17
+ Uint16 RMP18:1; // 18 RMP for Mailbox 18
+ Uint16 RMP19:1; // 19 RMP for Mailbox 19
+ Uint16 RMP20:1; // 20 RMP for Mailbox 20
+ Uint16 RMP21:1; // 21 RMP for Mailbox 21
+ Uint16 RMP22:1; // 22 RMP for Mailbox 22
+ Uint16 RMP23:1; // 23 RMP for Mailbox 23
+ Uint16 RMP24:1; // 24 RMP for Mailbox 24
+ Uint16 RMP25:1; // 25 RMP for Mailbox 25
+ Uint16 RMP26:1; // 26 RMP for Mailbox 26
+ Uint16 RMP27:1; // 27 RMP for Mailbox 27
+ Uint16 RMP28:1; // 28 RMP for Mailbox 28
+ Uint16 RMP29:1; // 29 RMP for Mailbox 29
+ Uint16 RMP30:1; // 30 RMP for Mailbox 30
+ Uint16 RMP31:1; // 31 RMP for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANRMP_REG {
+ Uint32 all;
+ struct CANRMP_BITS bit;
+};
+
+//
+// eCAN Received Message Lost register (CANRML) bit definitions
+//
+struct CANRML_BITS { // bit description
+ Uint16 RML0:1; // 0 RML for Mailbox 0
+ Uint16 RML1:1; // 1 RML for Mailbox 1
+ Uint16 RML2:1; // 2 RML for Mailbox 2
+ Uint16 RML3:1; // 3 RML for Mailbox 3
+ Uint16 RML4:1; // 4 RML for Mailbox 4
+ Uint16 RML5:1; // 5 RML for Mailbox 5
+ Uint16 RML6:1; // 6 RML for Mailbox 6
+ Uint16 RML7:1; // 7 RML for Mailbox 7
+ Uint16 RML8:1; // 8 RML for Mailbox 8
+ Uint16 RML9:1; // 9 RML for Mailbox 9
+ Uint16 RML10:1; // 10 RML for Mailbox 10
+ Uint16 RML11:1; // 11 RML for Mailbox 11
+ Uint16 RML12:1; // 12 RML for Mailbox 12
+ Uint16 RML13:1; // 13 RML for Mailbox 13
+ Uint16 RML14:1; // 14 RML for Mailbox 14
+ Uint16 RML15:1; // 15 RML for Mailbox 15
+ Uint16 RML16:1; // 16 RML for Mailbox 16
+ Uint16 RML17:1; // 17 RML for Mailbox 17
+ Uint16 RML18:1; // 18 RML for Mailbox 18
+ Uint16 RML19:1; // 19 RML for Mailbox 19
+ Uint16 RML20:1; // 20 RML for Mailbox 20
+ Uint16 RML21:1; // 21 RML for Mailbox 21
+ Uint16 RML22:1; // 22 RML for Mailbox 22
+ Uint16 RML23:1; // 23 RML for Mailbox 23
+ Uint16 RML24:1; // 24 RML for Mailbox 24
+ Uint16 RML25:1; // 25 RML for Mailbox 25
+ Uint16 RML26:1; // 26 RML for Mailbox 26
+ Uint16 RML27:1; // 27 RML for Mailbox 27
+ Uint16 RML28:1; // 28 RML for Mailbox 28
+ Uint16 RML29:1; // 29 RML for Mailbox 29
+ Uint16 RML30:1; // 30 RML for Mailbox 30
+ Uint16 RML31:1; // 31 RML for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANRML_REG {
+ Uint32 all;
+ struct CANRML_BITS bit;
+};
+
+//
+// eCAN Remote Frame Pending register (CANRFP) bit definitions
+//
+struct CANRFP_BITS { // bit description
+ Uint16 RFP0:1; // 0 RFP for Mailbox 0
+ Uint16 RFP1:1; // 1 RFP for Mailbox 1
+ Uint16 RFP2:1; // 2 RFP for Mailbox 2
+ Uint16 RFP3:1; // 3 RFP for Mailbox 3
+ Uint16 RFP4:1; // 4 RFP for Mailbox 4
+ Uint16 RFP5:1; // 5 RFP for Mailbox 5
+ Uint16 RFP6:1; // 6 RFP for Mailbox 6
+ Uint16 RFP7:1; // 7 RFP for Mailbox 7
+ Uint16 RFP8:1; // 8 RFP for Mailbox 8
+ Uint16 RFP9:1; // 9 RFP for Mailbox 9
+ Uint16 RFP10:1; // 10 RFP for Mailbox 10
+ Uint16 RFP11:1; // 11 RFP for Mailbox 11
+ Uint16 RFP12:1; // 12 RFP for Mailbox 12
+ Uint16 RFP13:1; // 13 RFP for Mailbox 13
+ Uint16 RFP14:1; // 14 RFP for Mailbox 14
+ Uint16 RFP15:1; // 15 RFP for Mailbox 15
+ Uint16 RFP16:1; // 16 RFP for Mailbox 16
+ Uint16 RFP17:1; // 17 RFP for Mailbox 17
+ Uint16 RFP18:1; // 18 RFP for Mailbox 18
+ Uint16 RFP19:1; // 19 RFP for Mailbox 19
+ Uint16 RFP20:1; // 20 RFP for Mailbox 20
+ Uint16 RFP21:1; // 21 RFP for Mailbox 21
+ Uint16 RFP22:1; // 22 RFP for Mailbox 22
+ Uint16 RFP23:1; // 23 RFP for Mailbox 23
+ Uint16 RFP24:1; // 24 RFP for Mailbox 24
+ Uint16 RFP25:1; // 25 RFP for Mailbox 25
+ Uint16 RFP26:1; // 26 RFP for Mailbox 26
+ Uint16 RFP27:1; // 27 RFP for Mailbox 27
+ Uint16 RFP28:1; // 28 RFP for Mailbox 28
+ Uint16 RFP29:1; // 29 RFP for Mailbox 29
+ Uint16 RFP30:1; // 30 RFP for Mailbox 30
+ Uint16 RFP31:1; // 31 RFP for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANRFP_REG {
+ Uint32 all;
+ struct CANRFP_BITS bit;
+};
+
+//
+// eCAN Global Acceptance Mask register (CANGAM) bit definitions
+//
+struct CANGAM_BITS { // bits description
+ Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15
+ Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28
+ Uint16 rsvd:2; // 30:29 reserved
+ Uint16 AMI:1; // 31 AMI bit
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANGAM_REG {
+ Uint32 all;
+ struct CANGAM_BITS bit;
+};
+
+//
+// eCAN Master Control register (CANMC) bit definitions
+//
+struct CANMC_BITS { // bits description
+ Uint16 MBNR:5; // 4:0 MBX # for CDR bit
+ Uint16 SRES:1; // 5 Soft reset
+ Uint16 STM:1; // 6 Self-test mode
+ Uint16 ABO:1; // 7 Auto bus-on
+ Uint16 CDR:1; // 8 Change data request
+ Uint16 WUBA:1; // 9 Wake-up on bus activity
+ Uint16 DBO:1; // 10 Data-byte order
+ Uint16 PDR:1; // 11 Power-down mode request
+ Uint16 CCR:1; // 12 Change configuration request
+ Uint16 SCB:1; // 13 SCC compatibility bit
+ Uint16 TCC:1; // 14 TSC MSB clear bit
+ Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16
+ Uint16 SUSP:1; // 16 SUSPEND free/soft bit
+ Uint16 rsvd:15; // 31:17 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMC_REG {
+ Uint32 all;
+ struct CANMC_BITS bit;
+};
+
+//
+// eCAN Bit -timing configuration register (CANBTC) bit definitions
+//
+struct CANBTC_BITS { // bits description
+ Uint16 TSEG2REG:3; // 2:0 TSEG2 register value
+ Uint16 TSEG1REG:4; // 6:3 TSEG1 register value
+ Uint16 SAM:1; // 7 Sample-point setting
+ Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value
+ Uint16 rsvd1:6; // 15:10 reserved
+ Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value
+ Uint16 rsvd2:8; // 31:24 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANBTC_REG {
+ Uint32 all;
+ struct CANBTC_BITS bit;
+};
+
+//
+// eCAN Error & Status register (CANES) bit definitions
+//
+struct CANES_BITS { // bits description
+ Uint16 TM:1; // 0 Transmit Mode
+ Uint16 RM:1; // 1 Receive Mode
+ Uint16 rsvd1:1; // 2 reserved
+ Uint16 PDA:1; // 3 Power-down acknowledge
+ Uint16 CCE:1; // 4 Change Configuration Enable
+ Uint16 SMA:1; // 5 Suspend Mode Acknowledge
+ Uint16 rsvd2:10; // 15:6 reserved
+ Uint16 EW:1; // 16 Warning status
+ Uint16 EP:1; // 17 Error Passive status
+ Uint16 BO:1; // 18 Bus-off status
+ Uint16 ACKE:1; // 19 Acknowledge error
+ Uint16 SE:1; // 20 Stuff error
+ Uint16 CRCE:1; // 21 CRC error
+ Uint16 SA1:1; // 22 Stuck at Dominant error
+ Uint16 BE:1; // 23 Bit error
+ Uint16 FE:1; // 24 Framing error
+ Uint16 rsvd3:7; // 31:25 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANES_REG {
+ Uint32 all;
+ struct CANES_BITS bit;
+};
+
+//
+// eCAN Transmit Error Counter register (CANTEC) bit definitions
+//
+struct CANTEC_BITS { // bits description
+ Uint16 TEC:8; // 7:0 TEC
+ Uint16 rsvd1:8; // 15:8 reserved
+ Uint16 rsvd2:16; // 31:16 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTEC_REG {
+ Uint32 all;
+ struct CANTEC_BITS bit;
+};
+
+//
+// eCAN Receive Error Counter register (CANREC) bit definitions
+//
+struct CANREC_BITS { // bits description
+ Uint16 REC:8; // 7:0 REC
+ Uint16 rsvd1:8; // 15:8 reserved
+ Uint16 rsvd2:16; // 31:16 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANREC_REG {
+ Uint32 all;
+ struct CANREC_BITS bit;
+};
+
+//
+// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions
+//
+struct CANGIF0_BITS { // bits description
+ Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector
+ Uint16 rsvd1:3; // 7:5 reserved
+ Uint16 WLIF0:1; // 8 Warning level interrupt flag
+ Uint16 EPIF0:1; // 9 Error-passive interrupt flag
+ Uint16 BOIF0:1; // 10 Bus-off interrupt flag
+ Uint16 RMLIF0:1; // 11 Received message lost interrupt flag
+ Uint16 WUIF0:1; // 12 Wakeup interrupt flag
+ Uint16 WDIF0:1; // 13 Write denied interrupt flag
+ Uint16 AAIF0:1; // 14 Abort Ack interrupt flag
+ Uint16 GMIF0:1; // 15 Global MBX interrupt flag
+ Uint16 TCOF0:1; // 16 TSC Overflow flag
+ Uint16 MTOF0:1; // 17 Mailbox Timeout flag
+ Uint16 rsvd2:14; // 31:18 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANGIF0_REG {
+ Uint32 all;
+ struct CANGIF0_BITS bit;
+};
+
+//
+// eCAN Global Interrupt Mask register (CANGIM) bit definitions
+//
+struct CANGIM_BITS { // bits description
+ Uint16 I0EN:1; // 0 Interrupt 0 enable
+ Uint16 I1EN:1; // 1 Interrupt 1 enable
+ Uint16 GIL:1; // 2 Global Interrupt Level
+ Uint16 rsvd1:5; // 7:3 reserved
+ Uint16 WLIM:1; // 8 Warning level interrupt mask
+ Uint16 EPIM:1; // 9 Error-passive interrupt mask
+ Uint16 BOIM:1; // 10 Bus-off interrupt mask
+ Uint16 RMLIM:1; // 11 Received message lost interrupt mask
+ Uint16 WUIM:1; // 12 Wakeup interrupt mask
+ Uint16 WDIM:1; // 13 Write denied interrupt mask
+ Uint16 AAIM:1; // 14 Abort Ack interrupt mask
+ Uint16 rsvd2:1; // 15 reserved
+ Uint16 TCOM:1; // 16 TSC overflow interrupt mask
+ Uint16 MTOM:1; // 17 MBX Timeout interrupt mask
+ Uint16 rsvd3:14; // 31:18 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANGIM_REG {
+ Uint32 all;
+ struct CANGIM_BITS bit;
+};
+
+//
+// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions
+//
+struct CANGIF1_BITS { // bits description
+ Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector
+ Uint16 rsvd1:3; // 7:5 reserved
+ Uint16 WLIF1:1; // 8 Warning level interrupt flag
+ Uint16 EPIF1:1; // 9 Error-passive interrupt flag
+ Uint16 BOIF1:1; // 10 Bus-off interrupt flag
+ Uint16 RMLIF1:1; // 11 Received message lost interrupt flag
+ Uint16 WUIF1:1; // 12 Wakeup interrupt flag
+ Uint16 WDIF1:1; // 13 Write denied interrupt flag
+ Uint16 AAIF1:1; // 14 Abort Ack interrupt flag
+ Uint16 GMIF1:1; // 15 Global MBX interrupt flag
+ Uint16 TCOF1:1; // 16 TSC Overflow flag
+ Uint16 MTOF1:1; // 17 Mailbox Timeout flag
+ Uint16 rsvd2:14; // 31:18 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANGIF1_REG {
+ Uint32 all;
+ struct CANGIF1_BITS bit;
+};
+
+//
+// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions
+//
+struct CANMIM_BITS { // bit description
+ Uint16 MIM0:1; // 0 MIM for Mailbox 0
+ Uint16 MIM1:1; // 1 MIM for Mailbox 1
+ Uint16 MIM2:1; // 2 MIM for Mailbox 2
+ Uint16 MIM3:1; // 3 MIM for Mailbox 3
+ Uint16 MIM4:1; // 4 MIM for Mailbox 4
+ Uint16 MIM5:1; // 5 MIM for Mailbox 5
+ Uint16 MIM6:1; // 6 MIM for Mailbox 6
+ Uint16 MIM7:1; // 7 MIM for Mailbox 7
+ Uint16 MIM8:1; // 8 MIM for Mailbox 8
+ Uint16 MIM9:1; // 9 MIM for Mailbox 9
+ Uint16 MIM10:1; // 10 MIM for Mailbox 10
+ Uint16 MIM11:1; // 11 MIM for Mailbox 11
+ Uint16 MIM12:1; // 12 MIM for Mailbox 12
+ Uint16 MIM13:1; // 13 MIM for Mailbox 13
+ Uint16 MIM14:1; // 14 MIM for Mailbox 14
+ Uint16 MIM15:1; // 15 MIM for Mailbox 15
+ Uint16 MIM16:1; // 16 MIM for Mailbox 16
+ Uint16 MIM17:1; // 17 MIM for Mailbox 17
+ Uint16 MIM18:1; // 18 MIM for Mailbox 18
+ Uint16 MIM19:1; // 19 MIM for Mailbox 19
+ Uint16 MIM20:1; // 20 MIM for Mailbox 20
+ Uint16 MIM21:1; // 21 MIM for Mailbox 21
+ Uint16 MIM22:1; // 22 MIM for Mailbox 22
+ Uint16 MIM23:1; // 23 MIM for Mailbox 23
+ Uint16 MIM24:1; // 24 MIM for Mailbox 24
+ Uint16 MIM25:1; // 25 MIM for Mailbox 25
+ Uint16 MIM26:1; // 26 MIM for Mailbox 26
+ Uint16 MIM27:1; // 27 MIM for Mailbox 27
+ Uint16 MIM28:1; // 28 MIM for Mailbox 28
+ Uint16 MIM29:1; // 29 MIM for Mailbox 29
+ Uint16 MIM30:1; // 30 MIM for Mailbox 30
+ Uint16 MIM31:1; // 31 MIM for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMIM_REG {
+ Uint32 all;
+ struct CANMIM_BITS bit;
+};
+
+//
+// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions
+//
+struct CANMIL_BITS { // bit description
+ Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6
+ Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMIL_REG {
+ Uint32 all;
+ struct CANMIL_BITS bit;
+};
+
+//
+// eCAN Overwrite Protection Control register (CANOPC) bit definitions
+//
+struct CANOPC_BITS { // bit description
+ Uint16 OPC0:1; // 0 OPC for Mailbox 0
+ Uint16 OPC1:1; // 1 OPC for Mailbox 1
+ Uint16 OPC2:1; // 2 OPC for Mailbox 2
+ Uint16 OPC3:1; // 3 OPC for Mailbox 3
+ Uint16 OPC4:1; // 4 OPC for Mailbox 4
+ Uint16 OPC5:1; // 5 OPC for Mailbox 5
+ Uint16 OPC6:1; // 6 OPC for Mailbox 6
+ Uint16 OPC7:1; // 7 OPC for Mailbox 7
+ Uint16 OPC8:1; // 8 OPC for Mailbox 8
+ Uint16 OPC9:1; // 9 OPC for Mailbox 9
+ Uint16 OPC10:1; // 10 OPC for Mailbox 10
+ Uint16 OPC11:1; // 11 OPC for Mailbox 11
+ Uint16 OPC12:1; // 12 OPC for Mailbox 12
+ Uint16 OPC13:1; // 13 OPC for Mailbox 13
+ Uint16 OPC14:1; // 14 OPC for Mailbox 14
+ Uint16 OPC15:1; // 15 OPC for Mailbox 15
+ Uint16 OPC16:1; // 16 OPC for Mailbox 16
+ Uint16 OPC17:1; // 17 OPC for Mailbox 17
+ Uint16 OPC18:1; // 18 OPC for Mailbox 18
+ Uint16 OPC19:1; // 19 OPC for Mailbox 19
+ Uint16 OPC20:1; // 20 OPC for Mailbox 20
+ Uint16 OPC21:1; // 21 OPC for Mailbox 21
+ Uint16 OPC22:1; // 22 OPC for Mailbox 22
+ Uint16 OPC23:1; // 23 OPC for Mailbox 23
+ Uint16 OPC24:1; // 24 OPC for Mailbox 24
+ Uint16 OPC25:1; // 25 OPC for Mailbox 25
+ Uint16 OPC26:1; // 26 OPC for Mailbox 26
+ Uint16 OPC27:1; // 27 OPC for Mailbox 27
+ Uint16 OPC28:1; // 28 OPC for Mailbox 28
+ Uint16 OPC29:1; // 29 OPC for Mailbox 29
+ Uint16 OPC30:1; // 30 OPC for Mailbox 30
+ Uint16 OPC31:1; // 31 OPC for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANOPC_REG {
+ Uint32 all;
+ struct CANOPC_BITS bit;
+};
+
+//
+// eCAN TX I/O Control Register (CANTIOC) bit definitions
+//
+struct CANTIOC_BITS { // bits description
+ Uint16 rsvd1:3; // 2:0 reserved
+ Uint16 TXFUNC:1; // 3 TXFUNC
+ Uint16 rsvd2:12; // 15:4 reserved
+ Uint16 rsvd3:16; // 31:16 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTIOC_REG {
+ Uint32 all;
+ struct CANTIOC_BITS bit;
+};
+
+//
+// eCAN RX I/O Control Register (CANRIOC) bit definitions
+//
+struct CANRIOC_BITS { // bits description
+ Uint16 rsvd1:3; // 2:0 reserved
+ Uint16 RXFUNC:1; // 3 RXFUNC
+ Uint16 rsvd2:12; // 15:4 reserved
+ Uint16 rsvd3:16; // 31:16 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANRIOC_REG {
+ Uint32 all;
+ struct CANRIOC_BITS bit;
+};
+
+//
+// eCAN Time-out Control register (CANTOC) bit definitions
+//
+struct CANTOC_BITS { // bit description
+ Uint16 TOC0:1; // 0 TOC for Mailbox 0
+ Uint16 TOC1:1; // 1 TOC for Mailbox 1
+ Uint16 TOC2:1; // 2 TOC for Mailbox 2
+ Uint16 TOC3:1; // 3 TOC for Mailbox 3
+ Uint16 TOC4:1; // 4 TOC for Mailbox 4
+ Uint16 TOC5:1; // 5 TOC for Mailbox 5
+ Uint16 TOC6:1; // 6 TOC for Mailbox 6
+ Uint16 TOC7:1; // 7 TOC for Mailbox 7
+ Uint16 TOC8:1; // 8 TOC for Mailbox 8
+ Uint16 TOC9:1; // 9 TOC for Mailbox 9
+ Uint16 TOC10:1; // 10 TOC for Mailbox 10
+ Uint16 TOC11:1; // 11 TOC for Mailbox 11
+ Uint16 TOC12:1; // 12 TOC for Mailbox 12
+ Uint16 TOC13:1; // 13 TOC for Mailbox 13
+ Uint16 TOC14:1; // 14 TOC for Mailbox 14
+ Uint16 TOC15:1; // 15 TOC for Mailbox 15
+ Uint16 TOC16:1; // 16 TOC for Mailbox 16
+ Uint16 TOC17:1; // 17 TOC for Mailbox 17
+ Uint16 TOC18:1; // 18 TOC for Mailbox 18
+ Uint16 TOC19:1; // 19 TOC for Mailbox 19
+ Uint16 TOC20:1; // 20 TOC for Mailbox 20
+ Uint16 TOC21:1; // 21 TOC for Mailbox 21
+ Uint16 TOC22:1; // 22 TOC for Mailbox 22
+ Uint16 TOC23:1; // 23 TOC for Mailbox 23
+ Uint16 TOC24:1; // 24 TOC for Mailbox 24
+ Uint16 TOC25:1; // 25 TOC for Mailbox 25
+ Uint16 TOC26:1; // 26 TOC for Mailbox 26
+ Uint16 TOC27:1; // 27 TOC for Mailbox 27
+ Uint16 TOC28:1; // 28 TOC for Mailbox 28
+ Uint16 TOC29:1; // 29 TOC for Mailbox 29
+ Uint16 TOC30:1; // 30 TOC for Mailbox 30
+ Uint16 TOC31:1; // 31 TOC for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTOC_REG {
+ Uint32 all;
+ struct CANTOC_BITS bit;
+};
+
+//
+// eCAN Time-out Status register (CANTOS) bit definitions
+//
+struct CANTOS_BITS { // bit description
+ Uint16 TOS0:1; // 0 TOS for Mailbox 0
+ Uint16 TOS1:1; // 1 TOS for Mailbox 1
+ Uint16 TOS2:1; // 2 TOS for Mailbox 2
+ Uint16 TOS3:1; // 3 TOS for Mailbox 3
+ Uint16 TOS4:1; // 4 TOS for Mailbox 4
+ Uint16 TOS5:1; // 5 TOS for Mailbox 5
+ Uint16 TOS6:1; // 6 TOS for Mailbox 6
+ Uint16 TOS7:1; // 7 TOS for Mailbox 7
+ Uint16 TOS8:1; // 8 TOS for Mailbox 8
+ Uint16 TOS9:1; // 9 TOS for Mailbox 9
+ Uint16 TOS10:1; // 10 TOS for Mailbox 10
+ Uint16 TOS11:1; // 11 TOS for Mailbox 11
+ Uint16 TOS12:1; // 12 TOS for Mailbox 12
+ Uint16 TOS13:1; // 13 TOS for Mailbox 13
+ Uint16 TOS14:1; // 14 TOS for Mailbox 14
+ Uint16 TOS15:1; // 15 TOS for Mailbox 15
+ Uint16 TOS16:1; // 16 TOS for Mailbox 16
+ Uint16 TOS17:1; // 17 TOS for Mailbox 17
+ Uint16 TOS18:1; // 18 TOS for Mailbox 18
+ Uint16 TOS19:1; // 19 TOS for Mailbox 19
+ Uint16 TOS20:1; // 20 TOS for Mailbox 20
+ Uint16 TOS21:1; // 21 TOS for Mailbox 21
+ Uint16 TOS22:1; // 22 TOS for Mailbox 22
+ Uint16 TOS23:1; // 23 TOS for Mailbox 23
+ Uint16 TOS24:1; // 24 TOS for Mailbox 24
+ Uint16 TOS25:1; // 25 TOS for Mailbox 25
+ Uint16 TOS26:1; // 26 TOS for Mailbox 26
+ Uint16 TOS27:1; // 27 TOS for Mailbox 27
+ Uint16 TOS28:1; // 28 TOS for Mailbox 28
+ Uint16 TOS29:1; // 29 TOS for Mailbox 29
+ Uint16 TOS30:1; // 30 TOS for Mailbox 30
+ Uint16 TOS31:1; // 31 TOS for Mailbox 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANTOS_REG {
+ Uint32 all;
+ struct CANTOS_BITS bit;
+};
+
+//
+// eCAN Control & Status register file
+//
+struct ECAN_REGS {
+ union CANME_REG CANME; // Mailbox Enable
+ union CANMD_REG CANMD; // Mailbox Direction
+ union CANTRS_REG CANTRS; // Transmit Request Set
+ union CANTRR_REG CANTRR; // Transmit Request Reset
+ union CANTA_REG CANTA; // Transmit Acknowledge
+ union CANAA_REG CANAA; // Abort Acknowledge
+ union CANRMP_REG CANRMP; // Received Message Pending
+ union CANRML_REG CANRML; // Received Message Lost
+ union CANRFP_REG CANRFP; // Remote Frame Pending
+ union CANGAM_REG CANGAM; // Global Acceptance Mask
+ union CANMC_REG CANMC; // Master Control
+ union CANBTC_REG CANBTC; // Bit Timing
+ union CANES_REG CANES; // Error Status
+ union CANTEC_REG CANTEC; // Transmit Error Counter
+ union CANREC_REG CANREC; // Receive Error Counter
+ union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0
+ union CANGIM_REG CANGIM; // Global Interrupt Mask 0
+ union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1
+ union CANMIM_REG CANMIM; // Mailbox Interrupt Mask
+ union CANMIL_REG CANMIL; // Mailbox Interrupt Level
+ union CANOPC_REG CANOPC; // Overwrite Protection Control
+ union CANTIOC_REG CANTIOC; // TX I/O Control
+ union CANRIOC_REG CANRIOC; // RX I/O Control
+ Uint32 CANTSC; // Time-stamp counter
+ union CANTOC_REG CANTOC; // Time-out Control
+ union CANTOS_REG CANTOS; // Time-out Status
+};
+
+//
+// eCAN Mailbox Registers
+//
+
+//
+// eCAN Message ID (MSGID) bit definitions
+//
+struct CANMSGID_BITS { // bits description
+ Uint16 EXTMSGID_L:16; // 0:15
+ Uint16 EXTMSGID_H:2; // 16:17
+ Uint16 STDMSGID:11; // 18:28
+ Uint16 AAM:1; // 29
+ Uint16 AME:1; // 30
+ Uint16 IDE:1; // 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMSGID_REG {
+ Uint32 all;
+ struct CANMSGID_BITS bit;
+};
+
+//
+// eCAN Message Control Register (MSGCTRL) bit definitions
+//
+struct CANMSGCTRL_BITS { // bits description
+ Uint16 DLC:4; // 0:3
+ Uint16 RTR:1; // 4
+ Uint16 rsvd1:3; // 7:5 reserved
+ Uint16 TPL:5; // 12:8
+ Uint16 rsvd2:3; // 15:13 reserved
+ Uint16 rsvd3:16; // 31:16 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMSGCTRL_REG {
+ Uint32 all;
+ struct CANMSGCTRL_BITS bit;
+};
+
+//
+// eCAN Message Data Register low (MDR_L) word definitions
+//
+struct CANMDL_WORDS { // bits description
+ Uint16 LOW_WORD:16; // 0:15
+ Uint16 HI_WORD:16; // 31:16
+};
+
+//
+// eCAN Message Data Register low (MDR_L) byte definitions
+//
+struct CANMDL_BYTES { // bits description
+ Uint16 BYTE3:8; // 31:24
+ Uint16 BYTE2:8; // 23:16
+ Uint16 BYTE1:8; // 15:8
+ Uint16 BYTE0:8; // 7:0
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMDL_REG {
+ Uint32 all;
+ struct CANMDL_WORDS word;
+ struct CANMDL_BYTES byte;
+};
+
+//
+// eCAN Message Data Register high (MDR_H) word definitions
+//
+struct CANMDH_WORDS { // bits description
+ Uint16 LOW_WORD:16; // 0:15
+ Uint16 HI_WORD:16; // 31:16
+};
+
+//
+// eCAN Message Data Register low (MDR_H) byte definitions
+//
+struct CANMDH_BYTES { // bits description
+ Uint16 BYTE7:8; // 63:56
+ Uint16 BYTE6:8; // 55:48
+ Uint16 BYTE5:8; // 47:40
+ Uint16 BYTE4:8; // 39:32
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANMDH_REG {
+ Uint32 all;
+ struct CANMDH_WORDS word;
+ struct CANMDH_BYTES byte;
+};
+
+struct MBOX {
+ union CANMSGID_REG MSGID;
+ union CANMSGCTRL_REG MSGCTRL;
+ union CANMDL_REG MDL;
+ union CANMDH_REG MDH;
+};
+
+//
+// eCAN Mailboxes
+//
+struct ECAN_MBOXES {
+ struct MBOX MBOX0;
+ struct MBOX MBOX1;
+ struct MBOX MBOX2;
+ struct MBOX MBOX3;
+ struct MBOX MBOX4;
+ struct MBOX MBOX5;
+ struct MBOX MBOX6;
+ struct MBOX MBOX7;
+ struct MBOX MBOX8;
+ struct MBOX MBOX9;
+ struct MBOX MBOX10;
+ struct MBOX MBOX11;
+ struct MBOX MBOX12;
+ struct MBOX MBOX13;
+ struct MBOX MBOX14;
+ struct MBOX MBOX15;
+ struct MBOX MBOX16;
+ struct MBOX MBOX17;
+ struct MBOX MBOX18;
+ struct MBOX MBOX19;
+ struct MBOX MBOX20;
+ struct MBOX MBOX21;
+ struct MBOX MBOX22;
+ struct MBOX MBOX23;
+ struct MBOX MBOX24;
+ struct MBOX MBOX25;
+ struct MBOX MBOX26;
+ struct MBOX MBOX27;
+ struct MBOX MBOX28;
+ struct MBOX MBOX29;
+ struct MBOX MBOX30;
+ struct MBOX MBOX31;
+};
+
+//
+// eCAN Local Acceptance Mask (LAM) bit definitions
+//
+struct CANLAM_BITS { // bits description
+ Uint16 LAM_L:16; // 0:15
+ Uint16 LAM_H:13; // 16:28
+ Uint16 rsvd1:2; // 29:30 reserved
+ Uint16 LAMI:1; // 31
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CANLAM_REG {
+ Uint32 all;
+ struct CANLAM_BITS bit;
+};
+
+//
+// eCAN Local Acceptance Masks
+//
+
+//
+// eCAN LAM File
+//
+struct LAM_REGS {
+ union CANLAM_REG LAM0;
+ union CANLAM_REG LAM1;
+ union CANLAM_REG LAM2;
+ union CANLAM_REG LAM3;
+ union CANLAM_REG LAM4;
+ union CANLAM_REG LAM5;
+ union CANLAM_REG LAM6;
+ union CANLAM_REG LAM7;
+ union CANLAM_REG LAM8;
+ union CANLAM_REG LAM9;
+ union CANLAM_REG LAM10;
+ union CANLAM_REG LAM11;
+ union CANLAM_REG LAM12;
+ union CANLAM_REG LAM13;
+ union CANLAM_REG LAM14;
+ union CANLAM_REG LAM15;
+ union CANLAM_REG LAM16;
+ union CANLAM_REG LAM17;
+ union CANLAM_REG LAM18;
+ union CANLAM_REG LAM19;
+ union CANLAM_REG LAM20;
+ union CANLAM_REG LAM21;
+ union CANLAM_REG LAM22;
+ union CANLAM_REG LAM23;
+ union CANLAM_REG LAM24;
+ union CANLAM_REG LAM25;
+ union CANLAM_REG LAM26;
+ union CANLAM_REG LAM27;
+ union CANLAM_REG LAM28;
+ union CANLAM_REG LAM29;
+ union CANLAM_REG LAM30;
+ union CANLAM_REG LAM31;
+};
+
+//
+// Mailbox MOTS File
+//
+struct MOTS_REGS {
+ Uint32 MOTS0;
+ Uint32 MOTS1;
+ Uint32 MOTS2;
+ Uint32 MOTS3;
+ Uint32 MOTS4;
+ Uint32 MOTS5;
+ Uint32 MOTS6;
+ Uint32 MOTS7;
+ Uint32 MOTS8;
+ Uint32 MOTS9;
+ Uint32 MOTS10;
+ Uint32 MOTS11;
+ Uint32 MOTS12;
+ Uint32 MOTS13;
+ Uint32 MOTS14;
+ Uint32 MOTS15;
+ Uint32 MOTS16;
+ Uint32 MOTS17;
+ Uint32 MOTS18;
+ Uint32 MOTS19;
+ Uint32 MOTS20;
+ Uint32 MOTS21;
+ Uint32 MOTS22;
+ Uint32 MOTS23;
+ Uint32 MOTS24;
+ Uint32 MOTS25;
+ Uint32 MOTS26;
+ Uint32 MOTS27;
+ Uint32 MOTS28;
+ Uint32 MOTS29;
+ Uint32 MOTS30;
+ Uint32 MOTS31;
+};
+
+//
+// Mailbox MOTO File
+//
+struct MOTO_REGS {
+ Uint32 MOTO0;
+ Uint32 MOTO1;
+ Uint32 MOTO2;
+ Uint32 MOTO3;
+ Uint32 MOTO4;
+ Uint32 MOTO5;
+ Uint32 MOTO6;
+ Uint32 MOTO7;
+ Uint32 MOTO8;
+ Uint32 MOTO9;
+ Uint32 MOTO10;
+ Uint32 MOTO11;
+ Uint32 MOTO12;
+ Uint32 MOTO13;
+ Uint32 MOTO14;
+ Uint32 MOTO15;
+ Uint32 MOTO16;
+ Uint32 MOTO17;
+ Uint32 MOTO18;
+ Uint32 MOTO19;
+ Uint32 MOTO20;
+ Uint32 MOTO21;
+ Uint32 MOTO22;
+ Uint32 MOTO23;
+ Uint32 MOTO24;
+ Uint32 MOTO25;
+ Uint32 MOTO26;
+ Uint32 MOTO27;
+ Uint32 MOTO28;
+ Uint32 MOTO29;
+ Uint32 MOTO30;
+ Uint32 MOTO31;
+};
+
+//
+// eCAN External References & Function Declarations
+//
+extern volatile struct ECAN_REGS ECanaRegs;
+extern volatile struct ECAN_MBOXES ECanaMboxes;
+extern volatile struct LAM_REGS ECanaLAMRegs;
+extern volatile struct MOTO_REGS ECanaMOTORegs;
+extern volatile struct MOTS_REGS ECanaMOTSRegs;
+
+extern volatile struct ECAN_REGS ECanbRegs;
+extern volatile struct ECAN_MBOXES ECanbMboxes;
+extern volatile struct LAM_REGS ECanbLAMRegs;
+extern volatile struct MOTO_REGS ECanbMOTORegs;
+extern volatile struct MOTS_REGS ECanbMOTSRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_ECAN.H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_ECap.h b/bsp/include/DSP2833x_ECap.h
new file mode 100644
index 0000000..eae9e7d
--- /dev/null
+++ b/bsp/include/DSP2833x_ECap.h
@@ -0,0 +1,179 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:07 $
+//###########################################################################
+//
+// FILE: DSP2833x_ECap.h
+//
+// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_ECAP_H
+#define DSP2833x_ECAP_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Capture control register 1 bit definitions
+//
+struct ECCTL1_BITS { // bits description
+ Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
+ Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
+ Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
+ Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
+ Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
+ Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
+ Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
+ Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
+ Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap
+ // Event
+ Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
+ Uint16 FREE_SOFT:2; // 15:14 Emulation mode
+};
+
+union ECCTL1_REG {
+ Uint16 all;
+ struct ECCTL1_BITS bit;
+};
+
+//
+// In V1.1 the STOPVALUE bit field was changed to
+// STOP_WRAP. This correlated to a silicon change from
+// F2833x Rev 0 to Rev A.
+//
+
+//
+// Capture control register 2 bit definitions
+//
+struct ECCTL2_BITS { // bits description
+ Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
+ Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
+ Uint16 REARM:1; // 3 One-shot re-arm
+ Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
+ Uint16 SYNCI_EN:1; // 5 Counter sync-in select
+ Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
+ Uint16 SWSYNC:1; // 8 SW forced counter sync
+ Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
+ Uint16 APWMPOL:1; // 10 APWM output polarity select
+ Uint16 rsvd1:5; // 15:11
+};
+
+union ECCTL2_REG {
+ Uint16 all;
+ struct ECCTL2_BITS bit;
+};
+
+//
+// ECAP interrupt enable register bit definitions
+//
+struct ECEINT_BITS { // bits description
+ Uint16 rsvd1:1; // 0 reserved
+ Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
+ Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
+ Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
+ Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
+ Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
+ Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
+ Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
+ Uint16 rsvd2:8; // 15:8 reserved
+};
+
+union ECEINT_REG {
+ Uint16 all;
+ struct ECEINT_BITS bit;
+};
+
+//
+// ECAP interrupt flag register bit definitions
+//
+struct ECFLG_BITS { // bits description
+ Uint16 INT:1; // 0 Global Flag
+ Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
+ Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
+ Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
+ Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
+ Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
+ Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag
+ Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag
+ Uint16 rsvd2:8; // 15:8 reserved
+};
+
+union ECFLG_REG {
+ Uint16 all;
+ struct ECFLG_BITS bit;
+};
+
+struct ECAP_REGS {
+ Uint32 TSCTR; // Time stamp counter
+ Uint32 CTRPHS; // Counter phase
+ Uint32 CAP1; // Capture 1
+ Uint32 CAP2; // Capture 2
+ Uint32 CAP3; // Capture 3
+ Uint32 CAP4; // Capture 4
+ Uint16 rsvd1[8]; // reserved
+ union ECCTL1_REG ECCTL1; // Capture Control Reg 1
+ union ECCTL2_REG ECCTL2; // Capture Control Reg 2
+ union ECEINT_REG ECEINT; // ECAP interrupt enable
+ union ECFLG_REG ECFLG; // ECAP interrupt flags
+ union ECFLG_REG ECCLR; // ECAP interrupt clear
+ union ECEINT_REG ECFRC; // ECAP interrupt force
+ Uint16 rsvd2[6]; // reserved
+};
+
+//
+// GPI/O External References & Function Declarations
+//
+extern volatile struct ECAP_REGS ECap1Regs;
+extern volatile struct ECAP_REGS ECap2Regs;
+extern volatile struct ECAP_REGS ECap3Regs;
+extern volatile struct ECAP_REGS ECap4Regs;
+extern volatile struct ECAP_REGS ECap5Regs;
+extern volatile struct ECAP_REGS ECap6Regs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_ECAP_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_EPwm.h b/bsp/include/DSP2833x_EPwm.h
new file mode 100644
index 0000000..326557f
--- /dev/null
+++ b/bsp/include/DSP2833x_EPwm.h
@@ -0,0 +1,465 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:10 $
+//###########################################################################
+//
+// FILE: DSP2833x_EPwm.h
+//
+// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_EPWM_H
+#define DSP2833x_EPWM_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Time base control register bit definitions
+//
+struct TBCTL_BITS { // bits description
+ Uint16 CTRMODE:2; // 1:0 Counter Mode
+ Uint16 PHSEN:1; // 2 Phase load enable
+ Uint16 PRDLD:1; // 3 Active period load
+ Uint16 SYNCOSEL:2; // 5:4 Sync output select
+ Uint16 SWFSYNC:1; // 6 Software force sync pulse
+ Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
+ Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
+ Uint16 PHSDIR:1; // 13 Phase Direction
+ Uint16 FREE_SOFT:2; // 15:14 Emulation mode
+};
+
+union TBCTL_REG {
+ Uint16 all;
+ struct TBCTL_BITS bit;
+};
+
+//
+// Time base status register bit definitions
+//
+struct TBSTS_BITS { // bits description
+ Uint16 CTRDIR:1; // 0 Counter direction status
+ Uint16 SYNCI:1; // 1 External input sync status
+ Uint16 CTRMAX:1; // 2 Counter max latched status
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union TBSTS_REG {
+ Uint16 all;
+ struct TBSTS_BITS bit;
+};
+
+//
+// Compare control register bit definitions
+//
+struct CMPCTL_BITS { // bits description
+ Uint16 LOADAMODE:2; // 0:1 Active compare A
+ Uint16 LOADBMODE:2; // 3:2 Active compare B
+ Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
+ Uint16 rsvd1:1; // 5 reserved
+ Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
+ Uint16 rsvd2:1; // 7 reserved
+ Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
+ Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
+ Uint16 rsvd3:6; // 15:10 reserved
+};
+
+union CMPCTL_REG {
+ Uint16 all;
+ struct CMPCTL_BITS bit;
+};
+
+//
+// Action qualifier register bit definitions
+//
+struct AQCTL_BITS { // bits description
+ Uint16 ZRO:2; // 1:0 Action Counter = Zero
+ Uint16 PRD:2; // 3:2 Action Counter = Period
+ Uint16 CAU:2; // 5:4 Action Counter = Compare A up
+ Uint16 CAD:2; // 7:6 Action Counter = Compare A down
+ Uint16 CBU:2; // 9:8 Action Counter = Compare B up
+ Uint16 CBD:2; // 11:10 Action Counter = Compare B down
+ Uint16 rsvd:4; // 15:12 reserved
+};
+
+union AQCTL_REG {
+ Uint16 all;
+ struct AQCTL_BITS bit;
+};
+
+//
+// Action qualifier SW force register bit definitions
+//
+struct AQSFRC_BITS { // bits description
+ Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
+ Uint16 OTSFA:1; // 2 One-time SW Force A output
+ Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
+ Uint16 OTSFB:1; // 5 One-time SW Force A output
+ Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union AQSFRC_REG {
+ Uint16 all;
+ struct AQSFRC_BITS bit;
+};
+
+//
+// Action qualifier continuous SW force register bit definitions
+//
+struct AQCSFRC_BITS { // bits description
+ Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
+ Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
+ Uint16 rsvd1:12; // 15:4 reserved
+};
+
+union AQCSFRC_REG {
+ Uint16 all;
+ struct AQCSFRC_BITS bit;
+};
+
+//
+// As of version 1.1
+// Changed the MODE bit-field to OUT_MODE
+// Added the bit-field IN_MODE
+// This corresponds to changes in silicon as of F2833x devices
+// Rev A silicon.
+//
+
+//
+// Dead-band generator control register bit definitions
+//
+struct DBCTL_BITS { // bits description
+ Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
+ Uint16 POLSEL:2; // 3:2 Polarity Select Control
+ Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
+ Uint16 rsvd1:10; // 15:4 reserved
+};
+
+union DBCTL_REG {
+ Uint16 all;
+ struct DBCTL_BITS bit;
+};
+
+//
+// Trip zone select register bit definitions
+//
+struct TZSEL_BITS { // bits description
+ Uint16 CBC1:1; // 0 TZ1 CBC select
+ Uint16 CBC2:1; // 1 TZ2 CBC select
+ Uint16 CBC3:1; // 2 TZ3 CBC select
+ Uint16 CBC4:1; // 3 TZ4 CBC select
+ Uint16 CBC5:1; // 4 TZ5 CBC select
+ Uint16 CBC6:1; // 5 TZ6 CBC select
+ Uint16 rsvd1:2; // 7:6 reserved
+ Uint16 OSHT1:1; // 8 One-shot TZ1 select
+ Uint16 OSHT2:1; // 9 One-shot TZ2 select
+ Uint16 OSHT3:1; // 10 One-shot TZ3 select
+ Uint16 OSHT4:1; // 11 One-shot TZ4 select
+ Uint16 OSHT5:1; // 12 One-shot TZ5 select
+ Uint16 OSHT6:1; // 13 One-shot TZ6 select
+ Uint16 rsvd2:2; // 15:14 reserved
+};
+
+union TZSEL_REG {
+ Uint16 all;
+ struct TZSEL_BITS bit;
+};
+
+//
+// Trip zone control register bit definitions
+//
+struct TZCTL_BITS { // bits description
+ Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
+ Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
+ Uint16 rsvd:12; // 15:4 reserved
+};
+
+union TZCTL_REG {
+ Uint16 all;
+ struct TZCTL_BITS bit;
+};
+
+//
+// Trip zone control register bit definitions
+//
+struct TZEINT_BITS { // bits description
+ Uint16 rsvd1:1; // 0 reserved
+ Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
+ Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
+ Uint16 rsvd2:13; // 15:3 reserved
+};
+
+union TZEINT_REG {
+ Uint16 all;
+ struct TZEINT_BITS bit;
+};
+
+//
+// Trip zone flag register bit definitions
+//
+struct TZFLG_BITS { // bits description
+ Uint16 INT:1; // 0 Global status
+ Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
+ Uint16 OST:1; // 2 Trip Zones One Shot Int
+ Uint16 rsvd2:13; // 15:3 reserved
+};
+
+union TZFLG_REG {
+ Uint16 all;
+ struct TZFLG_BITS bit;
+};
+
+//
+// Trip zone flag clear register bit definitions
+//
+struct TZCLR_BITS { // bits description
+ Uint16 INT:1; // 0 Global status
+ Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
+ Uint16 OST:1; // 2 Trip Zones One Shot Int
+ Uint16 rsvd2:13; // 15:3 reserved
+};
+
+union TZCLR_REG {
+ Uint16 all;
+ struct TZCLR_BITS bit;
+};
+
+//
+// Trip zone flag force register bit definitions
+//
+struct TZFRC_BITS { // bits description
+ Uint16 rsvd1:1; // 0 reserved
+ Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
+ Uint16 OST:1; // 2 Trip Zones One Shot Int
+ Uint16 rsvd2:13; // 15:3 reserved
+};
+
+union TZFRC_REG {
+ Uint16 all;
+ struct TZFRC_BITS bit;
+};
+
+//
+// Event trigger select register bit definitions
+//
+struct ETSEL_BITS { // bits description
+ Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
+ Uint16 INTEN:1; // 3 EPWMxINTn Enable
+ Uint16 rsvd1:4; // 7:4 reserved
+ Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
+ Uint16 SOCAEN:1; // 11 Start of conversion A Enable
+ Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
+ Uint16 SOCBEN:1; // 15 Start of conversion B Enable
+};
+
+union ETSEL_REG {
+ Uint16 all;
+ struct ETSEL_BITS bit;
+};
+
+//
+// Event trigger pre-scale register bit definitions
+//
+struct ETPS_BITS { // bits description
+ Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
+ Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
+ Uint16 rsvd1:4; // 7:4 reserved
+ Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
+ Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
+ Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
+ Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
+};
+
+union ETPS_REG {
+ Uint16 all;
+ struct ETPS_BITS bit;
+};
+
+//
+// Event trigger Flag register bit definitions
+//
+struct ETFLG_BITS { // bits description
+ Uint16 INT:1; // 0 EPWMxINTn Flag
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 SOCA:1; // 2 EPWMxSOCA Flag
+ Uint16 SOCB:1; // 3 EPWMxSOCB Flag
+ Uint16 rsvd2:12; // 15:4 reserved
+};
+
+union ETFLG_REG {
+ Uint16 all;
+ struct ETFLG_BITS bit;
+};
+
+//
+// Event trigger Clear register bit definitions
+//
+struct ETCLR_BITS { // bits description
+ Uint16 INT:1; // 0 EPWMxINTn Clear
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 SOCA:1; // 2 EPWMxSOCA Clear
+ Uint16 SOCB:1; // 3 EPWMxSOCB Clear
+ Uint16 rsvd2:12; // 15:4 reserved
+};
+
+union ETCLR_REG {
+ Uint16 all;
+ struct ETCLR_BITS bit;
+};
+
+//
+// Event trigger Force register bit definitions
+//
+struct ETFRC_BITS { // bits description
+ Uint16 INT:1; // 0 EPWMxINTn Force
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 SOCA:1; // 2 EPWMxSOCA Force
+ Uint16 SOCB:1; // 3 EPWMxSOCB Force
+ Uint16 rsvd2:12; // 15:4 reserved
+};
+
+union ETFRC_REG {
+ Uint16 all;
+ struct ETFRC_BITS bit;
+};
+
+//
+// PWM chopper control register bit definitions
+//
+struct PCCTL_BITS { // bits description
+ Uint16 CHPEN:1; // 0 PWM chopping enable
+ Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
+ Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
+ Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
+ Uint16 rsvd1:5; // 15:11 reserved
+};
+
+union PCCTL_REG {
+ Uint16 all;
+ struct PCCTL_BITS bit;
+};
+
+struct HRCNFG_BITS { // bits description
+ Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
+ Uint16 CTLMODE:1; // 2 Control mode Select Bit
+ Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
+ Uint16 rsvd1:12; // 15:4 reserved
+};
+
+union HRCNFG_REG {
+ Uint16 all;
+ struct HRCNFG_BITS bit;
+};
+
+struct TBPHS_HRPWM_REG { //bits description
+ Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits)
+ Uint16 TBPHS; //31:16 Phase offset register
+};
+
+union TBPHS_HRPWM_GROUP {
+ Uint32 all;
+ struct TBPHS_HRPWM_REG half;
+};
+
+struct CMPA_HRPWM_REG { // bits description
+ Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
+ Uint16 CMPA; // 31:16 Compare A reg
+};
+
+union CMPA_HRPWM_GROUP {
+ Uint32 all;
+ struct CMPA_HRPWM_REG half;
+};
+
+struct EPWM_REGS {
+ union TBCTL_REG TBCTL; //
+ union TBSTS_REG TBSTS; //
+ union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
+ Uint16 TBCTR; // Counter
+ Uint16 TBPRD; // Period register set
+ Uint16 rsvd1; //
+ union CMPCTL_REG CMPCTL; // Compare control
+ union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
+ Uint16 CMPB; // Compare B reg
+ union AQCTL_REG AQCTLA; // Action qual output A
+ union AQCTL_REG AQCTLB; // Action qual output B
+ union AQSFRC_REG AQSFRC; // Action qual SW force
+ union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
+ union DBCTL_REG DBCTL; // Dead-band control
+ Uint16 DBRED; // Dead-band rising edge delay
+ Uint16 DBFED; // Dead-band falling edge delay
+ union TZSEL_REG TZSEL; // Trip zone select
+ Uint16 rsvd2;
+ union TZCTL_REG TZCTL; // Trip zone control
+ union TZEINT_REG TZEINT; // Trip zone interrupt enable
+ union TZFLG_REG TZFLG; // Trip zone interrupt flags
+ union TZCLR_REG TZCLR; // Trip zone clear
+ union TZFRC_REG TZFRC; // Trip zone force interrupt
+ union ETSEL_REG ETSEL; // Event trigger selection
+ union ETPS_REG ETPS; // Event trigger pre-scaler
+ union ETFLG_REG ETFLG; // Event trigger flags
+ union ETCLR_REG ETCLR; // Event trigger clear
+ union ETFRC_REG ETFRC; // Event trigger force
+ union PCCTL_REG PCCTL; // PWM chopper control
+ Uint16 rsvd3; //
+ union HRCNFG_REG HRCNFG; // HRPWM Config Reg
+};
+
+
+//
+// External References & Function Declarations
+//
+extern volatile struct EPWM_REGS EPwm1Regs;
+extern volatile struct EPWM_REGS EPwm2Regs;
+extern volatile struct EPWM_REGS EPwm3Regs;
+extern volatile struct EPWM_REGS EPwm4Regs;
+extern volatile struct EPWM_REGS EPwm5Regs;
+extern volatile struct EPWM_REGS EPwm6Regs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_EPWM_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_EPwm_defines.h b/bsp/include/DSP2833x_EPwm_defines.h
new file mode 100644
index 0000000..47c8dd6
--- /dev/null
+++ b/bsp/include/DSP2833x_EPwm_defines.h
@@ -0,0 +1,243 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:45:39 $
+//###########################################################################
+//
+// FILE: DSP2833x_EPwm_defines.h
+//
+// TITLE: #defines used in ePWM examples examples
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_EPWM_DEFINES_H
+#define DSP2833x_EPWM_DEFINES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// TBCTL (Time-Base Control)
+//
+// CTRMODE bits
+//
+#define TB_COUNT_UP 0x0
+#define TB_COUNT_DOWN 0x1
+#define TB_COUNT_UPDOWN 0x2
+#define TB_FREEZE 0x3
+
+//
+// PHSEN bit
+//
+#define TB_DISABLE 0x0
+#define TB_ENABLE 0x1
+
+//
+// PRDLD bit
+//
+#define TB_SHADOW 0x0
+#define TB_IMMEDIATE 0x1
+
+//
+// SYNCOSEL bits
+//
+#define TB_SYNC_IN 0x0
+#define TB_CTR_ZERO 0x1
+#define TB_CTR_CMPB 0x2
+#define TB_SYNC_DISABLE 0x3
+
+//
+// HSPCLKDIV and CLKDIV bits
+//
+#define TB_DIV1 0x0
+#define TB_DIV2 0x1
+#define TB_DIV4 0x2
+
+//
+// PHSDIR bit
+//
+#define TB_DOWN 0x0
+#define TB_UP 0x1
+
+//
+// CMPCTL (Compare Control)
+//
+// LOADAMODE and LOADBMODE bits
+//
+#define CC_CTR_ZERO 0x0
+#define CC_CTR_PRD 0x1
+#define CC_CTR_ZERO_PRD 0x2
+#define CC_LD_DISABLE 0x3
+
+//
+// SHDWAMODE and SHDWBMODE bits
+//
+#define CC_SHADOW 0x0
+#define CC_IMMEDIATE 0x1
+
+//
+// AQCTLA and AQCTLB (Action Qualifier Control)
+//
+// ZRO, PRD, CAU, CAD, CBU, CBD bits
+//
+#define AQ_NO_ACTION 0x0
+#define AQ_CLEAR 0x1
+#define AQ_SET 0x2
+#define AQ_TOGGLE 0x3
+
+//
+// DBCTL (Dead-Band Control)
+//
+// OUT MODE bits
+//
+#define DB_DISABLE 0x0
+#define DBB_ENABLE 0x1
+#define DBA_ENABLE 0x2
+#define DB_FULL_ENABLE 0x3
+
+//
+// POLSEL bits
+//
+#define DB_ACTV_HI 0x0
+#define DB_ACTV_LOC 0x1
+#define DB_ACTV_HIC 0x2
+#define DB_ACTV_LO 0x3
+
+//
+// IN MODE
+//
+#define DBA_ALL 0x0
+#define DBB_RED_DBA_FED 0x1
+#define DBA_RED_DBB_FED 0x2
+#define DBB_ALL 0x3
+
+//
+// CHPCTL (chopper control)
+//
+// CHPEN bit
+//
+#define CHP_DISABLE 0x0
+#define CHP_ENABLE 0x1
+
+//
+// CHPFREQ bits
+//
+#define CHP_DIV1 0x0
+#define CHP_DIV2 0x1
+#define CHP_DIV3 0x2
+#define CHP_DIV4 0x3
+#define CHP_DIV5 0x4
+#define CHP_DIV6 0x5
+#define CHP_DIV7 0x6
+#define CHP_DIV8 0x7
+
+//
+// CHPDUTY bits
+//
+#define CHP1_8TH 0x0
+#define CHP2_8TH 0x1
+#define CHP3_8TH 0x2
+#define CHP4_8TH 0x3
+#define CHP5_8TH 0x4
+#define CHP6_8TH 0x5
+#define CHP7_8TH 0x6
+
+//
+// TZSEL (Trip Zone Select)
+//
+// CBCn and OSHTn bits
+//
+#define TZ_DISABLE 0x0
+#define TZ_ENABLE 0x1
+
+//
+// TZCTL (Trip Zone Control)
+//
+// TZA and TZB bits
+//
+#define TZ_HIZ 0x0
+#define TZ_FORCE_HI 0x1
+#define TZ_FORCE_LO 0x2
+#define TZ_NO_CHANGE 0x3
+
+//
+// ETSEL (Event Trigger Select)
+//
+#define ET_CTR_ZERO 0x1
+#define ET_CTR_PRD 0x2
+#define ET_CTRU_CMPA 0x4
+#define ET_CTRD_CMPA 0x5
+#define ET_CTRU_CMPB 0x6
+#define ET_CTRD_CMPB 0x7
+
+//
+// ETPS (Event Trigger Pre-scale)
+//
+// INTPRD, SOCAPRD, SOCBPRD bits
+//
+#define ET_DISABLE 0x0
+#define ET_1ST 0x1
+#define ET_2ND 0x2
+#define ET_3RD 0x3
+
+//
+// HRPWM (High Resolution PWM)
+//
+// HRCNFG
+//
+#define HR_Disable 0x0
+#define HR_REP 0x1
+#define HR_FEP 0x2
+#define HR_BEP 0x3
+
+#define HR_CMP 0x0
+#define HR_PHS 0x1
+
+#define HR_CTR_ZERO 0x0
+#define HR_CTR_PRD 0x1
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // - end of DSP2833x_EPWM_DEFINES_H
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_EQep.h b/bsp/include/DSP2833x_EQep.h
new file mode 100644
index 0000000..6d5998e
--- /dev/null
+++ b/bsp/include/DSP2833x_EQep.h
@@ -0,0 +1,270 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:13 $
+//###########################################################################
+//
+// FILE: DSP2833x_EQep.h
+//
+// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
+// Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_EQEP_H
+#define DSP2833x_EQEP_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Capture decoder control register bit definitions
+//
+struct QDECCTL_BITS { // bits description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 QSP:1; // 5 QEPS input polarity
+ Uint16 QIP:1; // 6 QEPI input polarity
+ Uint16 QBP:1; // 7 QEPB input polarity
+ Uint16 QAP:1; // 8 QEPA input polarity
+ Uint16 IGATE:1; // 9 Index pulse gating option
+ Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
+ Uint16 XCR:1; // 11 External clock rate
+ Uint16 SPSEL:1; // 12 Sync output pin select
+ Uint16 SOEN:1; // 13 Enable position compare sync
+ Uint16 QSRC:2; // 15:14 Position counter source
+};
+
+union QDECCTL_REG {
+ Uint16 all;
+ struct QDECCTL_BITS bit;
+};
+
+//
+// QEP control register bit definitions
+//
+struct QEPCTL_BITS { // bits description
+ Uint16 WDE:1; // 0 QEP watchdog enable
+ Uint16 UTE:1; // 1 QEP unit timer enable
+ Uint16 QCLM:1; // 2 QEP capture latch mode
+ Uint16 QPEN:1; // 3 Quadrature position counter enable
+ Uint16 IEL:2; // 5:4 Index event latch
+ Uint16 SEL:1; // 6 Strobe event latch
+ Uint16 SWI:1; // 7 Software init position counter
+ Uint16 IEI:2; // 9:8 Index event init of position count
+ Uint16 SEI:2; // 11:10 Strobe event init
+ Uint16 PCRM:2; // 13:12 Position counter reset
+ Uint16 FREE_SOFT:2; // 15:14 Emulation mode
+};
+
+union QEPCTL_REG {
+ Uint16 all;
+ struct QEPCTL_BITS bit;
+};
+
+//
+// Quadrature capture control register bit definitions
+//
+struct QCAPCTL_BITS { // bits description
+ Uint16 UPPS:4; // 3:0 Unit position pre-scale
+ Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
+ Uint16 rsvd1:8; // 14:7 reserved
+ Uint16 CEN:1; // 15 Enable QEP capture
+};
+
+union QCAPCTL_REG {
+ Uint16 all;
+ struct QCAPCTL_BITS bit;
+};
+
+//
+// Position compare control register bit definitions
+//
+struct QPOSCTL_BITS { // bits description
+ Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
+ Uint16 PCE:1; // 12 Position compare enable/disable
+ Uint16 PCPOL:1; // 13 Polarity of sync output
+ Uint16 PCLOAD:1; // 14 Position compare of shadow load
+ Uint16 PCSHDW:1; // 15 Position compare shadow enable
+};
+
+union QPOSCTL_REG {
+ Uint16 all;
+ struct QPOSCTL_BITS bit;
+};
+
+//
+// QEP interrupt control register bit definitions
+//
+struct QEINT_BITS { // bits description
+ Uint16 rsvd1:1; // 0 reserved
+ Uint16 PCE:1; // 1 Position counter error
+ Uint16 QPE:1; // 2 Quadrature phase error
+ Uint16 QDC:1; // 3 Quadrature dir change
+ Uint16 WTO:1; // 4 Watchdog timeout
+ Uint16 PCU:1; // 5 Position counter underflow
+ Uint16 PCO:1; // 6 Position counter overflow
+ Uint16 PCR:1; // 7 Position compare ready
+ Uint16 PCM:1; // 8 Position compare match
+ Uint16 SEL:1; // 9 Strobe event latch
+ Uint16 IEL:1; // 10 Event latch
+ Uint16 UTO:1; // 11 Unit timeout
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+union QEINT_REG {
+ Uint16 all;
+ struct QEINT_BITS bit;
+};
+
+//
+// QEP interrupt status register bit definitions
+//
+struct QFLG_BITS { // bits description
+ Uint16 INT:1; // 0 Global interrupt
+ Uint16 PCE:1; // 1 Position counter error
+ Uint16 PHE:1; // 2 Quadrature phase error
+ Uint16 QDC:1; // 3 Quadrature dir change
+ Uint16 WTO:1; // 4 Watchdog timeout
+ Uint16 PCU:1; // 5 Position counter underflow
+ Uint16 PCO:1; // 6 Position counter overflow
+ Uint16 PCR:1; // 7 Position compare ready
+ Uint16 PCM:1; // 8 Position compare match
+ Uint16 SEL:1; // 9 Strobe event latch
+ Uint16 IEL:1; // 10 Event latch
+ Uint16 UTO:1; // 11 Unit timeout
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+union QFLG_REG {
+ Uint16 all;
+ struct QFLG_BITS bit;
+};
+
+//
+// QEP interrupt force register bit definitions
+//
+struct QFRC_BITS { // bits description
+ Uint16 reserved:1; // 0 Reserved
+ Uint16 PCE:1; // 1 Position counter error
+ Uint16 PHE:1; // 2 Quadrature phase error
+ Uint16 QDC:1; // 3 Quadrature dir change
+ Uint16 WTO:1; // 4 Watchdog timeout
+ Uint16 PCU:1; // 5 Position counter underflow
+ Uint16 PCO:1; // 6 Position counter overflow
+ Uint16 PCR:1; // 7 Position compare ready
+ Uint16 PCM:1; // 8 Position compare match
+ Uint16 SEL:1; // 9 Strobe event latch
+ Uint16 IEL:1; // 10 Event latch
+ Uint16 UTO:1; // 11 Unit timeout
+ Uint16 rsvd2:4; // 15:12 reserved
+};
+
+
+union QFRC_REG {
+ Uint16 all;
+ struct QFRC_BITS bit;
+};
+
+//
+// V1.1 Added UPEVNT (bit 7) This reflects changes
+// made as of F2833x Rev A devices
+//
+
+//
+// QEP status register bit definitions
+//
+struct QEPSTS_BITS { // bits description
+ Uint16 PCEF:1; // 0 Position counter error
+ Uint16 FIMF:1; // 1 First index marker
+ Uint16 CDEF:1; // 2 Capture direction error
+ Uint16 COEF:1; // 3 Capture overflow error
+ Uint16 QDLF:1; // 4 QEP direction latch
+ Uint16 QDF:1; // 5 Quadrature direction
+ Uint16 FIDF:1; // 6 Direction on first index marker
+ Uint16 UPEVNT:1; // 7 Unit position event flag
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union QEPSTS_REG {
+ Uint16 all;
+ struct QEPSTS_BITS bit;
+};
+
+struct EQEP_REGS {
+ Uint32 QPOSCNT; // Position counter
+ Uint32 QPOSINIT; // Position counter init
+ Uint32 QPOSMAX; // Maximum position count
+ Uint32 QPOSCMP; // Position compare
+ Uint32 QPOSILAT; // Index position latch
+ Uint32 QPOSSLAT; // Strobe position latch
+ Uint32 QPOSLAT; // Position latch
+ Uint32 QUTMR; // Unit timer
+ Uint32 QUPRD; // Unit period
+ Uint16 QWDTMR; // QEP watchdog timer
+ Uint16 QWDPRD; // QEP watchdog period
+ union QDECCTL_REG QDECCTL; // Quadrature decoder control
+ union QEPCTL_REG QEPCTL; // QEP control
+ union QCAPCTL_REG QCAPCTL; // Quadrature capture control
+ union QPOSCTL_REG QPOSCTL; // Position compare control
+ union QEINT_REG QEINT; // QEP interrupt control
+ union QFLG_REG QFLG; // QEP interrupt flag
+ union QFLG_REG QCLR; // QEP interrupt clear
+ union QFRC_REG QFRC; // QEP interrupt force
+ union QEPSTS_REG QEPSTS; // QEP status
+ Uint16 QCTMR; // QEP capture timer
+ Uint16 QCPRD; // QEP capture period
+ Uint16 QCTMRLAT; // QEP capture latch
+ Uint16 QCPRDLAT; // QEP capture period latch
+ Uint16 rsvd1[30]; // reserved
+};
+
+//
+// GPI/O External References & Function Declarations
+//
+extern volatile struct EQEP_REGS EQep1Regs;
+extern volatile struct EQEP_REGS EQep2Regs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_EQEP_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Examples.h b/bsp/include/DSP2833x_Examples.h
new file mode 100644
index 0000000..a2754b4
--- /dev/null
+++ b/bsp/include/DSP2833x_Examples.h
@@ -0,0 +1,167 @@
+// TI File $Revision: /main/9 $
+// Checkin $Date: July 2, 2008 14:31:12 $
+//###########################################################################
+//
+// FILE: DSP2833x_Examples.h
+//
+// TITLE: DSP2833x Device Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_EXAMPLES_H
+#define DSP2833x_EXAMPLES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
+//
+//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
+//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
+#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
+//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
+
+#define DSP28_PLLCR 10
+//#define DSP28_PLLCR 9
+//#define DSP28_PLLCR 8
+//#define DSP28_PLLCR 7
+//#define DSP28_PLLCR 6
+//#define DSP28_PLLCR 5
+//#define DSP28_PLLCR 4
+//#define DSP28_PLLCR 3
+//#define DSP28_PLLCR 2
+//#define DSP28_PLLCR 1
+//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
+
+//
+// Specify the clock rate of the CPU (SYSCLKOUT) in nS.
+//
+// Take into account the input clock frequency and the PLL multiplier
+// selected in step 1.
+//
+// Use one of the values provided, or define your own.
+// The trailing L is required tells the compiler to treat
+// the number as a 64-bit value.
+//
+// Only one statement should be uncommented.
+//
+// Example 1:150 MHz devices:
+// CLKIN is a 30MHz crystal.
+//
+// In step 1 the user specified PLLCR = 0xA for a
+// 150Mhz CPU clock (SYSCLKOUT = 150MHz).
+//
+// In this case, the CPU_RATE will be 6.667L
+// Uncomment the line: #define CPU_RATE 6.667L
+//
+// Example 2: 100 MHz devices:
+// CLKIN is a 20MHz crystal.
+//
+// In step 1 the user specified PLLCR = 0xA for a
+// 100Mhz CPU clock (SYSCLKOUT = 100MHz).
+//
+// In this case, the CPU_RATE will be 10.000L
+// Uncomment the line: #define CPU_RATE 10.000L
+//
+#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
+
+//
+// Target device (in DSP2833x_Device.h) determines CPU frequency
+// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
+// (for 28332 and 28333). User does not have to change anything here.
+//
+#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only
+ #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
+ #define CPU_FRQ_150MHZ 0
+#else
+ #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
+ #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
+#endif
+
+//
+// Include Example Header Files
+//
+
+//
+// Prototypes for global functions within the .c files.
+//
+#include "DSP2833x_GlobalPrototypes.h"
+#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples.
+#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
+#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples.
+
+#define PARTNO_28335 0xEF
+#define PARTNO_28334 0xEE
+#define PARTNO_28333 0xEA
+#define PARTNO_28332 0xED
+
+//
+// Include files not used with DSP/BIOS
+//
+#ifndef DSP28_BIOS
+#include "DSP2833x_DefaultIsr.h"
+#endif
+
+//
+// DO NOT MODIFY THIS LINE.
+//
+#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \
+ (long double)CPU_RATE) - 9.0L) / 5.0L)
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_EXAMPLES_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_GlobalPrototypes.h b/bsp/include/DSP2833x_GlobalPrototypes.h
new file mode 100644
index 0000000..b9006ac
--- /dev/null
+++ b/bsp/include/DSP2833x_GlobalPrototypes.h
@@ -0,0 +1,291 @@
+// TI File $Revision: /main/11 $
+// Checkin $Date: May 12, 2008 14:30:08 $
+//###########################################################################
+//
+// FILE: DSP2833x_GlobalPrototypes.h
+//
+// TITLE: Global prototypes for DSP2833x Examples
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_GLOBALPROTOTYPES_H
+#define DSP2833x_GLOBALPROTOTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// shared global function prototypes
+//
+extern void InitAdc(void);
+extern void DMAInitialize(void);
+
+//
+// DMA Channel 1
+//
+extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
+ volatile Uint16 *DMA_Source);
+extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep);
+extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
+ Uint16 cont, Uint16 synce, Uint16 syncsel,
+ Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
+ Uint16 chinte);
+extern void StartDMACH1(void);
+
+//
+// DMA Channel 2
+//
+extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
+ volatile Uint16 *DMA_Source);
+extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep);
+extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
+ Uint16 cont, Uint16 synce, Uint16 syncsel,
+ Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
+ Uint16 chinte);
+extern void StartDMACH2(void);
+
+//
+// DMA Channel 3
+//
+extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
+ volatile Uint16 *DMA_Source);
+extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep);
+extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
+ Uint16 cont, Uint16 synce, Uint16 syncsel,
+ Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
+ Uint16 chinte);
+extern void StartDMACH3(void);
+
+//
+// DMA Channel 4
+//
+extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
+ volatile Uint16 *DMA_Source);
+extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep);
+extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
+ Uint16 cont, Uint16 synce, Uint16 syncsel,
+ Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
+ Uint16 chinte);
+extern void StartDMACH4(void);
+
+//
+// DMA Channel 5
+//
+extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
+ volatile Uint16 *DMA_Source);
+extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep);
+extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
+ Uint16 cont, Uint16 synce, Uint16 syncsel,
+ Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
+ Uint16 chinte);
+extern void StartDMACH5(void);
+
+//
+// DMA Channel 6
+//
+extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
+ volatile Uint16 *DMA_Source);
+extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep);
+extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
+ Uint16 cont, Uint16 synce, Uint16 syncsel,
+ Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
+ Uint16 chinte);
+extern void StartDMACH6(void);
+
+extern void InitPeripherals(void);
+#if DSP28_ECANA
+extern void InitECan(void);
+extern void InitECana(void);
+extern void InitECanGpio(void);
+extern void InitECanaGpio(void);
+#endif // endif DSP28_ECANA
+#if DSP28_ECANB
+extern void InitECanb(void);
+extern void InitECanbGpio(void);
+#endif // endif DSP28_ECANB
+extern void InitECap(void);
+extern void InitECapGpio(void);
+extern void InitECap1Gpio(void);
+extern void InitECap2Gpio(void);
+#if DSP28_ECAP3
+extern void InitECap3Gpio(void);
+#endif // endif DSP28_ECAP3
+#if DSP28_ECAP4
+extern void InitECap4Gpio(void);
+#endif // endif DSP28_ECAP4
+#if DSP28_ECAP5
+extern void InitECap5Gpio(void);
+#endif // endif DSP28_ECAP5
+#if DSP28_ECAP6
+extern void InitECap6Gpio(void);
+#endif // endif DSP28_ECAP6
+extern void InitEPwm(void);
+extern void InitEPwmGpio(void);
+extern void InitEPwm1Gpio(void);
+extern void InitEPwm2Gpio(void);
+extern void InitEPwm3Gpio(void);
+#if DSP28_EPWM4
+extern void InitEPwm4Gpio(void);
+#endif // endif DSP28_EPWM4
+#if DSP28_EPWM5
+extern void InitEPwm5Gpio(void);
+#endif // endif DSP28_EPWM5
+#if DSP28_EPWM6
+extern void InitEPwm6Gpio(void);
+#endif // endif DSP28_EPWM6
+#if DSP28_EQEP1
+extern void InitEQep(void);
+extern void InitEQepGpio(void);
+extern void InitEQep1Gpio(void);
+#endif // if DSP28_EQEP1
+#if DSP28_EQEP2
+extern void InitEQep2Gpio(void);
+#endif // endif DSP28_EQEP2
+extern void InitGpio(void);
+extern void InitI2CGpio(void);
+
+extern void InitMcbsp(void);
+extern void InitMcbspa(void);
+extern void delay_loop(void);
+extern void InitMcbspaGpio(void);
+extern void InitMcbspa8bit(void);
+extern void InitMcbspa12bit(void);
+extern void InitMcbspa16bit(void);
+extern void InitMcbspa20bit(void);
+extern void InitMcbspa24bit(void);
+extern void InitMcbspa32bit(void);
+#if DSP28_MCBSPB
+extern void InitMcbspb(void);
+extern void InitMcbspbGpio(void);
+extern void InitMcbspb8bit(void);
+extern void InitMcbspb12bit(void);
+extern void InitMcbspb16bit(void);
+extern void InitMcbspb20bit(void);
+extern void InitMcbspb24bit(void);
+extern void InitMcbspb32bit(void);
+#endif // endif DSP28_MCBSPB
+
+extern void InitPieCtrl(void);
+extern void InitPieVectTable(void);
+
+extern void InitSci(void);
+extern void InitSciGpio(void);
+extern void InitSciaGpio(void);
+#if DSP28_SCIB
+extern void InitScibGpio(void);
+#endif // endif DSP28_SCIB
+#if DSP28_SCIC
+extern void InitScicGpio(void);
+#endif
+extern void InitSpi(void);
+extern void InitSpiGpio(void);
+extern void InitSpiaGpio(void);
+extern void InitSysCtrl(void);
+extern void InitTzGpio(void);
+extern void InitXIntrupt(void);
+extern void XintfInit(void);
+extern void InitXintf16Gpio();
+extern void InitXintf32Gpio();
+extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
+extern void InitPeripheralClocks(void);
+extern void EnableInterrupts(void);
+extern void DSP28x_usDelay(Uint32 Count);
+extern void ADC_cal (void);
+#define KickDog ServiceDog // For compatiblity with previous versions
+extern void ServiceDog(void);
+extern void DisableDog(void);
+extern Uint16 CsmUnlock(void);
+
+//
+// DSP28_DBGIER.asm
+//
+extern void SetDBGIER(Uint16 dbgier);
+
+//
+// CAUTION
+// This function MUST be executed out of RAM. Executing it
+// out of OTP/Flash will yield unpredictable results
+//
+extern void InitFlash(void);
+
+void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
+
+//
+// External symbols created by the linker cmd file
+// DSP28 examples will use these to relocate code from one LOAD location
+// in either Flash or XINTF to a different RUN location in internal
+// RAM
+//
+extern Uint16 RamfuncsLoadStart;
+extern Uint16 RamfuncsLoadEnd;
+extern Uint16 RamfuncsRunStart;
+extern Uint16 RamfuncsLoadSize;
+
+extern Uint16 XintffuncsLoadStart;
+extern Uint16 XintffuncsLoadEnd;
+extern Uint16 XintffuncsRunStart;
+extern Uint16 XintffuncsLoadSize;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Gpio.h b/bsp/include/DSP2833x_Gpio.h
new file mode 100644
index 0000000..8ad1bf8
--- /dev/null
+++ b/bsp/include/DSP2833x_Gpio.h
@@ -0,0 +1,493 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: November 15, 2007 09:58:53 $
+//###########################################################################
+//
+// FILE: DSP2833x_Gpio.h
+//
+// TITLE: DSP2833x General Purpose I/O Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_GPIO_H
+#define DSP2833x_GPIO_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// GPIO A control register bit definitions
+//
+struct GPACTRL_BITS { // bits description
+ Uint16 QUALPRD0:8; // 7:0 Qual period
+ Uint16 QUALPRD1:8; // 15:8 Qual period
+ Uint16 QUALPRD2:8; // 23:16 Qual period
+ Uint16 QUALPRD3:8; // 31:24 Qual period
+};
+
+union GPACTRL_REG {
+ Uint32 all;
+ struct GPACTRL_BITS bit;
+};
+
+//
+// GPIO B control register bit definitions
+//
+struct GPBCTRL_BITS { // bits description
+ Uint16 QUALPRD0:8; // 7:0 Qual period
+ Uint16 QUALPRD1:8; // 15:8 Qual period
+ Uint16 QUALPRD2:8; // 23:16 Qual period
+ Uint16 QUALPRD3:8; // 31:24
+};
+
+union GPBCTRL_REG {
+ Uint32 all;
+ struct GPBCTRL_BITS bit;
+};
+
+//
+// GPIO A Qual/MUX select register bit definitions
+//
+struct GPA1_BITS { // bits description
+ Uint16 GPIO0:2; // 1:0 GPIO0
+ Uint16 GPIO1:2; // 3:2 GPIO1
+ Uint16 GPIO2:2; // 5:4 GPIO2
+ Uint16 GPIO3:2; // 7:6 GPIO3
+ Uint16 GPIO4:2; // 9:8 GPIO4
+ Uint16 GPIO5:2; // 11:10 GPIO5
+ Uint16 GPIO6:2; // 13:12 GPIO6
+ Uint16 GPIO7:2; // 15:14 GPIO7
+ Uint16 GPIO8:2; // 17:16 GPIO8
+ Uint16 GPIO9:2; // 19:18 GPIO9
+ Uint16 GPIO10:2; // 21:20 GPIO10
+ Uint16 GPIO11:2; // 23:22 GPIO11
+ Uint16 GPIO12:2; // 25:24 GPIO12
+ Uint16 GPIO13:2; // 27:26 GPIO13
+ Uint16 GPIO14:2; // 29:28 GPIO14
+ Uint16 GPIO15:2; // 31:30 GPIO15
+};
+
+struct GPA2_BITS { // bits description
+ Uint16 GPIO16:2; // 1:0 GPIO16
+ Uint16 GPIO17:2; // 3:2 GPIO17
+ Uint16 GPIO18:2; // 5:4 GPIO18
+ Uint16 GPIO19:2; // 7:6 GPIO19
+ Uint16 GPIO20:2; // 9:8 GPIO20
+ Uint16 GPIO21:2; // 11:10 GPIO21
+ Uint16 GPIO22:2; // 13:12 GPIO22
+ Uint16 GPIO23:2; // 15:14 GPIO23
+ Uint16 GPIO24:2; // 17:16 GPIO24
+ Uint16 GPIO25:2; // 19:18 GPIO25
+ Uint16 GPIO26:2; // 21:20 GPIO26
+ Uint16 GPIO27:2; // 23:22 GPIO27
+ Uint16 GPIO28:2; // 25:24 GPIO28
+ Uint16 GPIO29:2; // 27:26 GPIO29
+ Uint16 GPIO30:2; // 29:28 GPIO30
+ Uint16 GPIO31:2; // 31:30 GPIO31
+};
+
+struct GPB1_BITS { // bits description
+ Uint16 GPIO32:2; // 1:0 GPIO32
+ Uint16 GPIO33:2; // 3:2 GPIO33
+ Uint16 GPIO34:2; // 5:4 GPIO34
+ Uint16 GPIO35:2; // 7:6 GPIO35
+ Uint16 GPIO36:2; // 9:8 GPIO36
+ Uint16 GPIO37:2; // 11:10 GPIO37
+ Uint16 GPIO38:2; // 13:12 GPIO38
+ Uint16 GPIO39:2; // 15:14 GPIO39
+ Uint16 GPIO40:2; // 17:16 GPIO40
+ Uint16 GPIO41:2; // 19:16 GPIO41
+ Uint16 GPIO42:2; // 21:20 GPIO42
+ Uint16 GPIO43:2; // 23:22 GPIO43
+ Uint16 GPIO44:2; // 25:24 GPIO44
+ Uint16 GPIO45:2; // 27:26 GPIO45
+ Uint16 GPIO46:2; // 29:28 GPIO46
+ Uint16 GPIO47:2; // 31:30 GPIO47
+};
+
+struct GPB2_BITS { // bits description
+ Uint16 GPIO48:2; // 1:0 GPIO48
+ Uint16 GPIO49:2; // 3:2 GPIO49
+ Uint16 GPIO50:2; // 5:4 GPIO50
+ Uint16 GPIO51:2; // 7:6 GPIO51
+ Uint16 GPIO52:2; // 9:8 GPIO52
+ Uint16 GPIO53:2; // 11:10 GPIO53
+ Uint16 GPIO54:2; // 13:12 GPIO54
+ Uint16 GPIO55:2; // 15:14 GPIO55
+ Uint16 GPIO56:2; // 17:16 GPIO56
+ Uint16 GPIO57:2; // 19:18 GPIO57
+ Uint16 GPIO58:2; // 21:20 GPIO58
+ Uint16 GPIO59:2; // 23:22 GPIO59
+ Uint16 GPIO60:2; // 25:24 GPIO60
+ Uint16 GPIO61:2; // 27:26 GPIO61
+ Uint16 GPIO62:2; // 29:28 GPIO62
+ Uint16 GPIO63:2; // 31:30 GPIO63
+};
+
+struct GPC1_BITS { // bits description
+ Uint16 GPIO64:2; // 1:0 GPIO64
+ Uint16 GPIO65:2; // 3:2 GPIO65
+ Uint16 GPIO66:2; // 5:4 GPIO66
+ Uint16 GPIO67:2; // 7:6 GPIO67
+ Uint16 GPIO68:2; // 9:8 GPIO68
+ Uint16 GPIO69:2; // 11:10 GPIO69
+ Uint16 GPIO70:2; // 13:12 GPIO70
+ Uint16 GPIO71:2; // 15:14 GPIO71
+ Uint16 GPIO72:2; // 17:16 GPIO72
+ Uint16 GPIO73:2; // 19:18 GPIO73
+ Uint16 GPIO74:2; // 21:20 GPIO74
+ Uint16 GPIO75:2; // 23:22 GPIO75
+ Uint16 GPIO76:2; // 25:24 GPIO76
+ Uint16 GPIO77:2; // 27:26 GPIO77
+ Uint16 GPIO78:2; // 29:28 GPIO78
+ Uint16 GPIO79:2; // 31:30 GPIO79
+};
+
+struct GPC2_BITS { // bits description
+ Uint16 GPIO80:2; // 1:0 GPIO80
+ Uint16 GPIO81:2; // 3:2 GPIO81
+ Uint16 GPIO82:2; // 5:4 GPIO82
+ Uint16 GPIO83:2; // 7:6 GPIO83
+ Uint16 GPIO84:2; // 9:8 GPIO84
+ Uint16 GPIO85:2; // 11:10 GPIO85
+ Uint16 GPIO86:2; // 13:12 GPIO86
+ Uint16 GPIO87:2; // 15:14 GPIO87
+ Uint16 rsvd:16; // 31:16 reserved
+};
+
+union GPA1_REG {
+ Uint32 all;
+ struct GPA1_BITS bit;
+};
+
+union GPA2_REG {
+ Uint32 all;
+ struct GPA2_BITS bit;
+};
+
+union GPB1_REG {
+ Uint32 all;
+ struct GPB1_BITS bit;
+};
+
+union GPB2_REG {
+ Uint32 all;
+ struct GPB2_BITS bit;
+};
+
+union GPC1_REG {
+ Uint32 all;
+ struct GPC1_BITS bit;
+};
+
+union GPC2_REG {
+ Uint32 all;
+ struct GPC2_BITS bit;
+};
+
+//
+// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions
+//
+struct GPADAT_BITS { // bits description
+ Uint16 GPIO0:1; // 0 GPIO0
+ Uint16 GPIO1:1; // 1 GPIO1
+ Uint16 GPIO2:1; // 2 GPIO2
+ Uint16 GPIO3:1; // 3 GPIO3
+ Uint16 GPIO4:1; // 4 GPIO4
+ Uint16 GPIO5:1; // 5 GPIO5
+ Uint16 GPIO6:1; // 6 GPIO6
+ Uint16 GPIO7:1; // 7 GPIO7
+ Uint16 GPIO8:1; // 8 GPIO8
+ Uint16 GPIO9:1; // 9 GPIO9
+ Uint16 GPIO10:1; // 10 GPIO10
+ Uint16 GPIO11:1; // 11 GPIO11
+ Uint16 GPIO12:1; // 12 GPIO12
+ Uint16 GPIO13:1; // 13 GPIO13
+ Uint16 GPIO14:1; // 14 GPIO14
+ Uint16 GPIO15:1; // 15 GPIO15
+ Uint16 GPIO16:1; // 16 GPIO16
+ Uint16 GPIO17:1; // 17 GPIO17
+ Uint16 GPIO18:1; // 18 GPIO18
+ Uint16 GPIO19:1; // 19 GPIO19
+ Uint16 GPIO20:1; // 20 GPIO20
+ Uint16 GPIO21:1; // 21 GPIO21
+ Uint16 GPIO22:1; // 22 GPIO22
+ Uint16 GPIO23:1; // 23 GPIO23
+ Uint16 GPIO24:1; // 24 GPIO24
+ Uint16 GPIO25:1; // 25 GPIO25
+ Uint16 GPIO26:1; // 26 GPIO26
+ Uint16 GPIO27:1; // 27 GPIO27
+ Uint16 GPIO28:1; // 28 GPIO28
+ Uint16 GPIO29:1; // 29 GPIO29
+ Uint16 GPIO30:1; // 30 GPIO30
+ Uint16 GPIO31:1; // 31 GPIO31
+};
+
+struct GPBDAT_BITS { // bits description
+ Uint16 GPIO32:1; // 0 GPIO32
+ Uint16 GPIO33:1; // 1 GPIO33
+ Uint16 GPIO34:1; // 2 GPIO34
+ Uint16 GPIO35:1; // 3 GPIO35
+ Uint16 GPIO36:1; // 4 GPIO36
+ Uint16 GPIO37:1; // 5 GPIO37
+ Uint16 GPIO38:1; // 6 GPIO38
+ Uint16 GPIO39:1; // 7 GPIO39
+ Uint16 GPIO40:1; // 8 GPIO40
+ Uint16 GPIO41:1; // 9 GPIO41
+ Uint16 GPIO42:1; // 10 GPIO42
+ Uint16 GPIO43:1; // 11 GPIO43
+ Uint16 GPIO44:1; // 12 GPIO44
+ Uint16 GPIO45:1; // 13 GPIO45
+ Uint16 GPIO46:1; // 14 GPIO46
+ Uint16 GPIO47:1; // 15 GPIO47
+ Uint16 GPIO48:1; // 16 GPIO48
+ Uint16 GPIO49:1; // 17 GPIO49
+ Uint16 GPIO50:1; // 18 GPIO50
+ Uint16 GPIO51:1; // 19 GPIO51
+ Uint16 GPIO52:1; // 20 GPIO52
+ Uint16 GPIO53:1; // 21 GPIO53
+ Uint16 GPIO54:1; // 22 GPIO54
+ Uint16 GPIO55:1; // 23 GPIO55
+ Uint16 GPIO56:1; // 24 GPIO56
+ Uint16 GPIO57:1; // 25 GPIO57
+ Uint16 GPIO58:1; // 26 GPIO58
+ Uint16 GPIO59:1; // 27 GPIO59
+ Uint16 GPIO60:1; // 28 GPIO60
+ Uint16 GPIO61:1; // 29 GPIO61
+ Uint16 GPIO62:1; // 30 GPIO62
+ Uint16 GPIO63:1; // 31 GPIO63
+};
+
+struct GPCDAT_BITS { // bits description
+ Uint16 GPIO64:1; // 0 GPIO64
+ Uint16 GPIO65:1; // 1 GPIO65
+ Uint16 GPIO66:1; // 2 GPIO66
+ Uint16 GPIO67:1; // 3 GPIO67
+ Uint16 GPIO68:1; // 4 GPIO68
+ Uint16 GPIO69:1; // 5 GPIO69
+ Uint16 GPIO70:1; // 6 GPIO70
+ Uint16 GPIO71:1; // 7 GPIO71
+ Uint16 GPIO72:1; // 8 GPIO72
+ Uint16 GPIO73:1; // 9 GPIO73
+ Uint16 GPIO74:1; // 10 GPIO74
+ Uint16 GPIO75:1; // 11 GPIO75
+ Uint16 GPIO76:1; // 12 GPIO76
+ Uint16 GPIO77:1; // 13 GPIO77
+ Uint16 GPIO78:1; // 14 GPIO78
+ Uint16 GPIO79:1; // 15 GPIO79
+ Uint16 GPIO80:1; // 16 GPIO80
+ Uint16 GPIO81:1; // 17 GPIO81
+ Uint16 GPIO82:1; // 18 GPIO82
+ Uint16 GPIO83:1; // 19 GPIO83
+ Uint16 GPIO84:1; // 20 GPIO84
+ Uint16 GPIO85:1; // 21 GPIO85
+ Uint16 GPIO86:1; // 22 GPIO86
+ Uint16 GPIO87:1; // 23 GPIO87
+ Uint16 rsvd1:8; // 31:24 reserved
+};
+
+union GPADAT_REG {
+ Uint32 all;
+ struct GPADAT_BITS bit;
+};
+
+union GPBDAT_REG {
+ Uint32 all;
+ struct GPBDAT_BITS bit;
+};
+
+union GPCDAT_REG {
+ Uint32 all;
+ struct GPCDAT_BITS bit;
+};
+
+//
+// GPIO Xint1/XINT2/XNMI select register bit definitions
+//
+struct GPIOXINT_BITS { // bits description
+ Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
+ Uint16 rsvd1:11; // 15:5 reserved
+};
+
+union GPIOXINT_REG {
+ Uint16 all;
+ struct GPIOXINT_BITS bit;
+};
+
+struct GPIO_CTRL_REGS {
+ union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
+
+ //
+ // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
+ //
+ union GPA1_REG GPAQSEL1;
+
+ //
+ // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
+ //
+ union GPA2_REG GPAQSEL2;
+
+ //
+ // GPIO A Mux 1 Register (GPIO0 to 15)
+ //
+ union GPA1_REG GPAMUX1;
+
+ //
+ // GPIO A Mux 2 Register (GPIO16 to 31)
+ //
+ union GPA2_REG GPAMUX2;
+
+ union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
+
+ //
+ // GPIO A Pull Up Disable Register (GPIO0 to 31)
+ //
+ union GPADAT_REG GPAPUD;
+
+ Uint32 rsvd1;
+ union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
+
+ //
+ // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
+ //
+ union GPB1_REG GPBQSEL1;
+
+ //
+ // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
+ //
+ union GPB2_REG GPBQSEL2;
+
+ union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
+ union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
+ union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
+
+ //
+ // GPIO B Pull Up Disable Register (GPIO32 to 63)
+ //
+ union GPBDAT_REG GPBPUD;
+
+ Uint16 rsvd2[8];
+ union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
+ union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
+ union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
+
+ //
+ // GPIO C Pull Up Disable Register (GPIO64 to 95)
+ //
+ union GPCDAT_REG GPCPUD;
+};
+
+struct GPIO_DATA_REGS {
+ union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
+
+ //
+ // GPIO Data Set Register (GPIO0 to 31)
+ //
+ union GPADAT_REG GPASET;
+
+ //
+ // GPIO Data Clear Register (GPIO0 to 31)
+ //
+ union GPADAT_REG GPACLEAR;
+
+ //
+ // GPIO Data Toggle Register (GPIO0 to 31)
+ //
+ union GPADAT_REG GPATOGGLE;
+
+ union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
+
+ //
+ // GPIO Data Set Register (GPIO32 to 63)
+ //
+ union GPBDAT_REG GPBSET;
+
+ //
+ // GPIO Data Clear Register (GPIO32 to 63)
+ //
+ union GPBDAT_REG GPBCLEAR;
+
+ //
+ // GPIO Data Toggle Register (GPIO32 to 63)
+ //
+ union GPBDAT_REG GPBTOGGLE;
+
+ union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
+ union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
+
+ //
+ // GPIO Data Clear Register (GPIO64 to 95)
+ //
+ union GPCDAT_REG GPCCLEAR;
+
+ //
+ // GPIO Data Toggle Register (GPIO64 to 95)
+ //
+ union GPCDAT_REG GPCTOGGLE;
+ Uint16 rsvd1[8];
+};
+
+struct GPIO_INT_REGS {
+ union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection
+ union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection
+ union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection
+ union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select
+};
+
+//
+// GPI/O External References & Function Declarations
+//
+extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
+extern volatile struct GPIO_DATA_REGS GpioDataRegs;
+extern volatile struct GPIO_INT_REGS GpioIntRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_GPIO_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_I2c.h b/bsp/include/DSP2833x_I2c.h
new file mode 100644
index 0000000..2713833
--- /dev/null
+++ b/bsp/include/DSP2833x_I2c.h
@@ -0,0 +1,233 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 22, 2007 10:40:22 $
+//###########################################################################
+//
+// FILE: DSP2833x_I2c.h
+//
+// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
+// Register Bit Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_I2C_H
+#define DSP2833x_I2C_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// I2C interrupt vector register bit definitions
+//
+struct I2CISRC_BITS { // bits description
+ Uint16 INTCODE:3; // 2:0 Interrupt code
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union I2CISRC_REG {
+ Uint16 all;
+ struct I2CISRC_BITS bit;
+};
+
+//
+// I2C interrupt mask register bit definitions
+//
+struct I2CIER_BITS { // bits description
+ Uint16 ARBL:1; // 0 Arbitration lost interrupt
+ Uint16 NACK:1; // 1 No ack interrupt
+ Uint16 ARDY:1; // 2 Register access ready interrupt
+ Uint16 RRDY:1; // 3 Recieve data ready interrupt
+ Uint16 XRDY:1; // 4 Transmit data ready interrupt
+ Uint16 SCD:1; // 5 Stop condition detection
+ Uint16 AAS:1; // 6 Address as slave
+ Uint16 rsvd:9; // 15:7 reserved
+};
+
+union I2CIER_REG {
+ Uint16 all;
+ struct I2CIER_BITS bit;
+};
+
+//
+// I2C status register bit definitions
+//
+struct I2CSTR_BITS { // bits description
+ Uint16 ARBL:1; // 0 Arbitration lost interrupt
+ Uint16 NACK:1; // 1 No ack interrupt
+ Uint16 ARDY:1; // 2 Register access ready interrupt
+ Uint16 RRDY:1; // 3 Recieve data ready interrupt
+ Uint16 XRDY:1; // 4 Transmit data ready interrupt
+ Uint16 SCD:1; // 5 Stop condition detection
+ Uint16 rsvd1:2; // 7:6 reserved
+ Uint16 AD0:1; // 8 Address Zero
+ Uint16 AAS:1; // 9 Address as slave
+ Uint16 XSMT:1; // 10 XMIT shift empty
+ Uint16 RSFULL:1; // 11 Recieve shift full
+ Uint16 BB:1; // 12 Bus busy
+ Uint16 NACKSNT:1; // 13 A no ack sent
+ Uint16 SDIR:1; // 14 Slave direction
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union I2CSTR_REG {
+ Uint16 all;
+ struct I2CSTR_BITS bit;
+};
+
+//
+// I2C mode control register bit definitions
+//
+struct I2CMDR_BITS { // bits description
+ Uint16 BC:3; // 2:0 Bit count
+ Uint16 FDF:1; // 3 Free data format
+ Uint16 STB:1; // 4 Start byte
+ Uint16 IRS:1; // 5 I2C Reset not
+ Uint16 DLB:1; // 6 Digital loopback
+ Uint16 RM:1; // 7 Repeat mode
+ Uint16 XA:1; // 8 Expand address
+ Uint16 TRX:1; // 9 Transmitter/reciever
+ Uint16 MST:1; // 10 Master/slave
+ Uint16 STP:1; // 11 Stop condition
+ Uint16 rsvd1:1; // 12 reserved
+ Uint16 STT:1; // 13 Start condition
+ Uint16 FREE:1; // 14 Emulation mode
+ Uint16 NACKMOD:1; // 15 No Ack mode
+};
+
+union I2CMDR_REG {
+ Uint16 all;
+ struct I2CMDR_BITS bit;
+};
+
+//
+// I2C extended mode control register bit definitions
+//
+struct I2CEMDR_BITS { // bits description
+ Uint16 BCM:1; // 0 Backward compatibility mode
+ Uint16 rsvd:15; // 15 reserved
+};
+
+union I2CEMDR_REG {
+ Uint16 all;
+ struct I2CEMDR_BITS bit;
+};
+
+//
+// I2C pre-scaler register bit definitions
+//
+struct I2CPSC_BITS { // bits description
+ Uint16 IPSC:8; // 7:0 pre-scaler
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union I2CPSC_REG {
+ Uint16 all;
+ struct I2CPSC_BITS bit;
+};
+
+//
+// TX FIFO control register bit definitions
+//
+struct I2CFFTX_BITS { // bits description
+ Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
+ Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
+ Uint16 TXFFINTCLR:1; // 6 FIFO clear
+ Uint16 TXFFINT:1; // 7 FIFO interrupt flag
+ Uint16 TXFFST:5; // 12:8 FIFO level status
+ Uint16 TXFFRST:1; // 13 FIFO reset
+ Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
+ Uint16 rsvd1:1; // 15 reserved
+};
+
+union I2CFFTX_REG {
+ Uint16 all;
+ struct I2CFFTX_BITS bit;
+};
+
+//
+// RX FIFO control register bit definitions
+//
+struct I2CFFRX_BITS { // bits description
+ Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
+ Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
+ Uint16 RXFFINTCLR:1; // 6 FIFO clear
+ Uint16 RXFFINT:1; // 7 FIFO interrupt flag
+ Uint16 RXFFST:5; // 12:8 FIFO level
+ Uint16 RXFFRST:1; // 13 FIFO reset
+ Uint16 rsvd1:2; // 15:14 reserved
+};
+
+union I2CFFRX_REG {
+ Uint16 all;
+ struct I2CFFRX_BITS bit;
+};
+
+struct I2C_REGS {
+ Uint16 I2COAR; // Own address register
+ union I2CIER_REG I2CIER; // Interrupt enable
+ union I2CSTR_REG I2CSTR; // Interrupt status
+ Uint16 I2CCLKL; // Clock divider low
+ Uint16 I2CCLKH; // Clock divider high
+ Uint16 I2CCNT; // Data count
+ Uint16 I2CDRR; // Data recieve
+ Uint16 I2CSAR; // Slave address
+ Uint16 I2CDXR; // Data transmit
+ union I2CMDR_REG I2CMDR; // Mode
+ union I2CISRC_REG I2CISRC; // Interrupt source
+ union I2CEMDR_REG I2CEMDR; // Extended Mode
+ union I2CPSC_REG I2CPSC; // Pre-scaler
+ Uint16 rsvd2[19]; // reserved
+ union I2CFFTX_REG I2CFFTX; // Transmit FIFO
+ union I2CFFRX_REG I2CFFRX; // Recieve FIFO
+};
+
+//
+// External References & Function Declarations
+//
+extern volatile struct I2C_REGS I2caRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_I2C_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_I2c_defines.h b/bsp/include/DSP2833x_I2c_defines.h
new file mode 100644
index 0000000..c03c934
--- /dev/null
+++ b/bsp/include/DSP2833x_I2c_defines.h
@@ -0,0 +1,179 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 16, 2008 17:16:47 $
+//###########################################################################
+//
+// FILE: DSP2833x_I2cExample.h
+//
+// TITLE: 2833x I2C Example Code Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_I2C_DEFINES_H
+#define DSP2833x_I2C_DEFINES_H
+
+//
+// Defines
+//
+
+//
+// Error Messages
+//
+#define I2C_ERROR 0xFFFF
+#define I2C_ARB_LOST_ERROR 0x0001
+#define I2C_NACK_ERROR 0x0002
+#define I2C_BUS_BUSY_ERROR 0x1000
+#define I2C_STP_NOT_READY_ERROR 0x5555
+#define I2C_NO_FLAGS 0xAAAA
+#define I2C_SUCCESS 0x0000
+
+//
+// Clear Status Flags
+//
+#define I2C_CLR_AL_BIT 0x0001
+#define I2C_CLR_NACK_BIT 0x0002
+#define I2C_CLR_ARDY_BIT 0x0004
+#define I2C_CLR_RRDY_BIT 0x0008
+#define I2C_CLR_SCD_BIT 0x0020
+
+//
+// Interrupt Source Messages
+//
+#define I2C_NO_ISRC 0x0000
+#define I2C_ARB_ISRC 0x0001
+#define I2C_NACK_ISRC 0x0002
+#define I2C_ARDY_ISRC 0x0003
+#define I2C_RX_ISRC 0x0004
+#define I2C_TX_ISRC 0x0005
+#define I2C_SCD_ISRC 0x0006
+#define I2C_AAS_ISRC 0x0007
+
+//
+// I2CMSG structure defines
+//
+#define I2C_NO_STOP 0
+#define I2C_YES_STOP 1
+#define I2C_RECEIVE 0
+#define I2C_TRANSMIT 1
+#define I2C_MAX_BUFFER_SIZE 16
+
+//
+// I2C Slave State defines
+//
+#define I2C_NOTSLAVE 0
+#define I2C_ADDR_AS_SLAVE 1
+#define I2C_ST_MSG_READY 2
+
+//
+// I2C Slave Receiver messages defines
+//
+#define I2C_SND_MSG1 1
+#define I2C_SND_MSG2 2
+
+//
+// I2C State defines
+//
+#define I2C_IDLE 0
+#define I2C_SLAVE_RECEIVER 1
+#define I2C_SLAVE_TRANSMITTER 2
+#define I2C_MASTER_RECEIVER 3
+#define I2C_MASTER_TRANSMITTER 4
+
+//
+// I2C Message Commands for I2CMSG struct
+//
+#define I2C_MSGSTAT_INACTIVE 0x0000
+#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
+#define I2C_MSGSTAT_WRITE_BUSY 0x0011
+#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
+#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
+#define I2C_MSGSTAT_RESTART 0x0022
+#define I2C_MSGSTAT_READ_BUSY 0x0023
+
+//
+// Generic defines
+//
+#define I2C_TRUE 1
+#define I2C_FALSE 0
+#define I2C_YES 1
+#define I2C_NO 0
+#define I2C_DUMMY_BYTE 0
+
+//
+// Structures
+//
+
+//
+// I2C Message Structure
+//
+struct I2CMSG
+{
+ Uint16 MsgStatus; // Word stating what state msg is in:
+ // I2C_MSGCMD_INACTIVE = do not send msg
+ // I2C_MSGCMD_BUSY = msg start has been sent,
+ // awaiting stop
+ // I2C_MSGCMD_SEND_WITHSTOP = command to send
+ // master trans msg complete with a stop bit
+ // I2C_MSGCMD_SEND_NOSTOP = command to send
+ // master trans msg without the stop bit
+ // I2C_MSGCMD_RESTART = command to send a restart
+ // as a master receiver with a stop bit
+ Uint16 SlaveAddress; // I2C address of slave msg is intended for
+ Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
+
+ //
+ // EEPROM address of data associated with msg (high byte)
+ //
+ Uint16 MemoryHighAddr;
+
+ //
+ // EEPROM address of data associated with msg (low byte)
+ //
+ Uint16 MemoryLowAddr;
+
+ //
+ // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to
+ // the FIFO's
+ Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE];
+};
+
+
+#endif // end of DSP2833x_I2C_DEFINES_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Mcbsp.h b/bsp/include/DSP2833x_Mcbsp.h
new file mode 100644
index 0000000..13e9cad
--- /dev/null
+++ b/bsp/include/DSP2833x_Mcbsp.h
@@ -0,0 +1,807 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: May 14, 2008 16:30:31 $
+//###########################################################################
+//
+// FILE: DSP2833x_Mcbsp.h
+//
+// TITLE: DSP2833x Device McBSP Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_MCBSP_H
+#define DSP2833x_MCBSP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// McBSP Individual Register Bit Definitions
+//
+
+//
+// McBSP DRR2 register bit definitions
+//
+struct DRR2_BITS { // bit description
+ Uint16 HWLB:8; // 16:23 High word low byte
+ Uint16 HWHB:8; // 24:31 High word high byte
+};
+
+union DRR2_REG {
+ Uint16 all;
+ struct DRR2_BITS bit;
+};
+
+//
+// McBSP DRR1 register bit definitions
+//
+struct DRR1_BITS { // bit description
+ Uint16 LWLB:8; // 16:23 Low word low byte
+ Uint16 LWHB:8; // 24:31 low word high byte
+};
+
+union DRR1_REG {
+ Uint16 all;
+ struct DRR1_BITS bit;
+};
+
+//
+// McBSP DXR2 register bit definitions
+//
+struct DXR2_BITS { // bit description
+ Uint16 HWLB:8; // 16:23 High word low byte
+ Uint16 HWHB:8; // 24:31 High word high byte
+};
+
+union DXR2_REG {
+ Uint16 all;
+ struct DXR2_BITS bit;
+};
+
+//
+// McBSP DXR1 register bit definitions
+//
+struct DXR1_BITS { // bit description
+ Uint16 LWLB:8; // 16:23 Low word low byte
+ Uint16 LWHB:8; // 24:31 low word high byte
+};
+
+union DXR1_REG {
+ Uint16 all;
+ struct DXR1_BITS bit;
+};
+
+//
+// SPCR2 control register bit definitions
+//
+struct SPCR2_BITS { // bit description
+ Uint16 XRST:1; // 0 transmit reset
+ Uint16 XRDY:1; // 1 transmit ready
+ Uint16 XEMPTY:1; // 2 Transmit empty
+ Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
+ Uint16 XINTM:2; // 5:4 Transmit interrupt types
+ Uint16 GRST:1; // 6 CLKG reset
+ Uint16 FRST:1; // 7 Frame sync reset
+ Uint16 SOFT:1; // 8 SOFT bit
+ Uint16 FREE:1; // 9 FREE bit
+ Uint16 rsvd:6; // 15:10 reserved
+};
+
+union SPCR2_REG {
+ Uint16 all;
+ struct SPCR2_BITS bit;
+};
+
+//
+// SPCR1 control register bit definitions
+//
+struct SPCR1_BITS { // bit description
+ Uint16 RRST:1; // 0 Receive reset
+ Uint16 RRDY:1; // 1 Receive ready
+ Uint16 RFULL:1; // 2 Receive full
+ Uint16 RSYNCERR:1; // 7 Receive syn error
+ Uint16 RINTM:2; // 5:4 Receive interrupt types
+ Uint16 rsvd1:1; // 6 reserved
+ Uint16 DXENA:1; // 7 DX hi-z enable
+ Uint16 rsvd2:3; // 10:8 reserved
+ Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
+ Uint16 RJUST:2; // 13:14 Right justified
+ Uint16 DLB:1; // 15 Digital loop back
+};
+
+union SPCR1_REG {
+ Uint16 all;
+ struct SPCR1_BITS bit;
+};
+
+//
+// RCR2 control register bit definitions
+//
+struct RCR2_BITS { // bit description
+ Uint16 RDATDLY:2; // 1:0 Receive data delay
+ Uint16 RFIG:1; // 2 Receive frame sync ignore
+ Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
+ Uint16 RWDLEN2:3; // 7:5 Receive word length
+ Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
+ Uint16 RPHASE:1; // 15 Receive Phase
+};
+
+union RCR2_REG {
+ Uint16 all;
+ struct RCR2_BITS bit;
+};
+
+//
+// RCR1 control register bit definitions
+//
+struct RCR1_BITS { // bit description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 RWDLEN1:3; // 7:5 Receive word length
+ Uint16 RFRLEN1:7; // 14:8 Receive frame length
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union RCR1_REG {
+ Uint16 all;
+ struct RCR1_BITS bit;
+};
+
+//
+// XCR2 control register bit definitions
+//
+struct XCR2_BITS { // bit description
+ Uint16 XDATDLY:2; // 1:0 Transmit data delay
+ Uint16 XFIG:1; // 2 Transmit frame sync ignore
+ Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
+ Uint16 XWDLEN2:3; // 7:5 Transmit word length
+ Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
+ Uint16 XPHASE:1; // 15 Transmit Phase
+};
+
+union XCR2_REG {
+ Uint16 all;
+ struct XCR2_BITS bit;
+};
+
+//
+// XCR1 control register bit definitions
+//
+struct XCR1_BITS { // bit description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 XWDLEN1:3; // 7:5 Transmit word length
+ Uint16 XFRLEN1:7; // 14:8 Transmit frame length
+ Uint16 rsvd2:1; // 15 reserved
+};
+
+union XCR1_REG {
+ Uint16 all;
+ struct XCR1_BITS bit;
+};
+
+//
+// SRGR2 Sample rate generator control register bit definitions
+//
+struct SRGR2_BITS { // bit description
+ Uint16 FPER:12; // 11:0 Frame period
+ Uint16 FSGM:1; // 12 Frame sync generator mode
+ Uint16 CLKSM:1; // 13 Sample rate generator mode
+ Uint16 rsvd:1; // 14 reserved
+ Uint16 GSYNC:1; // 15 CLKG sync
+};
+
+union SRGR2_REG {
+ Uint16 all;
+ struct SRGR2_BITS bit;
+};
+
+//
+// SRGR1 control register bit definitions
+//
+struct SRGR1_BITS { // bit description
+ Uint16 CLKGDV:8; // 7:0 CLKG divider
+ Uint16 FWID:8; // 15:8 Frame width
+};
+
+union SRGR1_REG {
+ Uint16 all;
+ struct SRGR1_BITS bit;
+};
+
+//
+// MCR2 Multichannel control register bit definitions
+//
+struct MCR2_BITS { // bit description
+ Uint16 XMCM:2; // 1:0 Transmit multichannel mode
+ Uint16 XCBLK:3; // 2:4 Transmit current block
+ Uint16 XPABLK:2; // 5:6 Transmit partition A Block
+ Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
+ Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
+ Uint16 rsvd:6; // 15:10 reserved
+};
+
+union MCR2_REG {
+ Uint16 all;
+ struct MCR2_BITS bit;
+};
+
+//
+// MCR1 Multichannel control register bit definitions
+//
+struct MCR1_BITS { // bit description
+ Uint16 RMCM:1; // 0 Receive multichannel mode
+ Uint16 rsvd:1; // 1 reserved
+ Uint16 RCBLK:3; // 4:2 Receive current block
+ Uint16 RPABLK:2; // 6:5 Receive partition A Block
+ Uint16 RPBBLK:2; // 7:8 Receive partition B Block
+ Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
+ Uint16 rsvd1:6; // 15:10 reserved
+};
+
+union MCR1_REG {
+ Uint16 all;
+ struct MCR1_BITS bit;
+};
+
+//
+// RCERA control register bit definitions
+//
+struct RCERA_BITS { // bit description
+ Uint16 RCEA0:1; // 0 Receive Channel enable bit
+ Uint16 RCEA1:1; // 1 Receive Channel enable bit
+ Uint16 RCEA2:1; // 2 Receive Channel enable bit
+ Uint16 RCEA3:1; // 3 Receive Channel enable bit
+ Uint16 RCEA4:1; // 4 Receive Channel enable bit
+ Uint16 RCEA5:1; // 5 Receive Channel enable bit
+ Uint16 RCEA6:1; // 6 Receive Channel enable bit
+ Uint16 RCEA7:1; // 7 Receive Channel enable bit
+ Uint16 RCEA8:1; // 8 Receive Channel enable bit
+ Uint16 RCEA9:1; // 9 Receive Channel enable bit
+ Uint16 RCEA10:1; // 10 Receive Channel enable bit
+ Uint16 RCEA11:1; // 11 Receive Channel enable bit
+ Uint16 RCEA12:1; // 12 Receive Channel enable bit
+ Uint16 RCEA13:1; // 13 Receive Channel enable bit
+ Uint16 RCEA14:1; // 14 Receive Channel enable bit
+ Uint16 RCEA15:1; // 15 Receive Channel enable bit
+};
+
+union RCERA_REG {
+ Uint16 all;
+ struct RCERA_BITS bit;
+};
+
+//
+// RCERB control register bit definitions
+//
+struct RCERB_BITS { // bit description
+ Uint16 RCEB0:1; // 0 Receive Channel enable bit
+ Uint16 RCEB1:1; // 1 Receive Channel enable bit
+ Uint16 RCEB2:1; // 2 Receive Channel enable bit
+ Uint16 RCEB3:1; // 3 Receive Channel enable bit
+ Uint16 RCEB4:1; // 4 Receive Channel enable bit
+ Uint16 RCEB5:1; // 5 Receive Channel enable bit
+ Uint16 RCEB6:1; // 6 Receive Channel enable bit
+ Uint16 RCEB7:1; // 7 Receive Channel enable bit
+ Uint16 RCEB8:1; // 8 Receive Channel enable bit
+ Uint16 RCEB9:1; // 9 Receive Channel enable bit
+ Uint16 RCEB10:1; // 10 Receive Channel enable bit
+ Uint16 RCEB11:1; // 11 Receive Channel enable bit
+ Uint16 RCEB12:1; // 12 Receive Channel enable bit
+ Uint16 RCEB13:1; // 13 Receive Channel enable bit
+ Uint16 RCEB14:1; // 14 Receive Channel enable bit
+ Uint16 RCEB15:1; // 15 Receive Channel enable bit
+};
+
+union RCERB_REG {
+ Uint16 all;
+ struct RCERB_BITS bit;
+};
+
+//
+// XCERA control register bit definitions
+//
+struct XCERA_BITS { // bit description
+ Uint16 XCERA0:1; // 0 Receive Channel enable bit
+ Uint16 XCERA1:1; // 1 Receive Channel enable bit
+ Uint16 XCERA2:1; // 2 Receive Channel enable bit
+ Uint16 XCERA3:1; // 3 Receive Channel enable bit
+ Uint16 XCERA4:1; // 4 Receive Channel enable bit
+ Uint16 XCERA5:1; // 5 Receive Channel enable bit
+ Uint16 XCERA6:1; // 6 Receive Channel enable bit
+ Uint16 XCERA7:1; // 7 Receive Channel enable bit
+ Uint16 XCERA8:1; // 8 Receive Channel enable bit
+ Uint16 XCERA9:1; // 9 Receive Channel enable bit
+ Uint16 XCERA10:1; // 10 Receive Channel enable bit
+ Uint16 XCERA11:1; // 11 Receive Channel enable bit
+ Uint16 XCERA12:1; // 12 Receive Channel enable bit
+ Uint16 XCERA13:1; // 13 Receive Channel enable bit
+ Uint16 XCERA14:1; // 14 Receive Channel enable bit
+ Uint16 XCERA15:1; // 15 Receive Channel enable bit
+};
+
+union XCERA_REG {
+ Uint16 all;
+ struct XCERA_BITS bit;
+};
+
+//
+// XCERB control register bit definitions
+//
+struct XCERB_BITS { // bit description
+ Uint16 XCERB0:1; // 0 Receive Channel enable bit
+ Uint16 XCERB1:1; // 1 Receive Channel enable bit
+ Uint16 XCERB2:1; // 2 Receive Channel enable bit
+ Uint16 XCERB3:1; // 3 Receive Channel enable bit
+ Uint16 XCERB4:1; // 4 Receive Channel enable bit
+ Uint16 XCERB5:1; // 5 Receive Channel enable bit
+ Uint16 XCERB6:1; // 6 Receive Channel enable bit
+ Uint16 XCERB7:1; // 7 Receive Channel enable bit
+ Uint16 XCERB8:1; // 8 Receive Channel enable bit
+ Uint16 XCERB9:1; // 9 Receive Channel enable bit
+ Uint16 XCERB10:1; // 10 Receive Channel enable bit
+ Uint16 XCERB11:1; // 11 Receive Channel enable bit
+ Uint16 XCERB12:1; // 12 Receive Channel enable bit
+ Uint16 XCERB13:1; // 13 Receive Channel enable bit
+ Uint16 XCERB14:1; // 14 Receive Channel enable bit
+ Uint16 XCERB15:1; // 15 Receive Channel enable bit
+};
+
+union XCERB_REG {
+ Uint16 all;
+ struct XCERB_BITS bit;
+};
+
+//
+// PCR control register bit definitions
+//
+struct PCR_BITS { // bit description
+ Uint16 CLKRP:1; // 0 Receive Clock polarity
+ Uint16 CLKXP:1; // 1 Transmit clock polarity
+ Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
+ Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
+ Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
+ Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
+ Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
+ Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
+ Uint16 CLKRM:1; // 8 Receiver Clock Mode
+ Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
+ Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
+ Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
+ Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in
+ // this 28x-McBSP
+ Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in
+ // this 28x-McBSP
+ Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
+ Uint16 rsvd:1 ; // 15 reserved
+};
+
+union PCR_REG {
+ Uint16 all;
+ struct PCR_BITS bit;
+};
+
+//
+// RCERC control register bit definitions
+//
+struct RCERC_BITS { // bit description
+ Uint16 RCEC0:1; // 0 Receive Channel enable bit
+ Uint16 RCEC1:1; // 1 Receive Channel enable bit
+ Uint16 RCEC2:1; // 2 Receive Channel enable bit
+ Uint16 RCEC3:1; // 3 Receive Channel enable bit
+ Uint16 RCEC4:1; // 4 Receive Channel enable bit
+ Uint16 RCEC5:1; // 5 Receive Channel enable bit
+ Uint16 RCEC6:1; // 6 Receive Channel enable bit
+ Uint16 RCEC7:1; // 7 Receive Channel enable bit
+ Uint16 RCEC8:1; // 8 Receive Channel enable bit
+ Uint16 RCEC9:1; // 9 Receive Channel enable bit
+ Uint16 RCEC10:1; // 10 Receive Channel enable bit
+ Uint16 RCEC11:1; // 11 Receive Channel enable bit
+ Uint16 RCEC12:1; // 12 Receive Channel enable bit
+ Uint16 RCEC13:1; // 13 Receive Channel enable bit
+ Uint16 RCEC14:1; // 14 Receive Channel enable bit
+ Uint16 RCEC15:1; // 15 Receive Channel enable bit
+};
+
+union RCERC_REG {
+ Uint16 all;
+ struct RCERC_BITS bit;
+};
+
+//
+// RCERD control register bit definitions
+//
+struct RCERD_BITS { // bit description
+ Uint16 RCED0:1; // 0 Receive Channel enable bit
+ Uint16 RCED1:1; // 1 Receive Channel enable bit
+ Uint16 RCED2:1; // 2 Receive Channel enable bit
+ Uint16 RCED3:1; // 3 Receive Channel enable bit
+ Uint16 RCED4:1; // 4 Receive Channel enable bit
+ Uint16 RCED5:1; // 5 Receive Channel enable bit
+ Uint16 RCED6:1; // 6 Receive Channel enable bit
+ Uint16 RCED7:1; // 7 Receive Channel enable bit
+ Uint16 RCED8:1; // 8 Receive Channel enable bit
+ Uint16 RCED9:1; // 9 Receive Channel enable bit
+ Uint16 RCED10:1; // 10 Receive Channel enable bit
+ Uint16 RCED11:1; // 11 Receive Channel enable bit
+ Uint16 RCED12:1; // 12 Receive Channel enable bit
+ Uint16 RCED13:1; // 13 Receive Channel enable bit
+ Uint16 RCED14:1; // 14 Receive Channel enable bit
+ Uint16 RCED15:1; // 15 Receive Channel enable bit
+};
+
+union RCERD_REG {
+ Uint16 all;
+ struct RCERD_BITS bit;
+};
+
+//
+// XCERC control register bit definitions
+//
+struct XCERC_BITS { // bit description
+ Uint16 XCERC0:1; // 0 Receive Channel enable bit
+ Uint16 XCERC1:1; // 1 Receive Channel enable bit
+ Uint16 XCERC2:1; // 2 Receive Channel enable bit
+ Uint16 XCERC3:1; // 3 Receive Channel enable bit
+ Uint16 XCERC4:1; // 4 Receive Channel enable bit
+ Uint16 XCERC5:1; // 5 Receive Channel enable bit
+ Uint16 XCERC6:1; // 6 Receive Channel enable bit
+ Uint16 XCERC7:1; // 7 Receive Channel enable bit
+ Uint16 XCERC8:1; // 8 Receive Channel enable bit
+ Uint16 XCERC9:1; // 9 Receive Channel enable bit
+ Uint16 XCERC10:1; // 10 Receive Channel enable bit
+ Uint16 XCERC11:1; // 11 Receive Channel enable bit
+ Uint16 XCERC12:1; // 12 Receive Channel enable bit
+ Uint16 XCERC13:1; // 13 Receive Channel enable bit
+ Uint16 XCERC14:1; // 14 Receive Channel enable bit
+ Uint16 XCERC15:1; // 15 Receive Channel enable bit
+};
+
+union XCERC_REG {
+ Uint16 all;
+ struct XCERC_BITS bit;
+};
+
+//
+// XCERD control register bit definitions
+//
+struct XCERD_BITS { // bit description
+ Uint16 XCERD0:1; // 0 Receive Channel enable bit
+ Uint16 XCERD1:1; // 1 Receive Channel enable bit
+ Uint16 XCERD2:1; // 2 Receive Channel enable bit
+ Uint16 XCERD3:1; // 3 Receive Channel enable bit
+ Uint16 XCERD4:1; // 4 Receive Channel enable bit
+ Uint16 XCERD5:1; // 5 Receive Channel enable bit
+ Uint16 XCERD6:1; // 6 Receive Channel enable bit
+ Uint16 XCERD7:1; // 7 Receive Channel enable bit
+ Uint16 XCERD8:1; // 8 Receive Channel enable bit
+ Uint16 XCERD9:1; // 9 Receive Channel enable bit
+ Uint16 XCERD10:1; // 10 Receive Channel enable bit
+ Uint16 XCERD11:1; // 11 Receive Channel enable bit
+ Uint16 XCERD12:1; // 12 Receive Channel enable bit
+ Uint16 XCERD13:1; // 13 Receive Channel enable bit
+ Uint16 XCERD14:1; // 14 Receive Channel enable bit
+ Uint16 XCERD15:1; // 15 Receive Channel enable bit
+};
+
+union XCERD_REG {
+ Uint16 all;
+ struct XCERD_BITS bit;
+};
+
+//
+// RCERE control register bit definitions
+//
+struct RCERE_BITS { // bit description
+ Uint16 RCEE0:1; // 0 Receive Channel enable bit
+ Uint16 RCEE1:1; // 1 Receive Channel enable bit
+ Uint16 RCEE2:1; // 2 Receive Channel enable bit
+ Uint16 RCEE3:1; // 3 Receive Channel enable bit
+ Uint16 RCEE4:1; // 4 Receive Channel enable bit
+ Uint16 RCEE5:1; // 5 Receive Channel enable bit
+ Uint16 RCEE6:1; // 6 Receive Channel enable bit
+ Uint16 RCEE7:1; // 7 Receive Channel enable bit
+ Uint16 RCEE8:1; // 8 Receive Channel enable bit
+ Uint16 RCEE9:1; // 9 Receive Channel enable bit
+ Uint16 RCEE10:1; // 10 Receive Channel enable bit
+ Uint16 RCEE11:1; // 11 Receive Channel enable bit
+ Uint16 RCEE12:1; // 12 Receive Channel enable bit
+ Uint16 RCEE13:1; // 13 Receive Channel enable bit
+ Uint16 RCEE14:1; // 14 Receive Channel enable bit
+ Uint16 RCEE15:1; // 15 Receive Channel enable bit
+};
+
+union RCERE_REG {
+ Uint16 all;
+ struct RCERE_BITS bit;
+};
+
+//
+// RCERF control register bit definitions
+//
+struct RCERF_BITS { // bit description
+ Uint16 RCEF0:1; // 0 Receive Channel enable bit
+ Uint16 RCEF1:1; // 1 Receive Channel enable bit
+ Uint16 RCEF2:1; // 2 Receive Channel enable bit
+ Uint16 RCEF3:1; // 3 Receive Channel enable bit
+ Uint16 RCEF4:1; // 4 Receive Channel enable bit
+ Uint16 RCEF5:1; // 5 Receive Channel enable bit
+ Uint16 RCEF6:1; // 6 Receive Channel enable bit
+ Uint16 RCEF7:1; // 7 Receive Channel enable bit
+ Uint16 RCEF8:1; // 8 Receive Channel enable bit
+ Uint16 RCEF9:1; // 9 Receive Channel enable bit
+ Uint16 RCEF10:1; // 10 Receive Channel enable bit
+ Uint16 RCEF11:1; // 11 Receive Channel enable bit
+ Uint16 RCEF12:1; // 12 Receive Channel enable bit
+ Uint16 RCEF13:1; // 13 Receive Channel enable bit
+ Uint16 RCEF14:1; // 14 Receive Channel enable bit
+ Uint16 RCEF15:1; // 15 Receive Channel enable bit
+};
+
+union RCERF_REG {
+ Uint16 all;
+ struct RCERF_BITS bit;
+};
+
+// XCERE control register bit definitions:
+struct XCERE_BITS { // bit description
+ Uint16 XCERE0:1; // 0 Receive Channel enable bit
+ Uint16 XCERE1:1; // 1 Receive Channel enable bit
+ Uint16 XCERE2:1; // 2 Receive Channel enable bit
+ Uint16 XCERE3:1; // 3 Receive Channel enable bit
+ Uint16 XCERE4:1; // 4 Receive Channel enable bit
+ Uint16 XCERE5:1; // 5 Receive Channel enable bit
+ Uint16 XCERE6:1; // 6 Receive Channel enable bit
+ Uint16 XCERE7:1; // 7 Receive Channel enable bit
+ Uint16 XCERE8:1; // 8 Receive Channel enable bit
+ Uint16 XCERE9:1; // 9 Receive Channel enable bit
+ Uint16 XCERE10:1; // 10 Receive Channel enable bit
+ Uint16 XCERE11:1; // 11 Receive Channel enable bit
+ Uint16 XCERE12:1; // 12 Receive Channel enable bit
+ Uint16 XCERE13:1; // 13 Receive Channel enable bit
+ Uint16 XCERE14:1; // 14 Receive Channel enable bit
+ Uint16 XCERE15:1; // 15 Receive Channel enable bit
+};
+
+union XCERE_REG {
+ Uint16 all;
+ struct XCERE_BITS bit;
+};
+
+//
+// XCERF control register bit definitions
+//
+struct XCERF_BITS { // bit description
+ Uint16 XCERF0:1; // 0 Receive Channel enable bit
+ Uint16 XCERF1:1; // 1 Receive Channel enable bit
+ Uint16 XCERF2:1; // 2 Receive Channel enable bit
+ Uint16 XCERF3:1; // 3 Receive Channel enable bit
+ Uint16 XCERF4:1; // 4 Receive Channel enable bit
+ Uint16 XCERF5:1; // 5 Receive Channel enable bit
+ Uint16 XCERF6:1; // 6 Receive Channel enable bit
+ Uint16 XCERF7:1; // 7 Receive Channel enable bit
+ Uint16 XCERF8:1; // 8 Receive Channel enable bit
+ Uint16 XCERF9:1; // 9 Receive Channel enable bit
+ Uint16 XCERF10:1; // 10 Receive Channel enable bit
+ Uint16 XCERF11:1; // 11 Receive Channel enable bit
+ Uint16 XCERF12:1; // 12 Receive Channel enable bit
+ Uint16 XCERF13:1; // 13 Receive Channel enable bit
+ Uint16 XCERF14:1; // 14 Receive Channel enable bit
+ Uint16 XCERF15:1; // 15 Receive Channel enable bit
+};
+
+union XCERF_REG {
+ Uint16 all;
+ struct XCERF_BITS bit;
+};
+
+//
+// RCERG control register bit definitions
+//
+struct RCERG_BITS { // bit description
+ Uint16 RCEG0:1; // 0 Receive Channel enable bit
+ Uint16 RCEG1:1; // 1 Receive Channel enable bit
+ Uint16 RCEG2:1; // 2 Receive Channel enable bit
+ Uint16 RCEG3:1; // 3 Receive Channel enable bit
+ Uint16 RCEG4:1; // 4 Receive Channel enable bit
+ Uint16 RCEG5:1; // 5 Receive Channel enable bit
+ Uint16 RCEG6:1; // 6 Receive Channel enable bit
+ Uint16 RCEG7:1; // 7 Receive Channel enable bit
+ Uint16 RCEG8:1; // 8 Receive Channel enable bit
+ Uint16 RCEG9:1; // 9 Receive Channel enable bit
+ Uint16 RCEG10:1; // 10 Receive Channel enable bit
+ Uint16 RCEG11:1; // 11 Receive Channel enable bit
+ Uint16 RCEG12:1; // 12 Receive Channel enable bit
+ Uint16 RCEG13:1; // 13 Receive Channel enable bit
+ Uint16 RCEG14:1; // 14 Receive Channel enable bit
+ Uint16 RCEG15:1; // 15 Receive Channel enable bit
+};
+
+union RCERG_REG {
+ Uint16 all;
+ struct RCERG_BITS bit;
+};
+
+// RCERH control register bit definitions:
+struct RCERH_BITS { // bit description
+ Uint16 RCEH0:1; // 0 Receive Channel enable bit
+ Uint16 RCEH1:1; // 1 Receive Channel enable bit
+ Uint16 RCEH2:1; // 2 Receive Channel enable bit
+ Uint16 RCEH3:1; // 3 Receive Channel enable bit
+ Uint16 RCEH4:1; // 4 Receive Channel enable bit
+ Uint16 RCEH5:1; // 5 Receive Channel enable bit
+ Uint16 RCEH6:1; // 6 Receive Channel enable bit
+ Uint16 RCEH7:1; // 7 Receive Channel enable bit
+ Uint16 RCEH8:1; // 8 Receive Channel enable bit
+ Uint16 RCEH9:1; // 9 Receive Channel enable bit
+ Uint16 RCEH10:1; // 10 Receive Channel enable bit
+ Uint16 RCEH11:1; // 11 Receive Channel enable bit
+ Uint16 RCEH12:1; // 12 Receive Channel enable bit
+ Uint16 RCEH13:1; // 13 Receive Channel enable bit
+ Uint16 RCEH14:1; // 14 Receive Channel enable bit
+ Uint16 RCEH15:1; // 15 Receive Channel enable bit
+};
+
+union RCERH_REG {
+ Uint16 all;
+ struct RCERH_BITS bit;
+};
+
+//
+// XCERG control register bit definitions
+//
+struct XCERG_BITS { // bit description
+ Uint16 XCERG0:1; // 0 Receive Channel enable bit
+ Uint16 XCERG1:1; // 1 Receive Channel enable bit
+ Uint16 XCERG2:1; // 2 Receive Channel enable bit
+ Uint16 XCERG3:1; // 3 Receive Channel enable bit
+ Uint16 XCERG4:1; // 4 Receive Channel enable bit
+ Uint16 XCERG5:1; // 5 Receive Channel enable bit
+ Uint16 XCERG6:1; // 6 Receive Channel enable bit
+ Uint16 XCERG7:1; // 7 Receive Channel enable bit
+ Uint16 XCERG8:1; // 8 Receive Channel enable bit
+ Uint16 XCERG9:1; // 9 Receive Channel enable bit
+ Uint16 XCERG10:1; // 10 Receive Channel enable bit
+ Uint16 XCERG11:1; // 11 Receive Channel enable bit
+ Uint16 XCERG12:1; // 12 Receive Channel enable bit
+ Uint16 XCERG13:1; // 13 Receive Channel enable bit
+ Uint16 XCERG14:1; // 14 Receive Channel enable bit
+ Uint16 XCERG15:1; // 15 Receive Channel enable bit
+};
+
+union XCERG_REG {
+ Uint16 all;
+ struct XCERG_BITS bit;
+};
+
+//
+// XCERH control register bit definitions
+//
+struct XCERH_BITS { // bit description
+ Uint16 XCEH0:1; // 0 Receive Channel enable bit
+ Uint16 XCEH1:1; // 1 Receive Channel enable bit
+ Uint16 XCEH2:1; // 2 Receive Channel enable bit
+ Uint16 XCEH3:1; // 3 Receive Channel enable bit
+ Uint16 XCEH4:1; // 4 Receive Channel enable bit
+ Uint16 XCEH5:1; // 5 Receive Channel enable bit
+ Uint16 XCEH6:1; // 6 Receive Channel enable bit
+ Uint16 XCEH7:1; // 7 Receive Channel enable bit
+ Uint16 XCEH8:1; // 8 Receive Channel enable bit
+ Uint16 XCEH9:1; // 9 Receive Channel enable bit
+ Uint16 XCEH10:1; // 10 Receive Channel enable bit
+ Uint16 XCEH11:1; // 11 Receive Channel enable bit
+ Uint16 XCEH12:1; // 12 Receive Channel enable bit
+ Uint16 XCEH13:1; // 13 Receive Channel enable bit
+ Uint16 XCEH14:1; // 14 Receive Channel enable bit
+ Uint16 XCEH15:1; // 15 Receive Channel enable bit
+};
+
+union XCERH_REG {
+ Uint16 all;
+ struct XCERH_BITS bit;
+};
+
+//
+// McBSP Interrupt enable register for RINT/XINT
+//
+struct MFFINT_BITS { // bits description
+ Uint16 XINT:1; // 0 XINT interrupt enable
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 RINT:1; // 2 RINT interrupt enable
+ Uint16 rsvd2:13; // 15:3 reserved
+};
+
+union MFFINT_REG {
+ Uint16 all;
+ struct MFFINT_BITS bit;
+};
+
+//
+// McBSP Register File
+//
+struct MCBSP_REGS {
+ union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
+ union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
+ union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
+ union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
+ union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
+ union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
+ union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
+ union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
+ union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
+ union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
+ union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
+ union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
+ union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
+ union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
+ union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
+ union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
+ union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
+ union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
+ union PCR_REG PCR; // MCBSP Pin control register bits 15-0
+ union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
+ union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
+ union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
+ union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
+ union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
+ union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
+ union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
+ union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
+ union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
+ union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
+ union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
+ union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
+ Uint16 rsvd1[4]; // reserved
+ union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for
+ // RINT/XINT
+ Uint16 rsvd2; // reserved
+};
+
+//
+// McBSP External References & Function Declarations
+//
+extern volatile struct MCBSP_REGS McbspaRegs;
+extern volatile struct MCBSP_REGS McbspbRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_MCBSP_H definition
+
+//
+// No more
+//
+
diff --git a/bsp/include/DSP2833x_PieCtrl.h b/bsp/include/DSP2833x_PieCtrl.h
new file mode 100644
index 0000000..10c7b7c
--- /dev/null
+++ b/bsp/include/DSP2833x_PieCtrl.h
@@ -0,0 +1,195 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:24 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieCtrl.h
+//
+// TITLE: DSP2833x Device PIE Control Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_PIE_CTRL_H
+#define DSP2833x_PIE_CTRL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// PIE Control Register Bit Definitions
+//
+
+//
+// PIECTRL: Register bit definitions
+//
+struct PIECTRL_BITS { // bits description
+ Uint16 ENPIE:1; // 0 Enable PIE block
+ Uint16 PIEVECT:15; // 15:1 Fetched vector address
+};
+
+union PIECTRL_REG {
+ Uint16 all;
+ struct PIECTRL_BITS bit;
+};
+
+//
+// PIEIER: Register bit definitions
+//
+struct PIEIER_BITS { // bits description
+ Uint16 INTx1:1; // 0 INTx.1
+ Uint16 INTx2:1; // 1 INTx.2
+ Uint16 INTx3:1; // 2 INTx.3
+ Uint16 INTx4:1; // 3 INTx.4
+ Uint16 INTx5:1; // 4 INTx.5
+ Uint16 INTx6:1; // 5 INTx.6
+ Uint16 INTx7:1; // 6 INTx.7
+ Uint16 INTx8:1; // 7 INTx.8
+ Uint16 rsvd:8; // 15:8 reserved
+};
+
+union PIEIER_REG {
+ Uint16 all;
+ struct PIEIER_BITS bit;
+};
+
+//
+// PIEIFR: Register bit definitions
+//
+struct PIEIFR_BITS { // bits description
+ Uint16 INTx1:1; // 0 INTx.1
+ Uint16 INTx2:1; // 1 INTx.2
+ Uint16 INTx3:1; // 2 INTx.3
+ Uint16 INTx4:1; // 3 INTx.4
+ Uint16 INTx5:1; // 4 INTx.5
+ Uint16 INTx6:1; // 5 INTx.6
+ Uint16 INTx7:1; // 6 INTx.7
+ Uint16 INTx8:1; // 7 INTx.8
+ Uint16 rsvd:8; // 15:8 reserved
+};
+
+union PIEIFR_REG {
+ Uint16 all;
+ struct PIEIFR_BITS bit;
+};
+
+//
+// PIEACK: Register bit definitions
+//
+struct PIEACK_BITS { // bits description
+ Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
+ Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
+ Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
+ Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
+ Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
+ Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
+ Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
+ Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
+ Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
+ Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
+ Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
+ Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
+ Uint16 rsvd:4; // 15:12 reserved
+};
+
+union PIEACK_REG {
+ Uint16 all;
+ struct PIEACK_BITS bit;
+};
+
+//
+// PIE Control Register File
+//
+struct PIE_CTRL_REGS {
+ union PIECTRL_REG PIECTRL; // PIE control register
+ union PIEACK_REG PIEACK; // PIE acknowledge
+ union PIEIER_REG PIEIER1; // PIE int1 IER register
+ union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
+ union PIEIER_REG PIEIER2; // PIE INT2 IER register
+ union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
+ union PIEIER_REG PIEIER3; // PIE INT3 IER register
+ union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
+ union PIEIER_REG PIEIER4; // PIE INT4 IER register
+ union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
+ union PIEIER_REG PIEIER5; // PIE INT5 IER register
+ union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
+ union PIEIER_REG PIEIER6; // PIE INT6 IER register
+ union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
+ union PIEIER_REG PIEIER7; // PIE INT7 IER register
+ union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
+ union PIEIER_REG PIEIER8; // PIE INT8 IER register
+ union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
+ union PIEIER_REG PIEIER9; // PIE INT9 IER register
+ union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
+ union PIEIER_REG PIEIER10; // PIE int10 IER register
+ union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
+ union PIEIER_REG PIEIER11; // PIE int11 IER register
+ union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
+ union PIEIER_REG PIEIER12; // PIE int12 IER register
+ union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
+};
+
+//
+// Defines
+//
+#define PIEACK_GROUP1 0x0001
+#define PIEACK_GROUP2 0x0002
+#define PIEACK_GROUP3 0x0004
+#define PIEACK_GROUP4 0x0008
+#define PIEACK_GROUP5 0x0010
+#define PIEACK_GROUP6 0x0020
+#define PIEACK_GROUP7 0x0040
+#define PIEACK_GROUP8 0x0080
+#define PIEACK_GROUP9 0x0100
+#define PIEACK_GROUP10 0x0200
+#define PIEACK_GROUP11 0x0400
+#define PIEACK_GROUP12 0x0800
+
+//
+// PIE Control Registers External References & Function Declarations
+//
+extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_PIE_CTRL_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_PieVect.h b/bsp/include/DSP2833x_PieVect.h
new file mode 100644
index 0000000..4301b00
--- /dev/null
+++ b/bsp/include/DSP2833x_PieVect.h
@@ -0,0 +1,265 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 16, 2007 09:00:21 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieVect.h
+//
+// TITLE: DSP2833x Devices PIE Vector Table Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_PIE_VECT_H
+#define DSP2833x_PIE_VECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// PIE Interrupt Vector Table Definition
+//
+
+//
+// Typedef used to create a user type called PINT (pointer to interrupt)
+//
+typedef interrupt void(*PINT)(void);
+
+//
+// Vector Table Define
+//
+struct PIE_VECT_TABLE {
+ //
+ // Reset is never fetched from this table. It will always be fetched from
+ // 0x3FFFC0 in boot ROM
+ //
+ PINT PIE1_RESERVED;
+ PINT PIE2_RESERVED;
+ PINT PIE3_RESERVED;
+ PINT PIE4_RESERVED;
+ PINT PIE5_RESERVED;
+ PINT PIE6_RESERVED;
+ PINT PIE7_RESERVED;
+ PINT PIE8_RESERVED;
+ PINT PIE9_RESERVED;
+ PINT PIE10_RESERVED;
+ PINT PIE11_RESERVED;
+ PINT PIE12_RESERVED;
+ PINT PIE13_RESERVED;
+
+ //
+ // Non-Peripheral Interrupts
+ //
+ PINT XINT13; // XINT13 / CPU-Timer1
+ PINT TINT2; // CPU-Timer2
+ PINT DATALOG; // Datalogging interrupt
+ PINT RTOSINT; // RTOS interrupt
+ PINT EMUINT; // Emulation interrupt
+ PINT XNMI; // Non-maskable interrupt
+ PINT ILLEGAL; // Illegal operation TRAP
+ PINT USER1; // User Defined trap 1
+ PINT USER2; // User Defined trap 2
+ PINT USER3; // User Defined trap 3
+ PINT USER4; // User Defined trap 4
+ PINT USER5; // User Defined trap 5
+ PINT USER6; // User Defined trap 6
+ PINT USER7; // User Defined trap 7
+ PINT USER8; // User Defined trap 8
+ PINT USER9; // User Defined trap 9
+ PINT USER10; // User Defined trap 10
+ PINT USER11; // User Defined trap 11
+ PINT USER12; // User Defined trap 12
+
+ //
+ // Group 1 PIE Peripheral Vectors
+ //
+ PINT SEQ1INT;
+ PINT SEQ2INT;
+ PINT rsvd1_3;
+ PINT XINT1;
+ PINT XINT2;
+ PINT ADCINT; // ADC
+ PINT TINT0; // Timer 0
+ PINT WAKEINT; // WD
+
+ //
+ // Group 2 PIE Peripheral Vectors
+ //
+ PINT EPWM1_TZINT; // EPWM-1
+ PINT EPWM2_TZINT; // EPWM-2
+ PINT EPWM3_TZINT; // EPWM-3
+ PINT EPWM4_TZINT; // EPWM-4
+ PINT EPWM5_TZINT; // EPWM-5
+ PINT EPWM6_TZINT; // EPWM-6
+ PINT rsvd2_7;
+ PINT rsvd2_8;
+
+ //
+ // Group 3 PIE Peripheral Vectors
+ //
+ PINT EPWM1_INT; // EPWM-1
+ PINT EPWM2_INT; // EPWM-2
+ PINT EPWM3_INT; // EPWM-3
+ PINT EPWM4_INT; // EPWM-4
+ PINT EPWM5_INT; // EPWM-5
+ PINT EPWM6_INT; // EPWM-6
+ PINT rsvd3_7;
+ PINT rsvd3_8;
+
+ //
+ // Group 4 PIE Peripheral Vectors
+ //
+ PINT ECAP1_INT; // ECAP-1
+ PINT ECAP2_INT; // ECAP-2
+ PINT ECAP3_INT; // ECAP-3
+ PINT ECAP4_INT; // ECAP-4
+ PINT ECAP5_INT; // ECAP-5
+ PINT ECAP6_INT; // ECAP-6
+ PINT rsvd4_7;
+ PINT rsvd4_8;
+
+ //
+ // Group 5 PIE Peripheral Vectors
+ //
+ PINT EQEP1_INT; // EQEP-1
+ PINT EQEP2_INT; // EQEP-2
+ PINT rsvd5_3;
+ PINT rsvd5_4;
+ PINT rsvd5_5;
+ PINT rsvd5_6;
+ PINT rsvd5_7;
+ PINT rsvd5_8;
+
+ //
+ // Group 6 PIE Peripheral Vectors
+ //
+ PINT SPIRXINTA; // SPI-A
+ PINT SPITXINTA; // SPI-A
+ PINT MRINTB; // McBSP-B
+ PINT MXINTB; // McBSP-B
+ PINT MRINTA; // McBSP-A
+ PINT MXINTA; // McBSP-A
+ PINT rsvd6_7;
+ PINT rsvd6_8;
+
+ //
+ // Group 7 PIE Peripheral Vectors
+ //
+ PINT DINTCH1; // DMA
+ PINT DINTCH2; // DMA
+ PINT DINTCH3; // DMA
+ PINT DINTCH4; // DMA
+ PINT DINTCH5; // DMA
+ PINT DINTCH6; // DMA
+ PINT rsvd7_7;
+ PINT rsvd7_8;
+
+ //
+ // Group 8 PIE Peripheral Vectors
+ //
+ PINT I2CINT1A; // I2C-A
+ PINT I2CINT2A; // I2C-A
+ PINT rsvd8_3;
+ PINT rsvd8_4;
+ PINT SCIRXINTC; // SCI-C
+ PINT SCITXINTC; // SCI-C
+ PINT rsvd8_7;
+ PINT rsvd8_8;
+
+ //
+ // Group 9 PIE Peripheral Vectors
+ //
+ PINT SCIRXINTA; // SCI-A
+ PINT SCITXINTA; // SCI-A
+ PINT SCIRXINTB; // SCI-B
+ PINT SCITXINTB; // SCI-B
+ PINT ECAN0INTA; // eCAN-A
+ PINT ECAN1INTA; // eCAN-A
+ PINT ECAN0INTB; // eCAN-B
+ PINT ECAN1INTB; // eCAN-B
+
+ //
+ // Group 10 PIE Peripheral Vectors
+ //
+ PINT rsvd10_1;
+ PINT rsvd10_2;
+ PINT rsvd10_3;
+ PINT rsvd10_4;
+ PINT rsvd10_5;
+ PINT rsvd10_6;
+ PINT rsvd10_7;
+ PINT rsvd10_8;
+
+ //
+ // Group 11 PIE Peripheral Vectors
+ //
+ PINT rsvd11_1;
+ PINT rsvd11_2;
+ PINT rsvd11_3;
+ PINT rsvd11_4;
+ PINT rsvd11_5;
+ PINT rsvd11_6;
+ PINT rsvd11_7;
+ PINT rsvd11_8;
+
+ //
+ // Group 12 PIE Peripheral Vectors
+ //
+ PINT XINT3; // External interrupt
+ PINT XINT4;
+ PINT XINT5;
+ PINT XINT6;
+ PINT XINT7;
+ PINT rsvd12_6;
+ PINT LVF; // Latched overflow
+ PINT LUF; // Latched underflow
+};
+
+//
+// PIE Interrupt Vector Table External References & Function Declarations
+//
+extern volatile struct PIE_VECT_TABLE PieVectTable;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_PIE_VECT_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_SWPrioritizedIsrLevels.h b/bsp/include/DSP2833x_SWPrioritizedIsrLevels.h
new file mode 100644
index 0000000..8c5146d
--- /dev/null
+++ b/bsp/include/DSP2833x_SWPrioritizedIsrLevels.h
@@ -0,0 +1,5999 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 4, 2007 14:25:21 $
+//###########################################################################
+//
+// FILE: DSP2833x_SWPrioritizedIsrLevels.h
+//
+// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine
+// Level definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_SW_PRIORITZIED_ISR_H
+#define DSP2833x_SW_PRIORITZIED_ISR_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// Interrupt Enable Register Allocation For 2833x Devices:
+//
+// Interrupts can be enabled/disabled using the CPU interrupt enable register
+// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12).
+//
+//
+// Set "Global" Interrupt Priority Level (IER register):
+//
+// The user must set the appropriate priority level for each of the CPU
+// interrupts. This is termed as the "global" priority. The priority level
+// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
+// be entered for reserved interrupts or interrupts that are not used. This
+// will also reduce code size by not including ISR's that are not used.
+//
+// Note: The priority levels below are used to calculate the IER register
+// interrupt masks MINT1 to MINT16.
+//
+//
+// Note: The priority levels shown here may not make sense in a
+// real application. This is for demonstration purposes only!!!
+//
+// The user should change these to values that make sense for
+// their application.
+//
+// 0 = not used
+// 1 = highest priority
+// ...
+// 16 = lowest priority
+//
+#define INT1PL 2 // Group1 Interrupts (PIEIER1)
+#define INT2PL 1 // Group2 Interrupts (PIEIER2)
+#define INT3PL 4 // Group3 Interrupts (PIEIER3)
+#define INT4PL 2 // Group4 Interrupts (PIEIER4)
+#define INT5PL 2 // Group5 Interrupts (PIEIER5)
+#define INT6PL 3 // Group6 Interrupts (PIEIER6)
+#define INT7PL 0 // reserved
+#define INT8PL 0 // reserved
+#define INT9PL 3 // Group9 Interrupts (PIEIER9)
+#define INT10PL 0 // reserved
+#define INT11PL 0 // reserved
+#define INT12PL 0 // reserved
+#define INT13PL 4 // XINT13
+#define INT14PL 4 // INT14 (TINT2)
+#define INT15PL 4 // DATALOG
+#define INT16PL 4 // RTOSINT
+
+//
+// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
+//
+// The user must set the appropriate priority level for each of the PIE
+// interrupts. This is termed as the "group" priority. The priority level
+// must be a number between 1 (highest) to 8 (lowest). A value of 0 must
+// be entered for reserved interrupts or interrupts that are not used. This
+// will also reduce code size by not including ISR's that are not used:
+//
+// Note: The priority levels below are used to calculate the following
+// PIEIER register interrupt masks:
+// MG11 to MG18
+// MG21 to MG28
+// MG31 to MG38
+// MG41 to MG48
+// MG51 to MG58
+// MG61 to MG68
+// MG71 to MG78
+// MG81 to MG88
+// MG91 to MG98
+// MG101 to MG108
+// MG111 to MG118
+// MG121 to MG128
+//
+// Note: The priority levels shown here may not make sense in a
+// real application. This is for demonstration purposes only!!!
+//
+// The user should change these to values that make sense for
+// their application.
+//
+// 0 = not used
+// 1 = highest priority
+// ...
+// 8 = lowest priority
+//
+#define G11PL 7 // SEQ1INT (ADC)
+#define G12PL 6 // SEQ2INT (ADC)
+#define G13PL 0 // reserved
+#define G14PL 1 // XINT1 (External)
+#define G15PL 3 // XINT2 (External)
+#define G16PL 2 // ADCINT (ADC)
+#define G17PL 1 // TINT0 (CPU Timer 0)
+#define G18PL 5 // WAKEINT (WD/LPM)
+
+#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip)
+#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip)
+#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip)
+#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip)
+#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip)
+#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip)
+#define G27PL 0 // reserved
+#define G28PL 0 // reserved
+
+#define G31PL 4 // EPWM1_INT (ePWM1 Int)
+#define G32PL 1 // EPWM2_INT (ePWM2 Int)
+#define G33PL 1 // EPWM3_INT (ePWM3 Int)
+#define G34PL 2 // EPWM4_INT (ePWM4 Int)
+#define G35PL 2 // EPWM5_INT (ePWM5 Int)
+#define G36PL 1 // EPWM6_INT (ePWM6 Int)
+#define G37PL 0 // reserved
+#define G38PL 0 // reserved
+
+#define G41PL 2 // ECAP1_INT (eCAP1 Int)
+#define G42PL 1 // ECAP2_INT (eCAP2 Int)
+#define G43PL 3 // ECAP3_INT (eCAP3 Int)
+#define G44PL 3 // ECAP4_INT (eCAP4 Int)
+#define G45PL 5 // ECAP5_INT (eCAP5 Int)
+#define G46PL 5 // ECAP6_INT (eCAP6 Int)
+#define G47PL 0 // reserved
+#define G48PL 0 // reserved
+
+#define G51PL 2 // EQEP1_INT (eQEP1 Int)
+#define G52PL 1 // EQEP2_INT (eQEP2 Int)
+#define G53PL 0 // reserved
+#define G54PL 0 // reserved
+#define G55PL 0 // reserved
+#define G56PL 0 // reserved
+#define G57PL 0 // reserved
+#define G58PL 0 // reserved
+
+#define G61PL 3 // SPIRXINTA (SPI-A)
+#define G62PL 1 // SPITXINTA (SPI-A)
+#define G63PL 4 // MRINTB (McBSP-B)
+#define G64PL 6 // MXINTB (McBSP-B)
+#define G65PL 2 // MRINTA (McBSP-A)
+#define G66PL 1 // MXINTA (McBSP-A)
+#define G67PL 0 // reserved
+#define G68PL 0 // reserved
+
+#define G71PL 5 // DINTCH1 (DMA)
+#define G72PL 4 // DINTCH2 (DMA)
+#define G73PL 4 // DINTCH3 (DMA)
+#define G74PL 2 // DINTCH4 (DMA)
+#define G75PL 3 // DINTCH5 (DMA)
+#define G76PL 1 // DINTCH6 (DMA)
+#define G77PL 0 // reserved
+#define G78PL 0 // reserved
+
+#define G81PL 1 // I2CINT1A (I2C-A)
+#define G82PL 2 // I2CINT2A (I2C-A)
+#define G83PL 0 // reserved
+#define G84PL 0 // reserved
+#define G85PL 4 // SCIRXINTC (SCI-C)
+#define G86PL 3 // SCITXINTC (SCI-C)
+#define G87PL 0 // reserved
+#define G88PL 0 // reserved
+
+#define G91PL 1 // SCIRXINTA (SCI-A)
+#define G92PL 5 // SCITXINTA (SCI-A)
+#define G93PL 3 // SCIRXINTB (SCI-B)
+#define G94PL 4 // SCITXINTB (SCI-B)
+#define G95PL 1 // ECAN0INTA (ECAN-A)
+#define G96PL 1 // ECAN1INTA (ECAN-A)
+#define G97PL 2 // ECAN0INTB (ECAN-B)
+#define G98PL 4 // ECAN1INTB (ECAN-B)
+
+#define G101PL 0 // reserved
+#define G102PL 0 // reserved
+#define G103PL 0 // reserved
+#define G104PL 0 // reserved
+#define G105PL 0 // reserved
+#define G106PL 0 // reserved
+#define G107PL 0 // reserved
+#define G108PL 0 // reserved
+
+#define G111PL 0 // reserved
+#define G112PL 0 // reserved
+#define G113PL 0 // reserved
+#define G114PL 0 // reserved
+#define G115PL 0 // reserved
+#define G116PL 0 // reserved
+#define G117PL 0 // reserved
+#define G118PL 0 // reserved
+
+#define G121PL 5 // XINT3 (External)
+#define G122PL 3 // XINT4 (External)
+#define G123PL 2 // XINT5 (External)
+#define G124PL 2 // XINT6 (External)
+#define G125PL 1 // XINT7 (External)
+#define G126PL 0 // reserved
+#define G127PL 6 // LVF (FPA32)
+#define G128PL 1 // LUF (FPA32)
+
+//
+// There should be no need to modify code below this line
+//
+// Automatically generate IER interrupt masks MINT1 to MINT16:
+//
+
+//
+// Beginning of MINT1:
+//
+#if (INT1PL == 0)
+#define MINT1_1PL ~(1 << 0)
+#else
+#define MINT1_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT1PL) || (INT2PL == 0)
+#define MINT1_2PL ~(1 << 1)
+#else
+#define MINT1_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT1PL) || (INT3PL == 0)
+#define MINT1_3PL ~(1 << 2)
+#else
+#define MINT1_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT1PL) || (INT4PL == 0)
+#define MINT1_4PL ~(1 << 3)
+#else
+#define MINT1_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT1PL) || (INT5PL == 0)
+#define MINT1_5PL ~(1 << 4)
+#else
+#define MINT1_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT1PL) || (INT6PL == 0)
+#define MINT1_6PL ~(1 << 5)
+#else
+#define MINT1_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT1PL) || (INT7PL == 0)
+#define MINT1_7PL ~(1 << 6)
+#else
+#define MINT1_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT1PL) || (INT8PL == 0)
+#define MINT1_8PL ~(1 << 7)
+#else
+#define MINT1_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT1PL) || (INT9PL == 0)
+#define MINT1_9PL ~(1 << 8)
+#else
+#define MINT1_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT1PL) || (INT10PL == 0)
+#define MINT1_10PL ~(1 << 9)
+#else
+#define MINT1_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT1PL) || (INT11PL == 0)
+#define MINT1_11PL ~(1 << 10)
+#else
+#define MINT1_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT1PL) || (INT12PL == 0)
+#define MINT1_12PL ~(1 << 11)
+#else
+#define MINT1_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT1PL) || (INT13PL == 0)
+#define MINT1_13PL ~(1 << 12)
+#else
+#define MINT1_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT1PL) || (INT14PL == 0)
+#define MINT1_14PL ~(1 << 13)
+#else
+#define MINT1_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT1PL) || (INT15PL == 0)
+#define MINT1_15PL ~(1 << 14)
+#else
+#define MINT1_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT1PL) || (INT16PL == 0)
+#define MINT1_16PL ~(1 << 15)
+#else
+#define MINT1_16PL 0xFFFF
+#endif
+
+#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \
+ MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \
+ MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \
+ MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL)
+
+//
+// Beginning of MINT2:
+//
+#if (INT1PL >= INT2PL) || (INT1PL == 0)
+#define MINT2_1PL ~(1 << 0)
+#else
+#define MINT2_1PL 0xFFFF
+#endif
+
+#if (INT2PL == 0)
+#define MINT2_2PL ~(1 << 1)
+#else
+#define MINT2_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT2PL) || (INT3PL == 0)
+#define MINT2_3PL ~(1 << 2)
+#else
+#define MINT2_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT2PL) || (INT4PL == 0)
+#define MINT2_4PL ~(1 << 3)
+#else
+#define MINT2_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT2PL) || (INT5PL == 0)
+#define MINT2_5PL ~(1 << 4)
+#else
+#define MINT2_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT2PL) || (INT6PL == 0)
+#define MINT2_6PL ~(1 << 5)
+#else
+#define MINT2_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT2PL) || (INT7PL == 0)
+#define MINT2_7PL ~(1 << 6)
+#else
+#define MINT2_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT2PL) || (INT8PL == 0)
+#define MINT2_8PL ~(1 << 7)
+#else
+#define MINT2_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT2PL) || (INT9PL == 0)
+#define MINT2_9PL ~(1 << 8)
+#else
+#define MINT2_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT2PL) || (INT10PL == 0)
+#define MINT2_10PL ~(1 << 9)
+#else
+#define MINT2_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT2PL) || (INT11PL == 0)
+#define MINT2_11PL ~(1 << 10)
+#else
+#define MINT2_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT2PL) || (INT12PL == 0)
+#define MINT2_12PL ~(1 << 11)
+#else
+#define MINT2_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT2PL) || (INT13PL == 0)
+#define MINT2_13PL ~(1 << 12)
+#else
+#define MINT2_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT2PL) || (INT14PL == 0)
+#define MINT2_14PL ~(1 << 13)
+#else
+#define MINT2_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT2PL) || (INT15PL == 0)
+#define MINT2_15PL ~(1 << 14)
+#else
+#define MINT2_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT2PL) || (INT16PL == 0)
+#define MINT2_16PL ~(1 << 15)
+#else
+#define MINT2_16PL 0xFFFF
+#endif
+
+#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \
+ MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \
+ MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \
+ MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL)
+
+//
+// Beginning of MINT3:
+//
+#if (INT1PL >= INT3PL) || (INT1PL == 0)
+#define MINT3_1PL ~(1 << 0)
+#else
+#define MINT3_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT3PL) || (INT2PL == 0)
+#define MINT3_2PL ~(1 << 1)
+#else
+#define MINT3_2PL 0xFFFF
+#endif
+
+#if (INT3PL == 0)
+#define MINT3_3PL ~(1 << 2)
+#else
+#define MINT3_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT3PL) || (INT4PL == 0)
+#define MINT3_4PL ~(1 << 3)
+#else
+#define MINT3_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT3PL) || (INT5PL == 0)
+#define MINT3_5PL ~(1 << 4)
+#else
+#define MINT3_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT3PL) || (INT6PL == 0)
+#define MINT3_6PL ~(1 << 5)
+#else
+#define MINT3_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT3PL) || (INT7PL == 0)
+#define MINT3_7PL ~(1 << 6)
+#else
+#define MINT3_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT3PL) || (INT8PL == 0)
+#define MINT3_8PL ~(1 << 7)
+#else
+#define MINT3_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT3PL) || (INT9PL == 0)
+#define MINT3_9PL ~(1 << 8)
+#else
+#define MINT3_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT3PL) || (INT10PL == 0)
+#define MINT3_10PL ~(1 << 9)
+#else
+#define MINT3_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT3PL) || (INT11PL == 0)
+#define MINT3_11PL ~(1 << 10)
+#else
+#define MINT3_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT3PL) || (INT12PL == 0)
+#define MINT3_12PL ~(1 << 11)
+#else
+#define MINT3_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT3PL) || (INT13PL == 0)
+#define MINT3_13PL ~(1 << 12)
+#else
+#define MINT3_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT3PL) || (INT14PL == 0)
+#define MINT3_14PL ~(1 << 13)
+#else
+#define MINT3_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT3PL) || (INT15PL == 0)
+#define MINT3_15PL ~(1 << 14)
+#else
+#define MINT3_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT3PL) || (INT16PL == 0)
+#define MINT3_16PL ~(1 << 15)
+#else
+#define MINT3_16PL 0xFFFF
+#endif
+
+#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \
+ MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \
+ MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \
+ MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL)
+
+//
+// Beginning of MINT4:
+//
+#if (INT1PL >= INT4PL) || (INT1PL == 0)
+#define MINT4_1PL ~(1 << 0)
+#else
+#define MINT4_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT4PL) || (INT2PL == 0)
+#define MINT4_2PL ~(1 << 1)
+#else
+#define MINT4_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT4PL) || (INT3PL == 0)
+#define MINT4_3PL ~(1 << 2)
+#else
+#define MINT4_3PL 0xFFFF
+#endif
+
+#if (INT4PL == 0)
+#define MINT4_4PL ~(1 << 3)
+#else
+#define MINT4_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT4PL) || (INT5PL == 0)
+#define MINT4_5PL ~(1 << 4)
+#else
+#define MINT4_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT4PL) || (INT6PL == 0)
+#define MINT4_6PL ~(1 << 5)
+#else
+#define MINT4_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT4PL) || (INT7PL == 0)
+#define MINT4_7PL ~(1 << 6)
+#else
+#define MINT4_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT4PL) || (INT8PL == 0)
+#define MINT4_8PL ~(1 << 7)
+#else
+#define MINT4_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT4PL) || (INT9PL == 0)
+#define MINT4_9PL ~(1 << 8)
+#else
+#define MINT4_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT4PL) || (INT10PL == 0)
+#define MINT4_10PL ~(1 << 9)
+#else
+#define MINT4_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT4PL) || (INT11PL == 0)
+#define MINT4_11PL ~(1 << 10)
+#else
+#define MINT4_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT4PL) || (INT12PL == 0)
+#define MINT4_12PL ~(1 << 11)
+#else
+#define MINT4_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT4PL) || (INT13PL == 0)
+#define MINT4_13PL ~(1 << 12)
+#else
+#define MINT4_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT4PL) || (INT14PL == 0)
+#define MINT4_14PL ~(1 << 13)
+#else
+#define MINT4_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT4PL) || (INT15PL == 0)
+#define MINT4_15PL ~(1 << 14)
+#else
+#define MINT4_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT4PL) || (INT16PL == 0)
+#define MINT4_16PL ~(1 << 15)
+#else
+#define MINT4_16PL 0xFFFF
+#endif
+
+#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \
+ MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \
+ MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \
+ MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL)
+
+//
+// Beginning of MINT5:
+//
+#if (INT1PL >= INT5PL) || (INT1PL == 0)
+#define MINT5_1PL ~(1 << 0)
+#else
+#define MINT5_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT5PL) || (INT2PL == 0)
+#define MINT5_2PL ~(1 << 1)
+#else
+#define MINT5_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT5PL) || (INT3PL == 0)
+#define MINT5_3PL ~(1 << 2)
+#else
+#define MINT5_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT5PL) || (INT4PL == 0)
+#define MINT5_4PL ~(1 << 3)
+#else
+#define MINT5_4PL 0xFFFF
+#endif
+
+#if (INT5PL == 0)
+#define MINT5_5PL ~(1 << 4)
+#else
+#define MINT5_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT5PL) || (INT6PL == 0)
+#define MINT5_6PL ~(1 << 5)
+#else
+#define MINT5_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT5PL) || (INT7PL == 0)
+#define MINT5_7PL ~(1 << 6)
+#else
+#define MINT5_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT5PL) || (INT8PL == 0)
+#define MINT5_8PL ~(1 << 7)
+#else
+#define MINT5_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT5PL) || (INT9PL == 0)
+#define MINT5_9PL ~(1 << 8)
+#else
+#define MINT5_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT5PL) || (INT10PL == 0)
+#define MINT5_10PL ~(1 << 9)
+#else
+#define MINT5_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT5PL) || (INT11PL == 0)
+#define MINT5_11PL ~(1 << 10)
+#else
+#define MINT5_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT5PL) || (INT12PL == 0)
+#define MINT5_12PL ~(1 << 11)
+#else
+#define MINT5_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT5PL) || (INT13PL == 0)
+#define MINT5_13PL ~(1 << 12)
+#else
+#define MINT5_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT5PL) || (INT14PL == 0)
+#define MINT5_14PL ~(1 << 13)
+#else
+#define MINT5_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT5PL) || (INT15PL == 0)
+#define MINT5_15PL ~(1 << 14)
+#else
+#define MINT5_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT5PL) || (INT16PL == 0)
+#define MINT5_16PL ~(1 << 15)
+#else
+#define MINT5_16PL 0xFFFF
+#endif
+
+#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \
+ MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \
+ MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \
+ MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL)
+
+//
+// Beginning of MINT6:
+//
+#if (INT1PL >= INT6PL) || (INT1PL == 0)
+#define MINT6_1PL ~(1 << 0)
+#else
+#define MINT6_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT6PL) || (INT2PL == 0)
+#define MINT6_2PL ~(1 << 1)
+#else
+#define MINT6_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT6PL) || (INT3PL == 0)
+#define MINT6_3PL ~(1 << 2)
+#else
+#define MINT6_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT6PL) || (INT4PL == 0)
+#define MINT6_4PL ~(1 << 3)
+#else
+#define MINT6_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT6PL) || (INT5PL == 0)
+#define MINT6_5PL ~(1 << 4)
+#else
+#define MINT6_5PL 0xFFFF
+#endif
+
+#if (INT6PL == 0)
+#define MINT6_6PL ~(1 << 5)
+#else
+#define MINT6_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT6PL) || (INT7PL == 0)
+#define MINT6_7PL ~(1 << 6)
+#else
+#define MINT6_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT6PL) || (INT8PL == 0)
+#define MINT6_8PL ~(1 << 7)
+#else
+#define MINT6_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT6PL) || (INT9PL == 0)
+#define MINT6_9PL ~(1 << 8)
+#else
+#define MINT6_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT6PL) || (INT10PL == 0)
+#define MINT6_10PL ~(1 << 9)
+#else
+#define MINT6_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT6PL) || (INT11PL == 0)
+#define MINT6_11PL ~(1 << 10)
+#else
+#define MINT6_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT6PL) || (INT12PL == 0)
+#define MINT6_12PL ~(1 << 11)
+#else
+#define MINT6_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT6PL) || (INT13PL == 0)
+#define MINT6_13PL ~(1 << 12)
+#else
+#define MINT6_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT6PL) || (INT14PL == 0)
+#define MINT6_14PL ~(1 << 13)
+#else
+#define MINT6_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT6PL) || (INT15PL == 0)
+#define MINT6_15PL ~(1 << 14)
+#else
+#define MINT6_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT6PL) || (INT16PL == 0)
+#define MINT6_16PL ~(1 << 15)
+#else
+#define MINT6_16PL 0xFFFF
+#endif
+
+#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \
+ MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \
+ MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \
+ MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL)
+
+//
+// Beginning of MINT7:
+//
+#if (INT1PL >= INT7PL) || (INT1PL == 0)
+#define MINT7_1PL ~(1 << 0)
+#else
+#define MINT7_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT7PL) || (INT2PL == 0)
+#define MINT7_2PL ~(1 << 1)
+#else
+#define MINT7_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT7PL) || (INT3PL == 0)
+#define MINT7_3PL ~(1 << 2)
+#else
+#define MINT7_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT7PL) || (INT4PL == 0)
+#define MINT7_4PL ~(1 << 3)
+#else
+#define MINT7_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT7PL) || (INT5PL == 0)
+#define MINT7_5PL ~(1 << 4)
+#else
+#define MINT7_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT7PL) || (INT6PL == 0)
+#define MINT7_6PL ~(1 << 5)
+#else
+#define MINT7_6PL 0xFFFF
+#endif
+
+#if (INT7PL == 0)
+#define MINT7_7PL ~(1 << 6)
+#else
+#define MINT7_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT7PL) || (INT8PL == 0)
+#define MINT7_8PL ~(1 << 7)
+#else
+#define MINT7_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT7PL) || (INT9PL == 0)
+#define MINT7_9PL ~(1 << 8)
+#else
+#define MINT7_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT7PL) || (INT10PL == 0)
+#define MINT7_10PL ~(1 << 9)
+#else
+#define MINT7_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT7PL) || (INT11PL == 0)
+#define MINT7_11PL ~(1 << 10)
+#else
+#define MINT7_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT7PL) || (INT12PL == 0)
+#define MINT7_12PL ~(1 << 11)
+#else
+#define MINT7_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT7PL) || (INT13PL == 0)
+#define MINT7_13PL ~(1 << 12)
+#else
+#define MINT7_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT7PL) || (INT14PL == 0)
+#define MINT7_14PL ~(1 << 13)
+#else
+#define MINT7_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT7PL) || (INT15PL == 0)
+#define MINT7_15PL ~(1 << 14)
+#else
+#define MINT7_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT7PL) || (INT16PL == 0)
+#define MINT7_16PL ~(1 << 15)
+#else
+#define MINT7_16PL 0xFFFF
+#endif
+
+#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \
+ MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \
+ MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \
+ MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL)
+
+//
+// Beginning of MINT8:
+//
+#if (INT1PL >= INT8PL) || (INT1PL == 0)
+#define MINT8_1PL ~(1 << 0)
+#else
+#define MINT8_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT8PL) || (INT2PL == 0)
+#define MINT8_2PL ~(1 << 1)
+#else
+#define MINT8_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT8PL) || (INT3PL == 0)
+#define MINT8_3PL ~(1 << 2)
+#else
+#define MINT8_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT8PL) || (INT4PL == 0)
+#define MINT8_4PL ~(1 << 3)
+#else
+#define MINT8_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT8PL) || (INT5PL == 0)
+#define MINT8_5PL ~(1 << 4)
+#else
+#define MINT8_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT8PL) || (INT6PL == 0)
+#define MINT8_6PL ~(1 << 5)
+#else
+#define MINT8_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT8PL) || (INT7PL == 0)
+#define MINT8_7PL ~(1 << 6)
+#else
+#define MINT8_7PL 0xFFFF
+#endif
+
+#if (INT8PL == 0)
+#define MINT8_8PL ~(1 << 7)
+#else
+#define MINT8_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT8PL) || (INT9PL == 0)
+#define MINT8_9PL ~(1 << 8)
+#else
+#define MINT8_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT8PL) || (INT10PL == 0)
+#define MINT8_10PL ~(1 << 9)
+#else
+#define MINT8_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT8PL) || (INT11PL == 0)
+#define MINT8_11PL ~(1 << 10)
+#else
+#define MINT8_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT8PL) || (INT12PL == 0)
+#define MINT8_12PL ~(1 << 11)
+#else
+#define MINT8_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT8PL) || (INT13PL == 0)
+#define MINT8_13PL ~(1 << 12)
+#else
+#define MINT8_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT8PL) || (INT14PL == 0)
+#define MINT8_14PL ~(1 << 13)
+#else
+#define MINT8_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT8PL) || (INT15PL == 0)
+#define MINT8_15PL ~(1 << 14)
+#else
+#define MINT8_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT8PL) || (INT16PL == 0)
+#define MINT8_16PL ~(1 << 15)
+#else
+#define MINT8_16PL 0xFFFF
+#endif
+
+#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \
+ MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \
+ MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \
+ MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL)
+
+//
+// Beginning of MINT9:
+//
+#if (INT1PL >= INT9PL) || (INT1PL == 0)
+#define MINT9_1PL ~(1 << 0)
+#else
+#define MINT9_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT9PL) || (INT2PL == 0)
+#define MINT9_2PL ~(1 << 1)
+#else
+#define MINT9_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT9PL) || (INT3PL == 0)
+#define MINT9_3PL ~(1 << 2)
+#else
+#define MINT9_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT9PL) || (INT4PL == 0)
+#define MINT9_4PL ~(1 << 3)
+#else
+#define MINT9_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT9PL) || (INT5PL == 0)
+#define MINT9_5PL ~(1 << 4)
+#else
+#define MINT9_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT9PL) || (INT6PL == 0)
+#define MINT9_6PL ~(1 << 5)
+#else
+#define MINT9_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT9PL) || (INT7PL == 0)
+#define MINT9_7PL ~(1 << 6)
+#else
+#define MINT9_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT9PL) || (INT8PL == 0)
+#define MINT9_8PL ~(1 << 7)
+#else
+#define MINT9_8PL 0xFFFF
+#endif
+
+#if (INT9PL == 0)
+#define MINT9_9PL ~(1 << 8)
+#else
+#define MINT9_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT9PL) || (INT10PL == 0)
+#define MINT9_10PL ~(1 << 9)
+#else
+#define MINT9_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT9PL) || (INT11PL == 0)
+#define MINT9_11PL ~(1 << 10)
+#else
+#define MINT9_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT9PL) || (INT12PL == 0)
+#define MINT9_12PL ~(1 << 11)
+#else
+#define MINT9_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT9PL) || (INT13PL == 0)
+#define MINT9_13PL ~(1 << 12)
+#else
+#define MINT9_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT9PL) || (INT14PL == 0)
+#define MINT9_14PL ~(1 << 13)
+#else
+#define MINT9_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT9PL) || (INT15PL == 0)
+#define MINT9_15PL ~(1 << 14)
+#else
+#define MINT9_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT9PL) || (INT16PL == 0)
+#define MINT9_16PL ~(1 << 15)
+#else
+#define MINT9_16PL 0xFFFF
+#endif
+
+#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \
+ MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \
+ MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \
+ MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL)
+
+//
+// Beginning of MINT10:
+//
+#if (INT1PL >= INT10PL) || (INT1PL == 0)
+#define MINT10_1PL ~(1 << 0)
+#else
+#define MINT10_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT10PL) || (INT2PL == 0)
+#define MINT10_2PL ~(1 << 1)
+#else
+#define MINT10_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT10PL) || (INT3PL == 0)
+#define MINT10_3PL ~(1 << 2)
+#else
+#define MINT10_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT10PL) || (INT4PL == 0)
+#define MINT10_4PL ~(1 << 3)
+#else
+#define MINT10_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT10PL) || (INT5PL == 0)
+#define MINT10_5PL ~(1 << 4)
+#else
+#define MINT10_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT10PL) || (INT6PL == 0)
+#define MINT10_6PL ~(1 << 5)
+#else
+#define MINT10_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT10PL) || (INT7PL == 0)
+#define MINT10_7PL ~(1 << 6)
+#else
+#define MINT10_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT10PL) || (INT8PL == 0)
+#define MINT10_8PL ~(1 << 7)
+#else
+#define MINT10_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT10PL) || (INT9PL == 0)
+#define MINT10_9PL ~(1 << 8)
+#else
+#define MINT10_9PL 0xFFFF
+#endif
+
+#if (INT10PL == 0)
+#define MINT10_10PL ~(1 << 9)
+#else
+#define MINT10_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT10PL) || (INT11PL == 0)
+#define MINT10_11PL ~(1 << 10)
+#else
+#define MINT10_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT10PL) || (INT12PL == 0)
+#define MINT10_12PL ~(1 << 11)
+#else
+#define MINT10_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT10PL) || (INT13PL == 0)
+#define MINT10_13PL ~(1 << 12)
+#else
+#define MINT10_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT10PL) || (INT14PL == 0)
+#define MINT10_14PL ~(1 << 13)
+#else
+#define MINT10_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT10PL) || (INT15PL == 0)
+#define MINT10_15PL ~(1 << 14)
+#else
+#define MINT10_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT10PL) || (INT16PL == 0)
+#define MINT10_16PL ~(1 << 15)
+#else
+#define MINT10_16PL 0xFFFF
+#endif
+
+#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \
+ MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \
+ MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \
+ MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL)
+
+//
+// Beginning of MINT11:
+//
+#if (INT1PL >= INT11PL) || (INT1PL == 0)
+#define MINT11_1PL ~(1 << 0)
+#else
+#define MINT11_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT11PL) || (INT2PL == 0)
+#define MINT11_2PL ~(1 << 1)
+#else
+#define MINT11_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT11PL) || (INT3PL == 0)
+#define MINT11_3PL ~(1 << 2)
+#else
+#define MINT11_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT11PL) || (INT4PL == 0)
+#define MINT11_4PL ~(1 << 3)
+#else
+#define MINT11_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT11PL) || (INT5PL == 0)
+#define MINT11_5PL ~(1 << 4)
+#else
+#define MINT11_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT11PL) || (INT6PL == 0)
+#define MINT11_6PL ~(1 << 5)
+#else
+#define MINT11_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT11PL) || (INT7PL == 0)
+#define MINT11_7PL ~(1 << 6)
+#else
+#define MINT11_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT11PL) || (INT8PL == 0)
+#define MINT11_8PL ~(1 << 7)
+#else
+#define MINT11_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT11PL) || (INT9PL == 0)
+#define MINT11_9PL ~(1 << 8)
+#else
+#define MINT11_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT11PL) || (INT10PL == 0)
+#define MINT11_10PL ~(1 << 9)
+#else
+#define MINT11_10PL 0xFFFF
+#endif
+
+#if (INT11PL == 0)
+#define MINT11_11PL ~(1 << 10)
+#else
+#define MINT11_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT11PL) || (INT12PL == 0)
+#define MINT11_12PL ~(1 << 11)
+#else
+#define MINT11_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT11PL) || (INT13PL == 0)
+#define MINT11_13PL ~(1 << 12)
+#else
+#define MINT11_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT11PL) || (INT14PL == 0)
+#define MINT11_14PL ~(1 << 13)
+#else
+#define MINT11_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT11PL) || (INT15PL == 0)
+#define MINT11_15PL ~(1 << 14)
+#else
+#define MINT11_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT11PL) || (INT16PL == 0)
+#define MINT11_16PL ~(1 << 15)
+#else
+#define MINT11_16PL 0xFFFF
+#endif
+
+#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \
+ MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \
+ MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \
+ MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL)
+
+//
+// Beginning of MINT12:
+//
+#if (INT1PL >= INT12PL) || (INT1PL == 0)
+#define MINT12_1PL ~(1 << 0)
+#else
+#define MINT12_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT12PL) || (INT2PL == 0)
+#define MINT12_2PL ~(1 << 1)
+#else
+#define MINT12_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT12PL) || (INT3PL == 0)
+#define MINT12_3PL ~(1 << 2)
+#else
+#define MINT12_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT12PL) || (INT4PL == 0)
+#define MINT12_4PL ~(1 << 3)
+#else
+#define MINT12_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT12PL) || (INT5PL == 0)
+#define MINT12_5PL ~(1 << 4)
+#else
+#define MINT12_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT12PL) || (INT6PL == 0)
+#define MINT12_6PL ~(1 << 5)
+#else
+#define MINT12_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT12PL) || (INT7PL == 0)
+#define MINT12_7PL ~(1 << 6)
+#else
+#define MINT12_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT12PL) || (INT8PL == 0)
+#define MINT12_8PL ~(1 << 7)
+#else
+#define MINT12_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT12PL) || (INT9PL == 0)
+#define MINT12_9PL ~(1 << 8)
+#else
+#define MINT12_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT12PL) || (INT10PL == 0)
+#define MINT12_10PL ~(1 << 9)
+#else
+#define MINT12_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT12PL) || (INT11PL == 0)
+#define MINT12_11PL ~(1 << 10)
+#else
+#define MINT12_11PL 0xFFFF
+#endif
+
+#if (INT12PL == 0)
+#define MINT12_12PL ~(1 << 11)
+#else
+#define MINT12_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT12PL) || (INT13PL == 0)
+#define MINT12_13PL ~(1 << 12)
+#else
+#define MINT12_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT12PL) || (INT14PL == 0)
+#define MINT12_14PL ~(1 << 13)
+#else
+#define MINT12_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT12PL) || (INT15PL == 0)
+#define MINT12_15PL ~(1 << 14)
+#else
+#define MINT12_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT12PL) || (INT16PL == 0)
+#define MINT12_16PL ~(1 << 15)
+#else
+#define MINT12_16PL 0xFFFF
+#endif
+
+#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \
+ MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \
+ MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \
+ MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL)
+
+//
+// Beginning of MINT13:
+//
+#if (INT1PL >= INT13PL) || (INT1PL == 0)
+#define MINT13_1PL ~(1 << 0)
+#else
+#define MINT13_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT13PL) || (INT2PL == 0)
+#define MINT13_2PL ~(1 << 1)
+#else
+#define MINT13_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT13PL) || (INT3PL == 0)
+#define MINT13_3PL ~(1 << 2)
+#else
+#define MINT13_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT13PL) || (INT4PL == 0)
+#define MINT13_4PL ~(1 << 3)
+#else
+#define MINT13_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT13PL) || (INT5PL == 0)
+#define MINT13_5PL ~(1 << 4)
+#else
+#define MINT13_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT13PL) || (INT6PL == 0)
+#define MINT13_6PL ~(1 << 5)
+#else
+#define MINT13_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT13PL) || (INT7PL == 0)
+#define MINT13_7PL ~(1 << 6)
+#else
+#define MINT13_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT13PL) || (INT8PL == 0)
+#define MINT13_8PL ~(1 << 7)
+#else
+#define MINT13_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT13PL) || (INT9PL == 0)
+#define MINT13_9PL ~(1 << 8)
+#else
+#define MINT13_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT13PL) || (INT10PL == 0)
+#define MINT13_10PL ~(1 << 9)
+#else
+#define MINT13_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT13PL) || (INT11PL == 0)
+#define MINT13_11PL ~(1 << 10)
+#else
+#define MINT13_11PL 0xFFFF
+#endif
+
+#define MINT13_12PL ~(1 << 11)
+
+#if (INT13PL == 0)
+#define MINT13_13PL ~(1 << 12)
+#else
+#define MINT13_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT13PL) || (INT14PL == 0)
+#define MINT13_14PL ~(1 << 13)
+#else
+#define MINT13_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT13PL) || (INT15PL == 0)
+#define MINT13_15PL ~(1 << 14)
+#else
+#define MINT13_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT13PL) || (INT16PL == 0)
+#define MINT13_16PL ~(1 << 15)
+#else
+#define MINT13_16PL 0xFFFF
+#endif
+
+#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \
+ MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \
+ MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \
+ MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL)
+
+//
+// Beginning of MINT14:
+//
+#if (INT1PL >= INT14PL) || (INT1PL == 0)
+#define MINT14_1PL ~(1 << 0)
+#else
+#define MINT14_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT14PL) || (INT2PL == 0)
+#define MINT14_2PL ~(1 << 1)
+#else
+#define MINT14_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT14PL) || (INT3PL == 0)
+#define MINT14_3PL ~(1 << 2)
+#else
+#define MINT14_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT14PL) || (INT4PL == 0)
+#define MINT14_4PL ~(1 << 3)
+#else
+#define MINT14_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT14PL) || (INT5PL == 0)
+#define MINT14_5PL ~(1 << 4)
+#else
+#define MINT14_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT14PL) || (INT6PL == 0)
+#define MINT14_6PL ~(1 << 5)
+#else
+#define MINT14_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT14PL) || (INT7PL == 0)
+#define MINT14_7PL ~(1 << 6)
+#else
+#define MINT14_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT14PL) || (INT8PL == 0)
+#define MINT14_8PL ~(1 << 7)
+#else
+#define MINT14_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT14PL) || (INT9PL == 0)
+#define MINT14_9PL ~(1 << 8)
+#else
+#define MINT14_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT14PL) || (INT10PL == 0)
+#define MINT14_10PL ~(1 << 9)
+#else
+#define MINT14_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT14PL) || (INT11PL == 0)
+#define MINT14_11PL ~(1 << 10)
+#else
+#define MINT14_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT14PL) || (INT12PL == 0)
+#define MINT14_12PL ~(1 << 11)
+#else
+#define MINT14_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT14PL) || (INT13PL == 0)
+#define MINT14_13PL ~(1 << 12)
+#else
+#define MINT14_13PL 0xFFFF
+#endif
+
+#define MINT14_14PL ~(1 << 13)
+
+#if (INT15PL >= INT14PL) || (INT15PL == 0)
+#define MINT14_15PL ~(1 << 14)
+#else
+#define MINT14_15PL 0xFFFF
+#endif
+
+#if (INT16PL >= INT14PL) || (INT16PL == 0)
+#define MINT14_16PL ~(1 << 15)
+#else
+#define MINT14_16PL 0xFFFF
+#endif
+
+#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \
+ MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \
+ MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \
+ MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL)
+
+//
+// Beginning of MINT15:
+//
+#if (INT1PL >= INT15PL) || (INT1PL == 0)
+#define MINT15_1PL ~(1 << 0)
+#else
+#define MINT15_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT15PL) || (INT2PL == 0)
+#define MINT15_2PL ~(1 << 1)
+#else
+#define MINT15_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT15PL) || (INT3PL == 0)
+#define MINT15_3PL ~(1 << 2)
+#else
+#define MINT15_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT15PL) || (INT4PL == 0)
+#define MINT15_4PL ~(1 << 3)
+#else
+#define MINT15_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT15PL) || (INT5PL == 0)
+#define MINT15_5PL ~(1 << 4)
+#else
+#define MINT15_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT15PL) || (INT6PL == 0)
+#define MINT15_6PL ~(1 << 5)
+#else
+#define MINT15_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT15PL) || (INT7PL == 0)
+#define MINT15_7PL ~(1 << 6)
+#else
+#define MINT15_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT15PL) || (INT8PL == 0)
+#define MINT15_8PL ~(1 << 7)
+#else
+#define MINT15_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT15PL) || (INT9PL == 0)
+#define MINT15_9PL ~(1 << 8)
+#else
+#define MINT15_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT15PL) || (INT10PL == 0)
+#define MINT15_10PL ~(1 << 9)
+#else
+#define MINT15_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT15PL) || (INT11PL == 0)
+#define MINT15_11PL ~(1 << 10)
+#else
+#define MINT15_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT15PL) || (INT12PL == 0)
+#define MINT15_12PL ~(1 << 11)
+#else
+#define MINT15_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT15PL) || (INT13PL == 0)
+#define MINT15_13PL ~(1 << 12)
+#else
+#define MINT15_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT15PL) || (INT14PL == 0)
+#define MINT15_14PL ~(1 << 13)
+#else
+#define MINT15_14PL 0xFFFF
+#endif
+
+#define MINT15_15PL ~(1 << 14)
+
+#if (INT16PL >= INT15PL) || (INT16PL == 0)
+#define MINT15_16PL ~(1 << 15)
+#else
+#define MINT15_16PL 0xFFFF
+#endif
+
+#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \
+ MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \
+ MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \
+ MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL)
+
+//
+// Beginning of MINT16:
+//
+#if (INT1PL >= INT16PL) || (INT1PL == 0)
+#define MINT16_1PL ~(1 << 0)
+#else
+#define MINT16_1PL 0xFFFF
+#endif
+
+#if (INT2PL >= INT16PL) || (INT2PL == 0)
+#define MINT16_2PL ~(1 << 1)
+#else
+#define MINT16_2PL 0xFFFF
+#endif
+
+#if (INT3PL >= INT16PL) || (INT3PL == 0)
+#define MINT16_3PL ~(1 << 2)
+#else
+#define MINT16_3PL 0xFFFF
+#endif
+
+#if (INT4PL >= INT16PL) || (INT4PL == 0)
+#define MINT16_4PL ~(1 << 3)
+#else
+#define MINT16_4PL 0xFFFF
+#endif
+
+#if (INT5PL >= INT16PL) || (INT5PL == 0)
+#define MINT16_5PL ~(1 << 4)
+#else
+#define MINT16_5PL 0xFFFF
+#endif
+
+#if (INT6PL >= INT16PL) || (INT6PL == 0)
+#define MINT16_6PL ~(1 << 5)
+#else
+#define MINT16_6PL 0xFFFF
+#endif
+
+#if (INT7PL >= INT16PL) || (INT7PL == 0)
+#define MINT16_7PL ~(1 << 6)
+#else
+#define MINT16_7PL 0xFFFF
+#endif
+
+#if (INT8PL >= INT16PL) || (INT8PL == 0)
+#define MINT16_8PL ~(1 << 7)
+#else
+#define MINT16_8PL 0xFFFF
+#endif
+
+#if (INT9PL >= INT16PL) || (INT9PL == 0)
+#define MINT16_9PL ~(1 << 8)
+#else
+#define MINT16_9PL 0xFFFF
+#endif
+
+#if (INT10PL >= INT16PL) || (INT10PL == 0)
+#define MINT16_10PL ~(1 << 9)
+#else
+#define MINT16_10PL 0xFFFF
+#endif
+
+#if (INT11PL >= INT16PL) || (INT11PL == 0)
+#define MINT16_11PL ~(1 << 10)
+#else
+#define MINT16_11PL 0xFFFF
+#endif
+
+#if (INT12PL >= INT16PL) || (INT12PL == 0)
+#define MINT16_12PL ~(1 << 11)
+#else
+#define MINT16_12PL 0xFFFF
+#endif
+
+#if (INT13PL >= INT16PL) || (INT13PL == 0)
+#define MINT16_13PL ~(1 << 12)
+#else
+#define MINT16_13PL 0xFFFF
+#endif
+
+#if (INT14PL >= INT16PL) || (INT14PL == 0)
+#define MINT16_14PL ~(1 << 13)
+#else
+#define MINT16_14PL 0xFFFF
+#endif
+
+#if (INT15PL >= INT16PL) || (INT15PL == 0)
+#define MINT16_15PL ~(1 << 14)
+#else
+#define MINT16_15PL 0xFFFF
+#endif
+
+#define MINT16_16PL ~(1 << 15)
+
+#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \
+ MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \
+ MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \
+ MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG11 to MG18:
+//
+
+//
+// Beginning of MG11:
+//
+#if (G12PL >= G11PL) || (G12PL == 0)
+#define MG11_12PL ~(1 << 1)
+#else
+#define MG11_12PL 0xFFFF
+#endif
+
+#if (G13PL >= G11PL) || (G13PL == 0)
+#define MG11_13PL ~(1 << 2)
+#else
+#define MG11_13PL 0xFFFF
+#endif
+
+#if (G14PL >= G11PL) || (G14PL == 0)
+#define MG11_14PL ~(1 << 3)
+#else
+#define MG11_14PL 0xFFFF
+#endif
+
+#if (G15PL >= G11PL) || (G15PL == 0)
+#define MG11_15PL ~(1 << 4)
+#else
+#define MG11_15PL 0xFFFF
+#endif
+
+#if (G16PL >= G11PL) || (G16PL == 0)
+#define MG11_16PL ~(1 << 5)
+#else
+#define MG11_16PL 0xFFFF
+#endif
+
+#if (G17PL >= G11PL) || (G17PL == 0)
+#define MG11_17PL ~(1 << 6)
+#else
+#define MG11_17PL 0xFFFF
+#endif
+
+#if (G18PL >= G11PL) || (G18PL == 0)
+#define MG11_18PL ~(1 << 7)
+#else
+#define MG11_18PL 0xFFFF
+#endif
+
+#define MG11_11PL 0x00FE
+#define MG11 (MG11_11PL & MG11_12PL & MG11_13PL & MG11_14PL & \
+ MG11_15PL & MG11_16PL & MG11_17PL & MG11_18PL)
+
+//
+// Beginning of MG12:
+//
+#if (G11PL >= G12PL) || (G11PL == 0)
+#define MG12_11PL ~(1)
+#else
+#define MG12_11PL 0xFFFF
+#endif
+#if (G13PL >= G12PL) || (G13PL == 0)
+#define MG12_13PL ~(1 << 2)
+#else
+#define MG12_13PL 0xFFFF
+#endif
+#if (G14PL >= G12PL) || (G14PL == 0)
+#define MG12_14PL ~(1 << 3)
+#else
+#define MG12_14PL 0xFFFF
+#endif
+#if (G15PL >= G12PL) || (G15PL == 0)
+#define MG12_15PL ~(1 << 4)
+#else
+#define MG12_15PL 0xFFFF
+#endif
+#if (G16PL >= G12PL) || (G16PL == 0)
+#define MG12_16PL ~(1 << 5)
+#else
+#define MG12_16PL 0xFFFF
+#endif
+#if (G17PL >= G12PL) || (G17PL == 0)
+#define MG12_17PL ~(1 << 6)
+#else
+#define MG12_17PL 0xFFFF
+#endif
+#if (G18PL >= G12PL) || (G18PL == 0)
+#define MG12_18PL ~(1 << 7)
+#else
+#define MG12_18PL 0xFFFF
+#endif
+#define MG12_12PL 0x00FD
+#define MG12 (MG12_11PL & MG12_12PL & MG12_13PL & MG12_14PL & \
+ MG12_15PL & MG12_16PL & MG12_17PL & MG12_18PL)
+
+//
+// End of MG12:
+//
+
+//
+// Beginning of MG13:
+//
+#if (G11PL >= G13PL) || (G11PL == 0)
+#define MG13_11PL ~(1)
+#else
+#define MG13_11PL 0xFFFF
+#endif
+#if (G12PL >= G13PL) || (G12PL == 0)
+#define MG13_12PL ~(1 << 1)
+#else
+#define MG13_12PL 0xFFFF
+#endif
+#if (G14PL >= G13PL) || (G14PL == 0)
+#define MG13_14PL ~(1 << 3)
+#else
+#define MG13_14PL 0xFFFF
+#endif
+#if (G15PL >= G13PL) || (G15PL == 0)
+#define MG13_15PL ~(1 << 4)
+#else
+#define MG13_15PL 0xFFFF
+#endif
+#if (G16PL >= G13PL) || (G16PL == 0)
+#define MG13_16PL ~(1 << 5)
+#else
+#define MG13_16PL 0xFFFF
+#endif
+#if (G17PL >= G13PL) || (G17PL == 0)
+#define MG13_17PL ~(1 << 6)
+#else
+#define MG13_17PL 0xFFFF
+#endif
+#if (G18PL >= G13PL) || (G18PL == 0)
+#define MG13_18PL ~(1 << 7)
+#else
+#define MG13_18PL 0xFFFF
+#endif
+#define MG13_13PL 0x00FB
+#define MG13 (MG13_11PL & MG13_12PL & MG13_13PL & MG13_14PL & \
+ MG13_15PL & MG13_16PL & MG13_17PL & MG13_18PL)
+
+//
+// Beginning of MG14:
+//
+#if (G11PL >= G14PL) || (G11PL == 0)
+#define MG14_11PL ~(1)
+#else
+#define MG14_11PL 0xFFFF
+#endif
+#if (G12PL >= G14PL) || (G12PL == 0)
+#define MG14_12PL ~(1 << 1)
+#else
+#define MG14_12PL 0xFFFF
+#endif
+#if (G13PL >= G14PL) || (G13PL == 0)
+#define MG14_13PL ~(1 << 2)
+#else
+#define MG14_13PL 0xFFFF
+#endif
+#if (G15PL >= G14PL) || (G15PL == 0)
+#define MG14_15PL ~(1 << 4)
+#else
+#define MG14_15PL 0xFFFF
+#endif
+#if (G16PL >= G14PL) || (G16PL == 0)
+#define MG14_16PL ~(1 << 5)
+#else
+#define MG14_16PL 0xFFFF
+#endif
+#if (G17PL >= G14PL) || (G17PL == 0)
+#define MG14_17PL ~(1 << 6)
+#else
+#define MG14_17PL 0xFFFF
+#endif
+#if (G18PL >= G14PL) || (G18PL == 0)
+#define MG14_18PL ~(1 << 7)
+#else
+#define MG14_18PL 0xFFFF
+#endif
+#define MG14_14PL 0x00F7
+#define MG14 (MG14_11PL & MG14_12PL & MG14_13PL & MG14_14PL & \
+ MG14_15PL & MG14_16PL & MG14_17PL & MG14_18PL)
+
+//
+// Beginning of MG15:
+//
+#if (G11PL >= G15PL) || (G11PL == 0)
+#define MG15_11PL ~(1)
+#else
+#define MG15_11PL 0xFFFF
+#endif
+#if (G12PL >= G15PL) || (G12PL == 0)
+#define MG15_12PL ~(1 << 1)
+#else
+#define MG15_12PL 0xFFFF
+#endif
+#if (G13PL >= G15PL) || (G13PL == 0)
+#define MG15_13PL ~(1 << 2)
+#else
+#define MG15_13PL 0xFFFF
+#endif
+#if (G14PL >= G15PL) || (G14PL == 0)
+#define MG15_14PL ~(1 << 3)
+#else
+#define MG15_14PL 0xFFFF
+#endif
+#if (G16PL >= G15PL) || (G16PL == 0)
+#define MG15_16PL ~(1 << 5)
+#else
+#define MG15_16PL 0xFFFF
+#endif
+#if (G17PL >= G15PL) || (G17PL == 0)
+#define MG15_17PL ~(1 << 6)
+#else
+#define MG15_17PL 0xFFFF
+#endif
+#if (G18PL >= G15PL) || (G18PL == 0)
+#define MG15_18PL ~(1 << 7)
+#else
+#define MG15_18PL 0xFFFF
+#endif
+#define MG15_15PL 0x00EF
+#define MG15 (MG15_11PL & MG15_12PL & MG15_13PL & MG15_14PL & \
+ MG15_15PL & MG15_16PL & MG15_17PL & MG15_18PL)
+
+//
+// Beginning of MG16:
+//
+#if (G11PL >= G16PL) || (G11PL == 0)
+#define MG16_11PL ~(1)
+#else
+#define MG16_11PL 0xFFFF
+#endif
+#if (G12PL >= G16PL) || (G12PL == 0)
+#define MG16_12PL ~(1 << 1)
+#else
+#define MG16_12PL 0xFFFF
+#endif
+#if (G13PL >= G16PL) || (G13PL == 0)
+#define MG16_13PL ~(1 << 2)
+#else
+#define MG16_13PL 0xFFFF
+#endif
+#if (G14PL >= G16PL) || (G14PL == 0)
+#define MG16_14PL ~(1 << 3)
+#else
+#define MG16_14PL 0xFFFF
+#endif
+#if (G15PL >= G16PL) || (G15PL == 0)
+#define MG16_15PL ~(1 << 4)
+#else
+#define MG16_15PL 0xFFFF
+#endif
+#if (G17PL >= G16PL) || (G17PL == 0)
+#define MG16_17PL ~(1 << 6)
+#else
+#define MG16_17PL 0xFFFF
+#endif
+#if (G18PL >= G16PL) || (G18PL == 0)
+#define MG16_18PL ~(1 << 7)
+#else
+#define MG16_18PL 0xFFFF
+#endif
+#define MG16_16PL 0x00DF
+#define MG16 (MG16_11PL & MG16_12PL & MG16_13PL & MG16_14PL & \
+ MG16_15PL & MG16_16PL & MG16_17PL & MG16_18PL)
+
+//
+// Beginning of MG17:
+//
+#if (G11PL >= G17PL) || (G11PL == 0)
+#define MG17_11PL ~(1)
+#else
+#define MG17_11PL 0xFFFF
+#endif
+#if (G12PL >= G17PL) || (G12PL == 0)
+#define MG17_12PL ~(1 << 1)
+#else
+#define MG17_12PL 0xFFFF
+#endif
+#if (G13PL >= G17PL) || (G13PL == 0)
+#define MG17_13PL ~(1 << 2)
+#else
+#define MG17_13PL 0xFFFF
+#endif
+#if (G14PL >= G17PL) || (G14PL == 0)
+#define MG17_14PL ~(1 << 3)
+#else
+#define MG17_14PL 0xFFFF
+#endif
+#if (G15PL >= G17PL) || (G15PL == 0)
+#define MG17_15PL ~(1 << 4)
+#else
+#define MG17_15PL 0xFFFF
+#endif
+#if (G16PL >= G17PL) || (G16PL == 0)
+#define MG17_16PL ~(1 << 5)
+#else
+#define MG17_16PL 0xFFFF
+#endif
+#if (G18PL >= G17PL) || (G18PL == 0)
+#define MG17_18PL ~(1 << 7)
+#else
+#define MG17_18PL 0xFFFF
+#endif
+#define MG17_17PL 0x00BF
+#define MG17 (MG17_11PL & MG17_12PL & MG17_13PL & MG17_14PL & \
+ MG17_15PL & MG17_16PL & MG17_17PL & MG17_18PL)
+
+//
+// Beginning of MG18:
+//
+#if (G11PL >= G18PL) || (G11PL == 0)
+#define MG18_11PL ~(1)
+#else
+#define MG18_11PL 0xFFFF
+#endif
+#if (G12PL >= G18PL) || (G12PL == 0)
+#define MG18_12PL ~(1 << 1)
+#else
+#define MG18_12PL 0xFFFF
+#endif
+#if (G13PL >= G18PL) || (G13PL == 0)
+#define MG18_13PL ~(1 << 2)
+#else
+#define MG18_13PL 0xFFFF
+#endif
+#if (G14PL >= G18PL) || (G14PL == 0)
+#define MG18_14PL ~(1 << 3)
+#else
+#define MG18_14PL 0xFFFF
+#endif
+#if (G15PL >= G18PL) || (G15PL == 0)
+#define MG18_15PL ~(1 << 4)
+#else
+#define MG18_15PL 0xFFFF
+#endif
+#if (G16PL >= G18PL) || (G16PL == 0)
+#define MG18_16PL ~(1 << 5)
+#else
+#define MG18_16PL 0xFFFF
+#endif
+#if (G17PL >= G18PL) || (G17PL == 0)
+#define MG18_17PL ~(1 << 6)
+#else
+#define MG18_17PL 0xFFFF
+#endif
+#define MG18_18PL 0x007F
+#define MG18 (MG18_11PL & MG18_12PL & MG18_13PL & MG18_14PL & \
+ MG18_15PL & MG18_16PL & MG18_17PL & MG18_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG21 to MG28:
+//
+
+//
+// Beginning of MG21:
+//
+#if (G22PL >= G21PL) || (G22PL == 0)
+#define MG21_12PL ~(1 << 1)
+#else
+#define MG21_12PL 0xFFFF
+#endif
+#if (G23PL >= G21PL) || (G23PL == 0)
+#define MG21_13PL ~(1 << 2)
+#else
+#define MG21_13PL 0xFFFF
+#endif
+#if (G24PL >= G21PL) || (G24PL == 0)
+#define MG21_14PL ~(1 << 3)
+#else
+#define MG21_14PL 0xFFFF
+#endif
+#if (G25PL >= G21PL) || (G25PL == 0)
+#define MG21_15PL ~(1 << 4)
+#else
+#define MG21_15PL 0xFFFF
+#endif
+#if (G26PL >= G21PL) || (G26PL == 0)
+#define MG21_16PL ~(1 << 5)
+#else
+#define MG21_16PL 0xFFFF
+#endif
+#if (G27PL >= G21PL) || (G27PL == 0)
+#define MG21_17PL ~(1 << 6)
+#else
+#define MG21_17PL 0xFFFF
+#endif
+#if (G28PL >= G21PL) || (G28PL == 0)
+#define MG21_18PL ~(1 << 7)
+#else
+#define MG21_18PL 0xFFFF
+#endif
+#define MG21_11PL 0x00FE
+#define MG21 (MG21_11PL & MG21_12PL & MG21_13PL & MG21_14PL & \
+ MG21_15PL & MG21_16PL & MG21_17PL & MG21_18PL)
+
+//
+// Beginning of MG22:
+//
+#if (G21PL >= G22PL) || (G21PL == 0)
+#define MG22_11PL ~(1)
+#else
+#define MG22_11PL 0xFFFF
+#endif
+#if (G23PL >= G22PL) || (G23PL == 0)
+#define MG22_13PL ~(1 << 2)
+#else
+#define MG22_13PL 0xFFFF
+#endif
+#if (G24PL >= G22PL) || (G24PL == 0)
+#define MG22_14PL ~(1 << 3)
+#else
+#define MG22_14PL 0xFFFF
+#endif
+#if (G25PL >= G22PL) || (G25PL == 0)
+#define MG22_15PL ~(1 << 4)
+#else
+#define MG22_15PL 0xFFFF
+#endif
+#if (G26PL >= G22PL) || (G26PL == 0)
+#define MG22_16PL ~(1 << 5)
+#else
+#define MG22_16PL 0xFFFF
+#endif
+#if (G27PL >= G22PL) || (G27PL == 0)
+#define MG22_17PL ~(1 << 6)
+#else
+#define MG22_17PL 0xFFFF
+#endif
+#if (G28PL >= G22PL) || (G28PL == 0)
+#define MG22_18PL ~(1 << 7)
+#else
+#define MG22_18PL 0xFFFF
+#endif
+#define MG22_12PL 0x00FD
+#define MG22 (MG22_11PL & MG22_12PL & MG22_13PL & MG22_14PL & \
+ MG22_15PL & MG22_16PL & MG22_17PL & MG22_18PL)
+
+//
+// Beginning of MG23:
+//
+#if (G21PL >= G23PL) || (G21PL == 0)
+#define MG23_11PL ~(1)
+#else
+#define MG23_11PL 0xFFFF
+#endif
+#if (G22PL >= G23PL) || (G22PL == 0)
+#define MG23_12PL ~(1 << 1)
+#else
+#define MG23_12PL 0xFFFF
+#endif
+#if (G24PL >= G23PL) || (G24PL == 0)
+#define MG23_14PL ~(1 << 3)
+#else
+#define MG23_14PL 0xFFFF
+#endif
+#if (G25PL >= G23PL) || (G25PL == 0)
+#define MG23_15PL ~(1 << 4)
+#else
+#define MG23_15PL 0xFFFF
+#endif
+#if (G26PL >= G23PL) || (G26PL == 0)
+#define MG23_16PL ~(1 << 5)
+#else
+#define MG23_16PL 0xFFFF
+#endif
+#if (G27PL >= G23PL) || (G27PL == 0)
+#define MG23_17PL ~(1 << 6)
+#else
+#define MG23_17PL 0xFFFF
+#endif
+#if (G28PL >= G23PL) || (G28PL == 0)
+#define MG23_18PL ~(1 << 7)
+#else
+#define MG23_18PL 0xFFFF
+#endif
+#define MG23_13PL 0x00FB
+#define MG23 (MG23_11PL & MG23_12PL & MG23_13PL & MG23_14PL & \
+ MG23_15PL & MG23_16PL & MG23_17PL & MG23_18PL)
+
+//
+// Beginning of MG24:
+//
+#if (G21PL >= G24PL) || (G21PL == 0)
+#define MG24_11PL ~(1)
+#else
+#define MG24_11PL 0xFFFF
+#endif
+#if (G22PL >= G24PL) || (G22PL == 0)
+#define MG24_12PL ~(1 << 1)
+#else
+#define MG24_12PL 0xFFFF
+#endif
+#if (G23PL >= G24PL) || (G23PL == 0)
+#define MG24_13PL ~(1 << 2)
+#else
+#define MG24_13PL 0xFFFF
+#endif
+#if (G25PL >= G24PL) || (G25PL == 0)
+#define MG24_15PL ~(1 << 4)
+#else
+#define MG24_15PL 0xFFFF
+#endif
+#if (G26PL >= G24PL) || (G26PL == 0)
+#define MG24_16PL ~(1 << 5)
+#else
+#define MG24_16PL 0xFFFF
+#endif
+#if (G27PL >= G24PL) || (G27PL == 0)
+#define MG24_17PL ~(1 << 6)
+#else
+#define MG24_17PL 0xFFFF
+#endif
+#if (G28PL >= G24PL) || (G28PL == 0)
+#define MG24_18PL ~(1 << 7)
+#else
+#define MG24_18PL 0xFFFF
+#endif
+#define MG24_14PL 0x00F7
+#define MG24 (MG24_11PL & MG24_12PL & MG24_13PL & MG24_14PL & \
+ MG24_15PL & MG24_16PL & MG24_17PL & MG24_18PL)
+
+//
+// Beginning of MG25:
+//
+#if (G21PL >= G25PL) || (G21PL == 0)
+#define MG25_11PL ~(1)
+#else
+#define MG25_11PL 0xFFFF
+#endif
+#if (G22PL >= G25PL) || (G22PL == 0)
+#define MG25_12PL ~(1 << 1)
+#else
+#define MG25_12PL 0xFFFF
+#endif
+#if (G23PL >= G25PL) || (G23PL == 0)
+#define MG25_13PL ~(1 << 2)
+#else
+#define MG25_13PL 0xFFFF
+#endif
+#if (G24PL >= G25PL) || (G24PL == 0)
+#define MG25_14PL ~(1 << 3)
+#else
+#define MG25_14PL 0xFFFF
+#endif
+#if (G26PL >= G25PL) || (G26PL == 0)
+#define MG25_16PL ~(1 << 5)
+#else
+#define MG25_16PL 0xFFFF
+#endif
+#if (G27PL >= G25PL) || (G27PL == 0)
+#define MG25_17PL ~(1 << 6)
+#else
+#define MG25_17PL 0xFFFF
+#endif
+#if (G28PL >= G25PL) || (G28PL == 0)
+#define MG25_18PL ~(1 << 7)
+#else
+#define MG25_18PL 0xFFFF
+#endif
+#define MG25_15PL 0x00EF
+#define MG25 (MG25_11PL & MG25_12PL & MG25_13PL & MG25_14PL & \
+ MG25_15PL & MG25_16PL & MG25_17PL & MG25_18PL)
+
+//
+// Beginning of MG26:
+//
+#if (G21PL >= G26PL) || (G21PL == 0)
+#define MG26_11PL ~(1)
+#else
+#define MG26_11PL 0xFFFF
+#endif
+#if (G22PL >= G26PL) || (G22PL == 0)
+#define MG26_12PL ~(1 << 1)
+#else
+#define MG26_12PL 0xFFFF
+#endif
+#if (G23PL >= G26PL) || (G23PL == 0)
+#define MG26_13PL ~(1 << 2)
+#else
+#define MG26_13PL 0xFFFF
+#endif
+#if (G24PL >= G26PL) || (G24PL == 0)
+#define MG26_14PL ~(1 << 3)
+#else
+#define MG26_14PL 0xFFFF
+#endif
+#if (G25PL >= G26PL) || (G25PL == 0)
+#define MG26_15PL ~(1 << 4)
+#else
+#define MG26_15PL 0xFFFF
+#endif
+#if (G27PL >= G26PL) || (G27PL == 0)
+#define MG26_17PL ~(1 << 6)
+#else
+#define MG26_17PL 0xFFFF
+#endif
+#if (G28PL >= G26PL) || (G28PL == 0)
+#define MG26_18PL ~(1 << 7)
+#else
+#define MG26_18PL 0xFFFF
+#endif
+#define MG26_16PL 0x00DF
+#define MG26 (MG26_11PL & MG26_12PL & MG26_13PL & MG26_14PL & \
+ MG26_15PL & MG26_16PL & MG26_17PL & MG26_18PL)
+
+//
+// Beginning of MG27:
+//
+#if (G21PL >= G27PL) || (G21PL == 0)
+#define MG27_11PL ~(1)
+#else
+#define MG27_11PL 0xFFFF
+#endif
+#if (G22PL >= G27PL) || (G22PL == 0)
+#define MG27_12PL ~(1 << 1)
+#else
+#define MG27_12PL 0xFFFF
+#endif
+#if (G23PL >= G27PL) || (G23PL == 0)
+#define MG27_13PL ~(1 << 2)
+#else
+#define MG27_13PL 0xFFFF
+#endif
+#if (G24PL >= G27PL) || (G24PL == 0)
+#define MG27_14PL ~(1 << 3)
+#else
+#define MG27_14PL 0xFFFF
+#endif
+#if (G25PL >= G27PL) || (G25PL == 0)
+#define MG27_15PL ~(1 << 4)
+#else
+#define MG27_15PL 0xFFFF
+#endif
+#if (G26PL >= G27PL) || (G26PL == 0)
+#define MG27_16PL ~(1 << 5)
+#else
+#define MG27_16PL 0xFFFF
+#endif
+#if (G28PL >= G27PL) || (G28PL == 0)
+#define MG27_18PL ~(1 << 7)
+#else
+#define MG27_18PL 0xFFFF
+#endif
+#define MG27_17PL 0x00BF
+#define MG27 (MG27_11PL & MG27_12PL & MG27_13PL & MG27_14PL & \
+ MG27_15PL & MG27_16PL & MG27_17PL & MG27_18PL)
+
+//
+// Beginning of MG28:
+//
+#if (G21PL >= G28PL) || (G21PL == 0)
+#define MG28_11PL ~(1)
+#else
+#define MG28_11PL 0xFFFF
+#endif
+#if (G22PL >= G28PL) || (G22PL == 0)
+#define MG28_12PL ~(1 << 1)
+#else
+#define MG28_12PL 0xFFFF
+#endif
+#if (G23PL >= G28PL) || (G23PL == 0)
+#define MG28_13PL ~(1 << 2)
+#else
+#define MG28_13PL 0xFFFF
+#endif
+#if (G24PL >= G28PL) || (G24PL == 0)
+#define MG28_14PL ~(1 << 3)
+#else
+#define MG28_14PL 0xFFFF
+#endif
+#if (G25PL >= G28PL) || (G25PL == 0)
+#define MG28_15PL ~(1 << 4)
+#else
+#define MG28_15PL 0xFFFF
+#endif
+#if (G26PL >= G28PL) || (G26PL == 0)
+#define MG28_16PL ~(1 << 5)
+#else
+#define MG28_16PL 0xFFFF
+#endif
+#if (G27PL >= G28PL) || (G27PL == 0)
+#define MG28_17PL ~(1 << 6)
+#else
+#define MG28_17PL 0xFFFF
+#endif
+#define MG28_18PL 0x007F
+#define MG28 (MG28_11PL & MG28_12PL & MG28_13PL & MG28_14PL & \
+ MG28_15PL & MG28_16PL & MG28_17PL & MG28_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG31 to MG38:
+//
+
+//
+// Beginning of MG31:
+//
+#if (G32PL >= G31PL) || (G32PL == 0)
+#define MG31_12PL ~(1 << 1)
+#else
+#define MG31_12PL 0xFFFF
+#endif
+#if (G33PL >= G31PL) || (G33PL == 0)
+#define MG31_13PL ~(1 << 2)
+#else
+#define MG31_13PL 0xFFFF
+#endif
+#if (G34PL >= G31PL) || (G34PL == 0)
+#define MG31_14PL ~(1 << 3)
+#else
+#define MG31_14PL 0xFFFF
+#endif
+#if (G35PL >= G31PL) || (G35PL == 0)
+#define MG31_15PL ~(1 << 4)
+#else
+#define MG31_15PL 0xFFFF
+#endif
+#if (G36PL >= G31PL) || (G36PL == 0)
+#define MG31_16PL ~(1 << 5)
+#else
+#define MG31_16PL 0xFFFF
+#endif
+#if (G37PL >= G31PL) || (G37PL == 0)
+#define MG31_17PL ~(1 << 6)
+#else
+#define MG31_17PL 0xFFFF
+#endif
+#if (G38PL >= G31PL) || (G38PL == 0)
+#define MG31_18PL ~(1 << 7)
+#else
+#define MG31_18PL 0xFFFF
+#endif
+#define MG31_11PL 0x00FE
+#define MG31 (MG31_11PL & MG31_12PL & MG31_13PL & MG31_14PL & \
+ MG31_15PL & MG31_16PL & MG31_17PL & MG31_18PL)
+
+//
+// Beginning of MG32:
+//
+#if (G31PL >= G32PL) || (G31PL == 0)
+#define MG32_11PL ~(1)
+#else
+#define MG32_11PL 0xFFFF
+#endif
+#if (G33PL >= G32PL) || (G33PL == 0)
+#define MG32_13PL ~(1 << 2)
+#else
+#define MG32_13PL 0xFFFF
+#endif
+#if (G34PL >= G32PL) || (G34PL == 0)
+#define MG32_14PL ~(1 << 3)
+#else
+#define MG32_14PL 0xFFFF
+#endif
+#if (G35PL >= G32PL) || (G35PL == 0)
+#define MG32_15PL ~(1 << 4)
+#else
+#define MG32_15PL 0xFFFF
+#endif
+#if (G36PL >= G32PL) || (G36PL == 0)
+#define MG32_16PL ~(1 << 5)
+#else
+#define MG32_16PL 0xFFFF
+#endif
+#if (G37PL >= G32PL) || (G37PL == 0)
+#define MG32_17PL ~(1 << 6)
+#else
+#define MG32_17PL 0xFFFF
+#endif
+#if (G38PL >= G32PL) || (G38PL == 0)
+#define MG32_18PL ~(1 << 7)
+#else
+#define MG32_18PL 0xFFFF
+#endif
+#define MG32_12PL 0x00FD
+#define MG32 (MG32_11PL & MG32_12PL & MG32_13PL & MG32_14PL & \
+ MG32_15PL & MG32_16PL & MG32_17PL & MG32_18PL)
+
+//
+// Beginning of MG33:
+//
+#if (G31PL >= G33PL) || (G31PL == 0)
+#define MG33_11PL ~(1)
+#else
+#define MG33_11PL 0xFFFF
+#endif
+#if (G32PL >= G33PL) || (G32PL == 0)
+#define MG33_12PL ~(1 << 1)
+#else
+#define MG33_12PL 0xFFFF
+#endif
+#if (G34PL >= G33PL) || (G34PL == 0)
+#define MG33_14PL ~(1 << 3)
+#else
+#define MG33_14PL 0xFFFF
+#endif
+#if (G35PL >= G33PL) || (G35PL == 0)
+#define MG33_15PL ~(1 << 4)
+#else
+#define MG33_15PL 0xFFFF
+#endif
+#if (G36PL >= G33PL) || (G36PL == 0)
+#define MG33_16PL ~(1 << 5)
+#else
+#define MG33_16PL 0xFFFF
+#endif
+#if (G37PL >= G33PL) || (G37PL == 0)
+#define MG33_17PL ~(1 << 6)
+#else
+#define MG33_17PL 0xFFFF
+#endif
+#if (G38PL >= G33PL) || (G38PL == 0)
+#define MG33_18PL ~(1 << 7)
+#else
+#define MG33_18PL 0xFFFF
+#endif
+#define MG33_13PL 0x00FB
+#define MG33 (MG33_11PL & MG33_12PL & MG33_13PL & MG33_14PL & \
+ MG33_15PL & MG33_16PL & MG33_17PL & MG33_18PL)
+
+//
+// Beginning of MG34:
+//
+#if (G31PL >= G34PL) || (G31PL == 0)
+#define MG34_11PL ~(1)
+#else
+#define MG34_11PL 0xFFFF
+#endif
+#if (G32PL >= G34PL) || (G32PL == 0)
+#define MG34_12PL ~(1 << 1)
+#else
+#define MG34_12PL 0xFFFF
+#endif
+#if (G33PL >= G34PL) || (G33PL == 0)
+#define MG34_13PL ~(1 << 2)
+#else
+#define MG34_13PL 0xFFFF
+#endif
+#if (G35PL >= G34PL) || (G35PL == 0)
+#define MG34_15PL ~(1 << 4)
+#else
+#define MG34_15PL 0xFFFF
+#endif
+#if (G36PL >= G34PL) || (G36PL == 0)
+#define MG34_16PL ~(1 << 5)
+#else
+#define MG34_16PL 0xFFFF
+#endif
+#if (G37PL >= G34PL) || (G37PL == 0)
+#define MG34_17PL ~(1 << 6)
+#else
+#define MG34_17PL 0xFFFF
+#endif
+#if (G38PL >= G34PL) || (G38PL == 0)
+#define MG34_18PL ~(1 << 7)
+#else
+#define MG34_18PL 0xFFFF
+#endif
+#define MG34_14PL 0x00F7
+#define MG34 (MG34_11PL & MG34_12PL & MG34_13PL & MG34_14PL & \
+ MG34_15PL & MG34_16PL & MG34_17PL & MG34_18PL)
+
+//
+// Beginning of MG35:
+//
+#if (G31PL >= G35PL) || (G31PL == 0)
+#define MG35_11PL ~(1)
+#else
+#define MG35_11PL 0xFFFF
+#endif
+#if (G32PL >= G35PL) || (G32PL == 0)
+#define MG35_12PL ~(1 << 1)
+#else
+#define MG35_12PL 0xFFFF
+#endif
+#if (G33PL >= G35PL) || (G33PL == 0)
+#define MG35_13PL ~(1 << 2)
+#else
+#define MG35_13PL 0xFFFF
+#endif
+#if (G34PL >= G35PL) || (G34PL == 0)
+#define MG35_14PL ~(1 << 3)
+#else
+#define MG35_14PL 0xFFFF
+#endif
+#if (G36PL >= G35PL) || (G36PL == 0)
+#define MG35_16PL ~(1 << 5)
+#else
+#define MG35_16PL 0xFFFF
+#endif
+#if (G37PL >= G35PL) || (G37PL == 0)
+#define MG35_17PL ~(1 << 6)
+#else
+#define MG35_17PL 0xFFFF
+#endif
+#if (G38PL >= G35PL) || (G38PL == 0)
+#define MG35_18PL ~(1 << 7)
+#else
+#define MG35_18PL 0xFFFF
+#endif
+#define MG35_15PL 0x00EF
+#define MG35 (MG35_11PL & MG35_12PL & MG35_13PL & MG35_14PL & \
+ MG35_15PL & MG35_16PL & MG35_17PL & MG35_18PL)
+
+//
+// Beginning of MG36:
+//
+#if (G31PL >= G36PL) || (G31PL == 0)
+#define MG36_11PL ~(1)
+#else
+#define MG36_11PL 0xFFFF
+#endif
+#if (G32PL >= G36PL) || (G32PL == 0)
+#define MG36_12PL ~(1 << 1)
+#else
+#define MG36_12PL 0xFFFF
+#endif
+#if (G33PL >= G36PL) || (G33PL == 0)
+#define MG36_13PL ~(1 << 2)
+#else
+#define MG36_13PL 0xFFFF
+#endif
+#if (G34PL >= G36PL) || (G34PL == 0)
+#define MG36_14PL ~(1 << 3)
+#else
+#define MG36_14PL 0xFFFF
+#endif
+#if (G35PL >= G36PL) || (G35PL == 0)
+#define MG36_15PL ~(1 << 4)
+#else
+#define MG36_15PL 0xFFFF
+#endif
+#if (G37PL >= G36PL) || (G37PL == 0)
+#define MG36_17PL ~(1 << 6)
+#else
+#define MG36_17PL 0xFFFF
+#endif
+#if (G38PL >= G36PL) || (G38PL == 0)
+#define MG36_18PL ~(1 << 7)
+#else
+#define MG36_18PL 0xFFFF
+#endif
+#define MG36_16PL 0x00DF
+#define MG36 (MG36_11PL & MG36_12PL & MG36_13PL & MG36_14PL & \
+ MG36_15PL & MG36_16PL & MG36_17PL & MG36_18PL)
+
+//
+// Beginning of MG37:
+//
+#if (G31PL >= G37PL) || (G31PL == 0)
+#define MG37_11PL ~(1)
+#else
+#define MG37_11PL 0xFFFF
+#endif
+#if (G32PL >= G37PL) || (G32PL == 0)
+#define MG37_12PL ~(1 << 1)
+#else
+#define MG37_12PL 0xFFFF
+#endif
+#if (G33PL >= G37PL) || (G33PL == 0)
+#define MG37_13PL ~(1 << 2)
+#else
+#define MG37_13PL 0xFFFF
+#endif
+#if (G34PL >= G37PL) || (G34PL == 0)
+#define MG37_14PL ~(1 << 3)
+#else
+#define MG37_14PL 0xFFFF
+#endif
+#if (G35PL >= G37PL) || (G35PL == 0)
+#define MG37_15PL ~(1 << 4)
+#else
+#define MG37_15PL 0xFFFF
+#endif
+#if (G36PL >= G37PL) || (G36PL == 0)
+#define MG37_16PL ~(1 << 5)
+#else
+#define MG37_16PL 0xFFFF
+#endif
+#if (G38PL >= G37PL) || (G38PL == 0)
+#define MG37_18PL ~(1 << 7)
+#else
+#define MG37_18PL 0xFFFF
+#endif
+#define MG37_17PL 0x00BF
+#define MG37 (MG37_11PL & MG37_12PL & MG37_13PL & MG37_14PL & \
+ MG37_15PL & MG37_16PL & MG37_17PL & MG37_18PL)
+
+//
+// Beginning of MG38:
+//
+#if (G31PL >= G38PL) || (G31PL == 0)
+#define MG38_11PL ~(1)
+#else
+#define MG38_11PL 0xFFFF
+#endif
+#if (G32PL >= G38PL) || (G32PL == 0)
+#define MG38_12PL ~(1 << 1)
+#else
+#define MG38_12PL 0xFFFF
+#endif
+#if (G33PL >= G38PL) || (G33PL == 0)
+#define MG38_13PL ~(1 << 2)
+#else
+#define MG38_13PL 0xFFFF
+#endif
+#if (G34PL >= G38PL) || (G34PL == 0)
+#define MG38_14PL ~(1 << 3)
+#else
+#define MG38_14PL 0xFFFF
+#endif
+#if (G35PL >= G38PL) || (G35PL == 0)
+#define MG38_15PL ~(1 << 4)
+#else
+#define MG38_15PL 0xFFFF
+#endif
+#if (G36PL >= G38PL) || (G36PL == 0)
+#define MG38_16PL ~(1 << 5)
+#else
+#define MG38_16PL 0xFFFF
+#endif
+#if (G37PL >= G38PL) || (G37PL == 0)
+#define MG38_17PL ~(1 << 6)
+#else
+#define MG38_17PL 0xFFFF
+#endif
+#define MG38_18PL 0x007F
+#define MG38 (MG38_11PL & MG38_12PL & MG38_13PL & MG38_14PL & \
+ MG38_15PL & MG38_16PL & MG38_17PL & MG38_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG41 to MG48:
+//
+
+//
+// Beginning of MG41:
+//
+#if (G42PL >= G41PL) || (G42PL == 0)
+#define MG41_12PL ~(1 << 1)
+#else
+#define MG41_12PL 0xFFFF
+#endif
+#if (G43PL >= G41PL) || (G43PL == 0)
+#define MG41_13PL ~(1 << 2)
+#else
+#define MG41_13PL 0xFFFF
+#endif
+#if (G44PL >= G41PL) || (G44PL == 0)
+#define MG41_14PL ~(1 << 3)
+#else
+#define MG41_14PL 0xFFFF
+#endif
+#if (G45PL >= G41PL) || (G45PL == 0)
+#define MG41_15PL ~(1 << 4)
+#else
+#define MG41_15PL 0xFFFF
+#endif
+#if (G46PL >= G41PL) || (G46PL == 0)
+#define MG41_16PL ~(1 << 5)
+#else
+#define MG41_16PL 0xFFFF
+#endif
+#if (G47PL >= G41PL) || (G47PL == 0)
+#define MG41_17PL ~(1 << 6)
+#else
+#define MG41_17PL 0xFFFF
+#endif
+#if (G48PL >= G41PL) || (G48PL == 0)
+#define MG41_18PL ~(1 << 7)
+#else
+#define MG41_18PL 0xFFFF
+#endif
+#define MG41_11PL 0x00FE
+#define MG41 (MG41_11PL & MG41_12PL & MG41_13PL & MG41_14PL & \
+ MG41_15PL & MG41_16PL & MG41_17PL & MG41_18PL)
+
+//
+// Beginning of MG42:
+//
+#if (G41PL >= G42PL) || (G41PL == 0)
+#define MG42_11PL ~(1)
+#else
+#define MG42_11PL 0xFFFF
+#endif
+#if (G43PL >= G42PL) || (G43PL == 0)
+#define MG42_13PL ~(1 << 2)
+#else
+#define MG42_13PL 0xFFFF
+#endif
+#if (G44PL >= G42PL) || (G44PL == 0)
+#define MG42_14PL ~(1 << 3)
+#else
+#define MG42_14PL 0xFFFF
+#endif
+#if (G45PL >= G42PL) || (G45PL == 0)
+#define MG42_15PL ~(1 << 4)
+#else
+#define MG42_15PL 0xFFFF
+#endif
+#if (G46PL >= G42PL) || (G46PL == 0)
+#define MG42_16PL ~(1 << 5)
+#else
+#define MG42_16PL 0xFFFF
+#endif
+#if (G47PL >= G42PL) || (G47PL == 0)
+#define MG42_17PL ~(1 << 6)
+#else
+#define MG42_17PL 0xFFFF
+#endif
+#if (G48PL >= G42PL) || (G48PL == 0)
+#define MG42_18PL ~(1 << 7)
+#else
+#define MG42_18PL 0xFFFF
+#endif
+#define MG42_12PL 0x00FD
+#define MG42 (MG42_11PL & MG42_12PL & MG42_13PL & MG42_14PL & \
+ MG42_15PL & MG42_16PL & MG42_17PL & MG42_18PL)
+
+//
+// Beginning of MG43:
+//
+#if (G41PL >= G43PL) || (G41PL == 0)
+#define MG43_11PL ~(1)
+#else
+#define MG43_11PL 0xFFFF
+#endif
+#if (G42PL >= G43PL) || (G42PL == 0)
+#define MG43_12PL ~(1 << 1)
+#else
+#define MG43_12PL 0xFFFF
+#endif
+#if (G44PL >= G43PL) || (G44PL == 0)
+#define MG43_14PL ~(1 << 3)
+#else
+#define MG43_14PL 0xFFFF
+#endif
+#if (G45PL >= G43PL) || (G45PL == 0)
+#define MG43_15PL ~(1 << 4)
+#else
+#define MG43_15PL 0xFFFF
+#endif
+#if (G46PL >= G43PL) || (G46PL == 0)
+#define MG43_16PL ~(1 << 5)
+#else
+#define MG43_16PL 0xFFFF
+#endif
+#if (G47PL >= G43PL) || (G47PL == 0)
+#define MG43_17PL ~(1 << 6)
+#else
+#define MG43_17PL 0xFFFF
+#endif
+#if (G48PL >= G43PL) || (G48PL == 0)
+#define MG43_18PL ~(1 << 7)
+#else
+#define MG43_18PL 0xFFFF
+#endif
+#define MG43_13PL 0x00FB
+#define MG43 (MG43_11PL & MG43_12PL & MG43_13PL & MG43_14PL & \
+ MG43_15PL & MG43_16PL & MG43_17PL & MG43_18PL)
+
+//
+// Beginning of MG44:
+//
+#if (G41PL >= G44PL) || (G41PL == 0)
+#define MG44_11PL ~(1)
+#else
+#define MG44_11PL 0xFFFF
+#endif
+#if (G42PL >= G44PL) || (G42PL == 0)
+#define MG44_12PL ~(1 << 1)
+#else
+#define MG44_12PL 0xFFFF
+#endif
+#if (G43PL >= G44PL) || (G43PL == 0)
+#define MG44_13PL ~(1 << 2)
+#else
+#define MG44_13PL 0xFFFF
+#endif
+#if (G45PL >= G44PL) || (G45PL == 0)
+#define MG44_15PL ~(1 << 4)
+#else
+#define MG44_15PL 0xFFFF
+#endif
+#if (G46PL >= G44PL) || (G46PL == 0)
+#define MG44_16PL ~(1 << 5)
+#else
+#define MG44_16PL 0xFFFF
+#endif
+#if (G47PL >= G44PL) || (G47PL == 0)
+#define MG44_17PL ~(1 << 6)
+#else
+#define MG44_17PL 0xFFFF
+#endif
+#if (G48PL >= G44PL) || (G48PL == 0)
+#define MG44_18PL ~(1 << 7)
+#else
+#define MG44_18PL 0xFFFF
+#endif
+#define MG44_14PL 0x00F7
+#define MG44 (MG44_11PL & MG44_12PL & MG44_13PL & MG44_14PL & \
+ MG44_15PL & MG44_16PL & MG44_17PL & MG44_18PL)
+
+//
+// Beginning of MG45:
+//
+#if (G41PL >= G45PL) || (G41PL == 0)
+#define MG45_11PL ~(1)
+#else
+#define MG45_11PL 0xFFFF
+#endif
+#if (G42PL >= G45PL) || (G42PL == 0)
+#define MG45_12PL ~(1 << 1)
+#else
+#define MG45_12PL 0xFFFF
+#endif
+#if (G43PL >= G45PL) || (G43PL == 0)
+#define MG45_13PL ~(1 << 2)
+#else
+#define MG45_13PL 0xFFFF
+#endif
+#if (G44PL >= G45PL) || (G44PL == 0)
+#define MG45_14PL ~(1 << 3)
+#else
+#define MG45_14PL 0xFFFF
+#endif
+#if (G46PL >= G45PL) || (G46PL == 0)
+#define MG45_16PL ~(1 << 5)
+#else
+#define MG45_16PL 0xFFFF
+#endif
+#if (G47PL >= G45PL) || (G47PL == 0)
+#define MG45_17PL ~(1 << 6)
+#else
+#define MG45_17PL 0xFFFF
+#endif
+#if (G48PL >= G45PL) || (G48PL == 0)
+#define MG45_18PL ~(1 << 7)
+#else
+#define MG45_18PL 0xFFFF
+#endif
+#define MG45_15PL 0x00EF
+#define MG45 (MG45_11PL & MG45_12PL & MG45_13PL & MG45_14PL & \
+ MG45_15PL & MG45_16PL & MG45_17PL & MG45_18PL)
+
+//
+// Beginning of MG46:
+//
+#if (G41PL >= G46PL) || (G41PL == 0)
+#define MG46_11PL ~(1)
+#else
+#define MG46_11PL 0xFFFF
+#endif
+#if (G42PL >= G46PL) || (G42PL == 0)
+#define MG46_12PL ~(1 << 1)
+#else
+#define MG46_12PL 0xFFFF
+#endif
+#if (G43PL >= G46PL) || (G43PL == 0)
+#define MG46_13PL ~(1 << 2)
+#else
+#define MG46_13PL 0xFFFF
+#endif
+#if (G44PL >= G46PL) || (G44PL == 0)
+#define MG46_14PL ~(1 << 3)
+#else
+#define MG46_14PL 0xFFFF
+#endif
+#if (G45PL >= G46PL) || (G45PL == 0)
+#define MG46_15PL ~(1 << 4)
+#else
+#define MG46_15PL 0xFFFF
+#endif
+#if (G47PL >= G46PL) || (G47PL == 0)
+#define MG46_17PL ~(1 << 6)
+#else
+#define MG46_17PL 0xFFFF
+#endif
+#if (G48PL >= G46PL) || (G48PL == 0)
+#define MG46_18PL ~(1 << 7)
+#else
+#define MG46_18PL 0xFFFF
+#endif
+#define MG46_16PL 0x00DF
+#define MG46 (MG46_11PL & MG46_12PL & MG46_13PL & MG46_14PL & \
+ MG46_15PL & MG46_16PL & MG46_17PL & MG46_18PL)
+
+//
+// Beginning of MG47:
+//
+#if (G41PL >= G47PL) || (G41PL == 0)
+#define MG47_11PL ~(1)
+#else
+#define MG47_11PL 0xFFFF
+#endif
+#if (G42PL >= G47PL) || (G42PL == 0)
+#define MG47_12PL ~(1 << 1)
+#else
+#define MG47_12PL 0xFFFF
+#endif
+#if (G43PL >= G47PL) || (G43PL == 0)
+#define MG47_13PL ~(1 << 2)
+#else
+#define MG47_13PL 0xFFFF
+#endif
+#if (G44PL >= G47PL) || (G44PL == 0)
+#define MG47_14PL ~(1 << 3)
+#else
+#define MG47_14PL 0xFFFF
+#endif
+#if (G45PL >= G47PL) || (G45PL == 0)
+#define MG47_15PL ~(1 << 4)
+#else
+#define MG47_15PL 0xFFFF
+#endif
+#if (G46PL >= G47PL) || (G46PL == 0)
+#define MG47_16PL ~(1 << 5)
+#else
+#define MG47_16PL 0xFFFF
+#endif
+#if (G48PL >= G47PL) || (G48PL == 0)
+#define MG47_18PL ~(1 << 7)
+#else
+#define MG47_18PL 0xFFFF
+#endif
+#define MG47_17PL 0x00BF
+#define MG47 (MG47_11PL & MG47_12PL & MG47_13PL & MG47_14PL & \
+ MG47_15PL & MG47_16PL & MG47_17PL & MG47_18PL)
+
+//
+// Beginning of MG48:
+//
+#if (G41PL >= G48PL) || (G41PL == 0)
+#define MG48_11PL ~(1)
+#else
+#define MG48_11PL 0xFFFF
+#endif
+#if (G42PL >= G48PL) || (G42PL == 0)
+#define MG48_12PL ~(1 << 1)
+#else
+#define MG48_12PL 0xFFFF
+#endif
+#if (G43PL >= G48PL) || (G43PL == 0)
+#define MG48_13PL ~(1 << 2)
+#else
+#define MG48_13PL 0xFFFF
+#endif
+#if (G44PL >= G48PL) || (G44PL == 0)
+#define MG48_14PL ~(1 << 3)
+#else
+#define MG48_14PL 0xFFFF
+#endif
+#if (G45PL >= G48PL) || (G45PL == 0)
+#define MG48_15PL ~(1 << 4)
+#else
+#define MG48_15PL 0xFFFF
+#endif
+#if (G46PL >= G48PL) || (G46PL == 0)
+#define MG48_16PL ~(1 << 5)
+#else
+#define MG48_16PL 0xFFFF
+#endif
+#if (G47PL >= G48PL) || (G47PL == 0)
+#define MG48_17PL ~(1 << 6)
+#else
+#define MG48_17PL 0xFFFF
+#endif
+#define MG48_18PL 0x007F
+#define MG48 (MG48_11PL & MG48_12PL & MG48_13PL & MG48_14PL & \
+ MG48_15PL & MG48_16PL & MG48_17PL & MG48_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG51 to MG58:
+//
+
+//
+// Beginning of MG51:
+//
+#if (G52PL >= G51PL) || (G52PL == 0)
+#define MG51_12PL ~(1 << 1)
+#else
+#define MG51_12PL 0xFFFF
+#endif
+#if (G53PL >= G51PL) || (G53PL == 0)
+#define MG51_13PL ~(1 << 2)
+#else
+#define MG51_13PL 0xFFFF
+#endif
+#if (G54PL >= G51PL) || (G54PL == 0)
+#define MG51_14PL ~(1 << 3)
+#else
+#define MG51_14PL 0xFFFF
+#endif
+#if (G55PL >= G51PL) || (G55PL == 0)
+#define MG51_15PL ~(1 << 4)
+#else
+#define MG51_15PL 0xFFFF
+#endif
+#if (G56PL >= G51PL) || (G56PL == 0)
+#define MG51_16PL ~(1 << 5)
+#else
+#define MG51_16PL 0xFFFF
+#endif
+#if (G57PL >= G51PL) || (G57PL == 0)
+#define MG51_17PL ~(1 << 6)
+#else
+#define MG51_17PL 0xFFFF
+#endif
+#if (G58PL >= G51PL) || (G58PL == 0)
+#define MG51_18PL ~(1 << 7)
+#else
+#define MG51_18PL 0xFFFF
+#endif
+#define MG51_11PL 0x00FE
+#define MG51 (MG51_11PL & MG51_12PL & MG51_13PL & MG51_14PL & \
+ MG51_15PL & MG51_16PL & MG51_17PL & MG51_18PL)
+
+//
+// Beginning of MG52:
+//
+#if (G51PL >= G52PL) || (G51PL == 0)
+#define MG52_11PL ~(1)
+#else
+#define MG52_11PL 0xFFFF
+#endif
+#if (G53PL >= G52PL) || (G53PL == 0)
+#define MG52_13PL ~(1 << 2)
+#else
+#define MG52_13PL 0xFFFF
+#endif
+#if (G54PL >= G52PL) || (G54PL == 0)
+#define MG52_14PL ~(1 << 3)
+#else
+#define MG52_14PL 0xFFFF
+#endif
+#if (G55PL >= G52PL) || (G55PL == 0)
+#define MG52_15PL ~(1 << 4)
+#else
+#define MG52_15PL 0xFFFF
+#endif
+#if (G56PL >= G52PL) || (G56PL == 0)
+#define MG52_16PL ~(1 << 5)
+#else
+#define MG52_16PL 0xFFFF
+#endif
+#if (G57PL >= G52PL) || (G57PL == 0)
+#define MG52_17PL ~(1 << 6)
+#else
+#define MG52_17PL 0xFFFF
+#endif
+#if (G58PL >= G52PL) || (G58PL == 0)
+#define MG52_18PL ~(1 << 7)
+#else
+#define MG52_18PL 0xFFFF
+#endif
+#define MG52_12PL 0x00FD
+#define MG52 (MG52_11PL & MG52_12PL & MG52_13PL & MG52_14PL & \
+ MG52_15PL & MG52_16PL & MG52_17PL & MG52_18PL)
+
+//
+// Beginning of MG53:
+//
+#if (G51PL >= G53PL) || (G51PL == 0)
+#define MG53_11PL ~(1)
+#else
+#define MG53_11PL 0xFFFF
+#endif
+#if (G52PL >= G53PL) || (G52PL == 0)
+#define MG53_12PL ~(1 << 1)
+#else
+#define MG53_12PL 0xFFFF
+#endif
+#if (G54PL >= G53PL) || (G54PL == 0)
+#define MG53_14PL ~(1 << 3)
+#else
+#define MG53_14PL 0xFFFF
+#endif
+#if (G55PL >= G53PL) || (G55PL == 0)
+#define MG53_15PL ~(1 << 4)
+#else
+#define MG53_15PL 0xFFFF
+#endif
+#if (G56PL >= G53PL) || (G56PL == 0)
+#define MG53_16PL ~(1 << 5)
+#else
+#define MG53_16PL 0xFFFF
+#endif
+#if (G57PL >= G53PL) || (G57PL == 0)
+#define MG53_17PL ~(1 << 6)
+#else
+#define MG53_17PL 0xFFFF
+#endif
+#if (G58PL >= G53PL) || (G58PL == 0)
+#define MG53_18PL ~(1 << 7)
+#else
+#define MG53_18PL 0xFFFF
+#endif
+#define MG53_13PL 0x00FB
+#define MG53 (MG53_11PL & MG53_12PL & MG53_13PL & MG53_14PL & \
+ MG53_15PL & MG53_16PL & MG53_17PL & MG53_18PL)
+
+//
+// Beginning of MG54:
+//
+#if (G51PL >= G54PL) || (G51PL == 0)
+#define MG54_11PL ~(1)
+#else
+#define MG54_11PL 0xFFFF
+#endif
+#if (G52PL >= G54PL) || (G52PL == 0)
+#define MG54_12PL ~(1 << 1)
+#else
+#define MG54_12PL 0xFFFF
+#endif
+#if (G53PL >= G54PL) || (G53PL == 0)
+#define MG54_13PL ~(1 << 2)
+#else
+#define MG54_13PL 0xFFFF
+#endif
+#if (G55PL >= G54PL) || (G55PL == 0)
+#define MG54_15PL ~(1 << 4)
+#else
+#define MG54_15PL 0xFFFF
+#endif
+#if (G56PL >= G54PL) || (G56PL == 0)
+#define MG54_16PL ~(1 << 5)
+#else
+#define MG54_16PL 0xFFFF
+#endif
+#if (G57PL >= G54PL) || (G57PL == 0)
+#define MG54_17PL ~(1 << 6)
+#else
+#define MG54_17PL 0xFFFF
+#endif
+#if (G58PL >= G54PL) || (G58PL == 0)
+#define MG54_18PL ~(1 << 7)
+#else
+#define MG54_18PL 0xFFFF
+#endif
+#define MG54_14PL 0x00F7
+#define MG54 (MG54_11PL & MG54_12PL & MG54_13PL & MG54_14PL & \
+ MG54_15PL & MG54_16PL & MG54_17PL & MG54_18PL)
+
+//
+// Beginning of MG55:
+//
+#if (G51PL >= G55PL) || (G51PL == 0)
+#define MG55_11PL ~(1)
+#else
+#define MG55_11PL 0xFFFF
+#endif
+#if (G52PL >= G55PL) || (G52PL == 0)
+#define MG55_12PL ~(1 << 1)
+#else
+#define MG55_12PL 0xFFFF
+#endif
+#if (G53PL >= G55PL) || (G53PL == 0)
+#define MG55_13PL ~(1 << 2)
+#else
+#define MG55_13PL 0xFFFF
+#endif
+#if (G54PL >= G55PL) || (G54PL == 0)
+#define MG55_14PL ~(1 << 3)
+#else
+#define MG55_14PL 0xFFFF
+#endif
+#if (G56PL >= G55PL) || (G56PL == 0)
+#define MG55_16PL ~(1 << 5)
+#else
+#define MG55_16PL 0xFFFF
+#endif
+#if (G57PL >= G55PL) || (G57PL == 0)
+#define MG55_17PL ~(1 << 6)
+#else
+#define MG55_17PL 0xFFFF
+#endif
+#if (G58PL >= G55PL) || (G58PL == 0)
+#define MG55_18PL ~(1 << 7)
+#else
+#define MG55_18PL 0xFFFF
+#endif
+#define MG55_15PL 0x00EF
+#define MG55 (MG55_11PL & MG55_12PL & MG55_13PL & MG55_14PL & \
+ MG55_15PL & MG55_16PL & MG55_17PL & MG55_18PL)
+
+//
+// Beginning of MG56:
+//
+#if (G51PL >= G56PL) || (G51PL == 0)
+#define MG56_11PL ~(1)
+#else
+#define MG56_11PL 0xFFFF
+#endif
+#if (G52PL >= G56PL) || (G52PL == 0)
+#define MG56_12PL ~(1 << 1)
+#else
+#define MG56_12PL 0xFFFF
+#endif
+#if (G53PL >= G56PL) || (G53PL == 0)
+#define MG56_13PL ~(1 << 2)
+#else
+#define MG56_13PL 0xFFFF
+#endif
+#if (G54PL >= G56PL) || (G54PL == 0)
+#define MG56_14PL ~(1 << 3)
+#else
+#define MG56_14PL 0xFFFF
+#endif
+#if (G55PL >= G56PL) || (G55PL == 0)
+#define MG56_15PL ~(1 << 4)
+#else
+#define MG56_15PL 0xFFFF
+#endif
+#if (G57PL >= G56PL) || (G57PL == 0)
+#define MG56_17PL ~(1 << 6)
+#else
+#define MG56_17PL 0xFFFF
+#endif
+#if (G58PL >= G56PL) || (G58PL == 0)
+#define MG56_18PL ~(1 << 7)
+#else
+#define MG56_18PL 0xFFFF
+#endif
+#define MG56_16PL 0x00DF
+#define MG56 (MG56_11PL & MG56_12PL & MG56_13PL & MG56_14PL & \
+ MG56_15PL & MG56_16PL & MG56_17PL & MG56_18PL)
+
+//
+// Beginning of MG57:
+//
+#if (G51PL >= G57PL) || (G51PL == 0)
+#define MG57_11PL ~(1)
+#else
+#define MG57_11PL 0xFFFF
+#endif
+#if (G52PL >= G57PL) || (G52PL == 0)
+#define MG57_12PL ~(1 << 1)
+#else
+#define MG57_12PL 0xFFFF
+#endif
+#if (G53PL >= G57PL) || (G53PL == 0)
+#define MG57_13PL ~(1 << 2)
+#else
+#define MG57_13PL 0xFFFF
+#endif
+#if (G54PL >= G57PL) || (G54PL == 0)
+#define MG57_14PL ~(1 << 3)
+#else
+#define MG57_14PL 0xFFFF
+#endif
+#if (G55PL >= G57PL) || (G55PL == 0)
+#define MG57_15PL ~(1 << 4)
+#else
+#define MG57_15PL 0xFFFF
+#endif
+#if (G56PL >= G57PL) || (G56PL == 0)
+#define MG57_16PL ~(1 << 5)
+#else
+#define MG57_16PL 0xFFFF
+#endif
+#if (G58PL >= G57PL) || (G58PL == 0)
+#define MG57_18PL ~(1 << 7)
+#else
+#define MG57_18PL 0xFFFF
+#endif
+#define MG57_17PL 0x00BF
+#define MG57 (MG57_11PL & MG57_12PL & MG57_13PL & MG57_14PL & \
+ MG57_15PL & MG57_16PL & MG57_17PL & MG57_18PL)
+
+//
+// Beginning of MG58:
+//
+#if (G51PL >= G58PL) || (G51PL == 0)
+#define MG58_11PL ~(1)
+#else
+#define MG58_11PL 0xFFFF
+#endif
+#if (G52PL >= G58PL) || (G52PL == 0)
+#define MG58_12PL ~(1 << 1)
+#else
+#define MG58_12PL 0xFFFF
+#endif
+#if (G53PL >= G58PL) || (G53PL == 0)
+#define MG58_13PL ~(1 << 2)
+#else
+#define MG58_13PL 0xFFFF
+#endif
+#if (G54PL >= G58PL) || (G54PL == 0)
+#define MG58_14PL ~(1 << 3)
+#else
+#define MG58_14PL 0xFFFF
+#endif
+#if (G55PL >= G58PL) || (G55PL == 0)
+#define MG58_15PL ~(1 << 4)
+#else
+#define MG58_15PL 0xFFFF
+#endif
+#if (G56PL >= G58PL) || (G56PL == 0)
+#define MG58_16PL ~(1 << 5)
+#else
+#define MG58_16PL 0xFFFF
+#endif
+#if (G57PL >= G58PL) || (G57PL == 0)
+#define MG58_17PL ~(1 << 6)
+#else
+#define MG58_17PL 0xFFFF
+#endif
+#define MG58_18PL 0x007F
+#define MG58 (MG58_11PL & MG58_12PL & MG58_13PL & MG58_14PL & \
+ MG58_15PL & MG58_16PL & MG58_17PL & MG58_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG61 to MG68:
+//
+
+//
+// Beginning of MG61:
+//
+#if (G62PL >= G61PL) || (G62PL == 0)
+#define MG61_12PL ~(1 << 1)
+#else
+#define MG61_12PL 0xFFFF
+#endif
+#if (G63PL >= G61PL) || (G63PL == 0)
+#define MG61_13PL ~(1 << 2)
+#else
+#define MG61_13PL 0xFFFF
+#endif
+#if (G64PL >= G61PL) || (G64PL == 0)
+#define MG61_14PL ~(1 << 3)
+#else
+#define MG61_14PL 0xFFFF
+#endif
+#if (G65PL >= G61PL) || (G65PL == 0)
+#define MG61_15PL ~(1 << 4)
+#else
+#define MG61_15PL 0xFFFF
+#endif
+#if (G66PL >= G61PL) || (G66PL == 0)
+#define MG61_16PL ~(1 << 5)
+#else
+#define MG61_16PL 0xFFFF
+#endif
+#if (G67PL >= G61PL) || (G67PL == 0)
+#define MG61_17PL ~(1 << 6)
+#else
+#define MG61_17PL 0xFFFF
+#endif
+#if (G68PL >= G61PL) || (G68PL == 0)
+#define MG61_18PL ~(1 << 7)
+#else
+#define MG61_18PL 0xFFFF
+#endif
+#define MG61_11PL 0x00FE
+#define MG61 (MG61_11PL & MG61_12PL & MG61_13PL & MG61_14PL & \
+ MG61_15PL & MG61_16PL & MG61_17PL & MG61_18PL)
+
+//
+// Beginning of MG62:
+//
+#if (G61PL >= G62PL) || (G61PL == 0)
+#define MG62_11PL ~(1)
+#else
+#define MG62_11PL 0xFFFF
+#endif
+#if (G63PL >= G62PL) || (G63PL == 0)
+#define MG62_13PL ~(1 << 2)
+#else
+#define MG62_13PL 0xFFFF
+#endif
+#if (G64PL >= G62PL) || (G64PL == 0)
+#define MG62_14PL ~(1 << 3)
+#else
+#define MG62_14PL 0xFFFF
+#endif
+#if (G65PL >= G62PL) || (G65PL == 0)
+#define MG62_15PL ~(1 << 4)
+#else
+#define MG62_15PL 0xFFFF
+#endif
+#if (G66PL >= G62PL) || (G66PL == 0)
+#define MG62_16PL ~(1 << 5)
+#else
+#define MG62_16PL 0xFFFF
+#endif
+#if (G67PL >= G62PL) || (G67PL == 0)
+#define MG62_17PL ~(1 << 6)
+#else
+#define MG62_17PL 0xFFFF
+#endif
+#if (G68PL >= G62PL) || (G68PL == 0)
+#define MG62_18PL ~(1 << 7)
+#else
+#define MG62_18PL 0xFFFF
+#endif
+#define MG62_12PL 0x00FD
+#define MG62 (MG62_11PL & MG62_12PL & MG62_13PL & MG62_14PL & \
+ MG62_15PL & MG62_16PL & MG62_17PL & MG62_18PL)
+
+//
+// Beginning of MG63:
+//
+#if (G61PL >= G63PL) || (G61PL == 0)
+#define MG63_11PL ~(1)
+#else
+#define MG63_11PL 0xFFFF
+#endif
+#if (G62PL >= G63PL) || (G62PL == 0)
+#define MG63_12PL ~(1 << 1)
+#else
+#define MG63_12PL 0xFFFF
+#endif
+#if (G64PL >= G63PL) || (G64PL == 0)
+#define MG63_14PL ~(1 << 3)
+#else
+#define MG63_14PL 0xFFFF
+#endif
+#if (G65PL >= G63PL) || (G65PL == 0)
+#define MG63_15PL ~(1 << 4)
+#else
+#define MG63_15PL 0xFFFF
+#endif
+#if (G66PL >= G63PL) || (G66PL == 0)
+#define MG63_16PL ~(1 << 5)
+#else
+#define MG63_16PL 0xFFFF
+#endif
+#if (G67PL >= G63PL) || (G67PL == 0)
+#define MG63_17PL ~(1 << 6)
+#else
+#define MG63_17PL 0xFFFF
+#endif
+#if (G68PL >= G63PL) || (G68PL == 0)
+#define MG63_18PL ~(1 << 7)
+#else
+#define MG63_18PL 0xFFFF
+#endif
+#define MG63_13PL 0x00FB
+#define MG63 (MG63_11PL & MG63_12PL & MG63_13PL & MG63_14PL & \
+ MG63_15PL & MG63_16PL & MG63_17PL & MG63_18PL)
+
+//
+// Beginning of MG64:
+//
+#if (G61PL >= G64PL) || (G61PL == 0)
+#define MG64_11PL ~(1)
+#else
+#define MG64_11PL 0xFFFF
+#endif
+#if (G62PL >= G64PL) || (G62PL == 0)
+#define MG64_12PL ~(1 << 1)
+#else
+#define MG64_12PL 0xFFFF
+#endif
+#if (G63PL >= G64PL) || (G63PL == 0)
+#define MG64_13PL ~(1 << 2)
+#else
+#define MG64_13PL 0xFFFF
+#endif
+#if (G65PL >= G64PL) || (G65PL == 0)
+#define MG64_15PL ~(1 << 4)
+#else
+#define MG64_15PL 0xFFFF
+#endif
+#if (G66PL >= G64PL) || (G66PL == 0)
+#define MG64_16PL ~(1 << 5)
+#else
+#define MG64_16PL 0xFFFF
+#endif
+#if (G67PL >= G64PL) || (G67PL == 0)
+#define MG64_17PL ~(1 << 6)
+#else
+#define MG64_17PL 0xFFFF
+#endif
+#if (G68PL >= G64PL) || (G68PL == 0)
+#define MG64_18PL ~(1 << 7)
+#else
+#define MG64_18PL 0xFFFF
+#endif
+#define MG64_14PL 0x00F7
+#define MG64 (MG64_11PL & MG64_12PL & MG64_13PL & MG64_14PL & \
+ MG64_15PL & MG64_16PL & MG64_17PL & MG64_18PL)
+
+//
+// Beginning of MG65:
+//
+#if (G61PL >= G65PL) || (G61PL == 0)
+#define MG65_11PL ~(1)
+#else
+#define MG65_11PL 0xFFFF
+#endif
+#if (G62PL >= G65PL) || (G62PL == 0)
+#define MG65_12PL ~(1 << 1)
+#else
+#define MG65_12PL 0xFFFF
+#endif
+#if (G63PL >= G65PL) || (G63PL == 0)
+#define MG65_13PL ~(1 << 2)
+#else
+#define MG65_13PL 0xFFFF
+#endif
+#if (G64PL >= G65PL) || (G64PL == 0)
+#define MG65_14PL ~(1 << 3)
+#else
+#define MG65_14PL 0xFFFF
+#endif
+#if (G66PL >= G65PL) || (G66PL == 0)
+#define MG65_16PL ~(1 << 5)
+#else
+#define MG65_16PL 0xFFFF
+#endif
+#if (G67PL >= G65PL) || (G67PL == 0)
+#define MG65_17PL ~(1 << 6)
+#else
+#define MG65_17PL 0xFFFF
+#endif
+#if (G68PL >= G65PL) || (G68PL == 0)
+#define MG65_18PL ~(1 << 7)
+#else
+#define MG65_18PL 0xFFFF
+#endif
+#define MG65_15PL 0x00EF
+#define MG65 (MG65_11PL & MG65_12PL & MG65_13PL & MG65_14PL & \
+ MG65_15PL & MG65_16PL & MG65_17PL & MG65_18PL)
+
+//
+// Beginning of MG66:
+//
+#if (G61PL >= G66PL) || (G61PL == 0)
+#define MG66_11PL ~(1)
+#else
+#define MG66_11PL 0xFFFF
+#endif
+#if (G62PL >= G66PL) || (G62PL == 0)
+#define MG66_12PL ~(1 << 1)
+#else
+#define MG66_12PL 0xFFFF
+#endif
+#if (G63PL >= G66PL) || (G63PL == 0)
+#define MG66_13PL ~(1 << 2)
+#else
+#define MG66_13PL 0xFFFF
+#endif
+#if (G64PL >= G66PL) || (G64PL == 0)
+#define MG66_14PL ~(1 << 3)
+#else
+#define MG66_14PL 0xFFFF
+#endif
+#if (G65PL >= G66PL) || (G65PL == 0)
+#define MG66_15PL ~(1 << 4)
+#else
+#define MG66_15PL 0xFFFF
+#endif
+#if (G67PL >= G66PL) || (G67PL == 0)
+#define MG66_17PL ~(1 << 6)
+#else
+#define MG66_17PL 0xFFFF
+#endif
+#if (G68PL >= G66PL) || (G68PL == 0)
+#define MG66_18PL ~(1 << 7)
+#else
+#define MG66_18PL 0xFFFF
+#endif
+#define MG66_16PL 0x00DF
+#define MG66 (MG66_11PL & MG66_12PL & MG66_13PL & MG66_14PL & \
+ MG66_15PL & MG66_16PL & MG66_17PL & MG66_18PL)
+
+//
+// Beginning of MG67:
+//
+#if (G61PL >= G67PL) || (G61PL == 0)
+#define MG67_11PL ~(1)
+#else
+#define MG67_11PL 0xFFFF
+#endif
+#if (G62PL >= G67PL) || (G62PL == 0)
+#define MG67_12PL ~(1 << 1)
+#else
+#define MG67_12PL 0xFFFF
+#endif
+#if (G63PL >= G67PL) || (G63PL == 0)
+#define MG67_13PL ~(1 << 2)
+#else
+#define MG67_13PL 0xFFFF
+#endif
+#if (G64PL >= G67PL) || (G64PL == 0)
+#define MG67_14PL ~(1 << 3)
+#else
+#define MG67_14PL 0xFFFF
+#endif
+#if (G65PL >= G67PL) || (G65PL == 0)
+#define MG67_15PL ~(1 << 4)
+#else
+#define MG67_15PL 0xFFFF
+#endif
+#if (G66PL >= G67PL) || (G66PL == 0)
+#define MG67_16PL ~(1 << 5)
+#else
+#define MG67_16PL 0xFFFF
+#endif
+#if (G68PL >= G67PL) || (G68PL == 0)
+#define MG67_18PL ~(1 << 7)
+#else
+#define MG67_18PL 0xFFFF
+#endif
+#define MG67_17PL 0x00BF
+#define MG67 (MG67_11PL & MG67_12PL & MG67_13PL & MG67_14PL & \
+ MG67_15PL & MG67_16PL & MG67_17PL & MG67_18PL)
+
+//
+// Beginning of MG68:
+//
+#if (G61PL >= G68PL) || (G61PL == 0)
+#define MG68_11PL ~(1)
+#else
+#define MG68_11PL 0xFFFF
+#endif
+#if (G62PL >= G68PL) || (G62PL == 0)
+#define MG68_12PL ~(1 << 1)
+#else
+#define MG68_12PL 0xFFFF
+#endif
+#if (G63PL >= G68PL) || (G63PL == 0)
+#define MG68_13PL ~(1 << 2)
+#else
+#define MG68_13PL 0xFFFF
+#endif
+#if (G64PL >= G68PL) || (G64PL == 0)
+#define MG68_14PL ~(1 << 3)
+#else
+#define MG68_14PL 0xFFFF
+#endif
+#if (G65PL >= G68PL) || (G65PL == 0)
+#define MG68_15PL ~(1 << 4)
+#else
+#define MG68_15PL 0xFFFF
+#endif
+#if (G66PL >= G68PL) || (G66PL == 0)
+#define MG68_16PL ~(1 << 5)
+#else
+#define MG68_16PL 0xFFFF
+#endif
+#if (G67PL >= G68PL) || (G67PL == 0)
+#define MG68_17PL ~(1 << 6)
+#else
+#define MG68_17PL 0xFFFF
+#endif
+#define MG68_18PL 0x007F
+#define MG68 (MG68_11PL & MG68_12PL & MG68_13PL & MG68_14PL & \
+ MG68_15PL & MG68_16PL & MG68_17PL & MG68_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG71 to MG78:
+//
+
+//
+// Beginning of MG71:
+//
+#if (G72PL >= G71PL) || (G72PL == 0)
+#define MG71_12PL ~(1 << 1)
+#else
+#define MG71_12PL 0xFFFF
+#endif
+#if (G73PL >= G71PL) || (G73PL == 0)
+#define MG71_13PL ~(1 << 2)
+#else
+#define MG71_13PL 0xFFFF
+#endif
+#if (G74PL >= G71PL) || (G74PL == 0)
+#define MG71_14PL ~(1 << 3)
+#else
+#define MG71_14PL 0xFFFF
+#endif
+#if (G75PL >= G71PL) || (G75PL == 0)
+#define MG71_15PL ~(1 << 4)
+#else
+#define MG71_15PL 0xFFFF
+#endif
+#if (G76PL >= G71PL) || (G76PL == 0)
+#define MG71_16PL ~(1 << 5)
+#else
+#define MG71_16PL 0xFFFF
+#endif
+#if (G77PL >= G71PL) || (G77PL == 0)
+#define MG71_17PL ~(1 << 6)
+#else
+#define MG71_17PL 0xFFFF
+#endif
+#if (G78PL >= G71PL) || (G78PL == 0)
+#define MG71_18PL ~(1 << 7)
+#else
+#define MG71_18PL 0xFFFF
+#endif
+#define MG71_11PL 0x00FE
+#define MG71 (MG71_11PL & MG71_12PL & MG71_13PL & MG71_14PL & \
+ MG71_15PL & MG71_16PL & MG71_17PL & MG71_18PL)
+
+//
+// Beginning of MG72:
+//
+#if (G71PL >= G72PL) || (G71PL == 0)
+#define MG72_11PL ~(1)
+#else
+#define MG72_11PL 0xFFFF
+#endif
+#if (G73PL >= G72PL) || (G73PL == 0)
+#define MG72_13PL ~(1 << 2)
+#else
+#define MG72_13PL 0xFFFF
+#endif
+#if (G74PL >= G72PL) || (G74PL == 0)
+#define MG72_14PL ~(1 << 3)
+#else
+#define MG72_14PL 0xFFFF
+#endif
+#if (G75PL >= G72PL) || (G75PL == 0)
+#define MG72_15PL ~(1 << 4)
+#else
+#define MG72_15PL 0xFFFF
+#endif
+#if (G76PL >= G72PL) || (G76PL == 0)
+#define MG72_16PL ~(1 << 5)
+#else
+#define MG72_16PL 0xFFFF
+#endif
+#if (G77PL >= G72PL) || (G77PL == 0)
+#define MG72_17PL ~(1 << 6)
+#else
+#define MG72_17PL 0xFFFF
+#endif
+#if (G78PL >= G72PL) || (G78PL == 0)
+#define MG72_18PL ~(1 << 7)
+#else
+#define MG72_18PL 0xFFFF
+#endif
+#define MG72_12PL 0x00FD
+#define MG72 (MG72_11PL & MG72_12PL & MG72_13PL & MG72_14PL & \
+ MG72_15PL & MG72_16PL & MG72_17PL & MG72_18PL)
+
+//
+// Beginning of MG73:
+//
+#if (G71PL >= G73PL) || (G71PL == 0)
+#define MG73_11PL ~(1)
+#else
+#define MG73_11PL 0xFFFF
+#endif
+#if (G72PL >= G73PL) || (G72PL == 0)
+#define MG73_12PL ~(1 << 1)
+#else
+#define MG73_12PL 0xFFFF
+#endif
+#if (G74PL >= G73PL) || (G74PL == 0)
+#define MG73_14PL ~(1 << 3)
+#else
+#define MG73_14PL 0xFFFF
+#endif
+#if (G75PL >= G73PL) || (G75PL == 0)
+#define MG73_15PL ~(1 << 4)
+#else
+#define MG73_15PL 0xFFFF
+#endif
+#if (G76PL >= G73PL) || (G76PL == 0)
+#define MG73_16PL ~(1 << 5)
+#else
+#define MG73_16PL 0xFFFF
+#endif
+#if (G77PL >= G73PL) || (G77PL == 0)
+#define MG73_17PL ~(1 << 6)
+#else
+#define MG73_17PL 0xFFFF
+#endif
+#if (G78PL >= G73PL) || (G78PL == 0)
+#define MG73_18PL ~(1 << 7)
+#else
+#define MG73_18PL 0xFFFF
+#endif
+#define MG73_13PL 0x00FB
+#define MG73 (MG73_11PL & MG73_12PL & MG73_13PL & MG73_14PL & \
+ MG73_15PL & MG73_16PL & MG73_17PL & MG73_18PL)
+
+//
+// Beginning of MG74:
+//
+#if (G71PL >= G74PL) || (G71PL == 0)
+#define MG74_11PL ~(1)
+#else
+#define MG74_11PL 0xFFFF
+#endif
+#if (G72PL >= G74PL) || (G72PL == 0)
+#define MG74_12PL ~(1 << 1)
+#else
+#define MG74_12PL 0xFFFF
+#endif
+#if (G73PL >= G74PL) || (G73PL == 0)
+#define MG74_13PL ~(1 << 2)
+#else
+#define MG74_13PL 0xFFFF
+#endif
+#if (G75PL >= G74PL) || (G75PL == 0)
+#define MG74_15PL ~(1 << 4)
+#else
+#define MG74_15PL 0xFFFF
+#endif
+#if (G76PL >= G74PL) || (G76PL == 0)
+#define MG74_16PL ~(1 << 5)
+#else
+#define MG74_16PL 0xFFFF
+#endif
+#if (G77PL >= G74PL) || (G77PL == 0)
+#define MG74_17PL ~(1 << 6)
+#else
+#define MG74_17PL 0xFFFF
+#endif
+#if (G78PL >= G74PL) || (G78PL == 0)
+#define MG74_18PL ~(1 << 7)
+#else
+#define MG74_18PL 0xFFFF
+#endif
+#define MG74_14PL 0x00F7
+#define MG74 (MG74_11PL & MG74_12PL & MG74_13PL & MG74_14PL & \
+ MG74_15PL & MG74_16PL & MG74_17PL & MG74_18PL)
+
+//
+// Beginning of MG75:
+//
+#if (G71PL >= G75PL) || (G71PL == 0)
+#define MG75_11PL ~(1)
+#else
+#define MG75_11PL 0xFFFF
+#endif
+#if (G72PL >= G75PL) || (G72PL == 0)
+#define MG75_12PL ~(1 << 1)
+#else
+#define MG75_12PL 0xFFFF
+#endif
+#if (G73PL >= G75PL) || (G73PL == 0)
+#define MG75_13PL ~(1 << 2)
+#else
+#define MG75_13PL 0xFFFF
+#endif
+#if (G74PL >= G75PL) || (G74PL == 0)
+#define MG75_14PL ~(1 << 3)
+#else
+#define MG75_14PL 0xFFFF
+#endif
+#if (G76PL >= G75PL) || (G76PL == 0)
+#define MG75_16PL ~(1 << 5)
+#else
+#define MG75_16PL 0xFFFF
+#endif
+#if (G77PL >= G75PL) || (G77PL == 0)
+#define MG75_17PL ~(1 << 6)
+#else
+#define MG75_17PL 0xFFFF
+#endif
+#if (G78PL >= G75PL) || (G78PL == 0)
+#define MG75_18PL ~(1 << 7)
+#else
+#define MG75_18PL 0xFFFF
+#endif
+#define MG75_15PL 0x00EF
+#define MG75 (MG75_11PL & MG75_12PL & MG75_13PL & MG75_14PL & \
+ MG75_15PL & MG75_16PL & MG75_17PL & MG75_18PL)
+
+//
+// Beginning of MG76:
+//
+#if (G71PL >= G76PL) || (G71PL == 0)
+#define MG76_11PL ~(1)
+#else
+#define MG76_11PL 0xFFFF
+#endif
+#if (G72PL >= G76PL) || (G72PL == 0)
+#define MG76_12PL ~(1 << 1)
+#else
+#define MG76_12PL 0xFFFF
+#endif
+#if (G73PL >= G76PL) || (G73PL == 0)
+#define MG76_13PL ~(1 << 2)
+#else
+#define MG76_13PL 0xFFFF
+#endif
+#if (G74PL >= G76PL) || (G74PL == 0)
+#define MG76_14PL ~(1 << 3)
+#else
+#define MG76_14PL 0xFFFF
+#endif
+#if (G75PL >= G76PL) || (G75PL == 0)
+#define MG76_15PL ~(1 << 4)
+#else
+#define MG76_15PL 0xFFFF
+#endif
+#if (G77PL >= G76PL) || (G77PL == 0)
+#define MG76_17PL ~(1 << 6)
+#else
+#define MG76_17PL 0xFFFF
+#endif
+#if (G78PL >= G76PL) || (G78PL == 0)
+#define MG76_18PL ~(1 << 7)
+#else
+#define MG76_18PL 0xFFFF
+#endif
+#define MG76_16PL 0x00DF
+#define MG76 (MG76_11PL & MG76_12PL & MG76_13PL & MG76_14PL & \
+ MG76_15PL & MG76_16PL & MG76_17PL & MG76_18PL)
+
+//
+// Beginning of MG77:
+//
+#if (G71PL >= G77PL) || (G71PL == 0)
+#define MG77_11PL ~(1)
+#else
+#define MG77_11PL 0xFFFF
+#endif
+#if (G72PL >= G77PL) || (G72PL == 0)
+#define MG77_12PL ~(1 << 1)
+#else
+#define MG77_12PL 0xFFFF
+#endif
+#if (G73PL >= G77PL) || (G73PL == 0)
+#define MG77_13PL ~(1 << 2)
+#else
+#define MG77_13PL 0xFFFF
+#endif
+#if (G74PL >= G77PL) || (G74PL == 0)
+#define MG77_14PL ~(1 << 3)
+#else
+#define MG77_14PL 0xFFFF
+#endif
+#if (G75PL >= G77PL) || (G75PL == 0)
+#define MG77_15PL ~(1 << 4)
+#else
+#define MG77_15PL 0xFFFF
+#endif
+#if (G76PL >= G77PL) || (G76PL == 0)
+#define MG77_16PL ~(1 << 5)
+#else
+#define MG77_16PL 0xFFFF
+#endif
+#if (G78PL >= G77PL) || (G78PL == 0)
+#define MG77_18PL ~(1 << 7)
+#else
+#define MG77_18PL 0xFFFF
+#endif
+#define MG77_17PL 0x00BF
+#define MG77 (MG77_11PL & MG77_12PL & MG77_13PL & MG77_14PL & \
+ MG77_15PL & MG77_16PL & MG77_17PL & MG77_18PL)
+
+//
+// Beginning of MG78:
+//
+#if (G71PL >= G78PL) || (G71PL == 0)
+#define MG78_11PL ~(1)
+#else
+#define MG78_11PL 0xFFFF
+#endif
+#if (G72PL >= G78PL) || (G72PL == 0)
+#define MG78_12PL ~(1 << 1)
+#else
+#define MG78_12PL 0xFFFF
+#endif
+#if (G73PL >= G78PL) || (G73PL == 0)
+#define MG78_13PL ~(1 << 2)
+#else
+#define MG78_13PL 0xFFFF
+#endif
+#if (G74PL >= G78PL) || (G74PL == 0)
+#define MG78_14PL ~(1 << 3)
+#else
+#define MG78_14PL 0xFFFF
+#endif
+#if (G75PL >= G78PL) || (G75PL == 0)
+#define MG78_15PL ~(1 << 4)
+#else
+#define MG78_15PL 0xFFFF
+#endif
+#if (G76PL >= G78PL) || (G76PL == 0)
+#define MG78_16PL ~(1 << 5)
+#else
+#define MG78_16PL 0xFFFF
+#endif
+#if (G77PL >= G78PL) || (G77PL == 0)
+#define MG78_17PL ~(1 << 6)
+#else
+#define MG78_17PL 0xFFFF
+#endif
+#define MG78_18PL 0x007F
+#define MG78 (MG78_11PL & MG78_12PL & MG78_13PL & MG78_14PL & \
+ MG78_15PL & MG78_16PL & MG78_17PL & MG78_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG81 to MG88:
+//
+
+//
+// Beginning of MG81:
+//
+#if (G82PL >= G81PL) || (G82PL == 0)
+#define MG81_12PL ~(1 << 1)
+#else
+#define MG81_12PL 0xFFFF
+#endif
+#if (G83PL >= G81PL) || (G83PL == 0)
+#define MG81_13PL ~(1 << 2)
+#else
+#define MG81_13PL 0xFFFF
+#endif
+#if (G84PL >= G81PL) || (G84PL == 0)
+#define MG81_14PL ~(1 << 3)
+#else
+#define MG81_14PL 0xFFFF
+#endif
+#if (G85PL >= G81PL) || (G85PL == 0)
+#define MG81_15PL ~(1 << 4)
+#else
+#define MG81_15PL 0xFFFF
+#endif
+#if (G86PL >= G81PL) || (G86PL == 0)
+#define MG81_16PL ~(1 << 5)
+#else
+#define MG81_16PL 0xFFFF
+#endif
+#if (G87PL >= G81PL) || (G87PL == 0)
+#define MG81_17PL ~(1 << 6)
+#else
+#define MG81_17PL 0xFFFF
+#endif
+#if (G88PL >= G81PL) || (G88PL == 0)
+#define MG81_18PL ~(1 << 7)
+#else
+#define MG81_18PL 0xFFFF
+#endif
+#define MG81_11PL 0x00FE
+#define MG81 (MG81_11PL & MG81_12PL & MG81_13PL & MG81_14PL & \
+ MG81_15PL & MG81_16PL & MG81_17PL & MG81_18PL)
+
+//
+// Beginning of MG82:
+//
+#if (G81PL >= G82PL) || (G81PL == 0)
+#define MG82_11PL ~(1)
+#else
+#define MG82_11PL 0xFFFF
+#endif
+#if (G83PL >= G82PL) || (G83PL == 0)
+#define MG82_13PL ~(1 << 2)
+#else
+#define MG82_13PL 0xFFFF
+#endif
+#if (G84PL >= G82PL) || (G84PL == 0)
+#define MG82_14PL ~(1 << 3)
+#else
+#define MG82_14PL 0xFFFF
+#endif
+#if (G85PL >= G82PL) || (G85PL == 0)
+#define MG82_15PL ~(1 << 4)
+#else
+#define MG82_15PL 0xFFFF
+#endif
+#if (G86PL >= G82PL) || (G86PL == 0)
+#define MG82_16PL ~(1 << 5)
+#else
+#define MG82_16PL 0xFFFF
+#endif
+#if (G87PL >= G82PL) || (G87PL == 0)
+#define MG82_17PL ~(1 << 6)
+#else
+#define MG82_17PL 0xFFFF
+#endif
+#if (G88PL >= G82PL) || (G88PL == 0)
+#define MG82_18PL ~(1 << 7)
+#else
+#define MG82_18PL 0xFFFF
+#endif
+#define MG82_12PL 0x00FD
+#define MG82 (MG82_11PL & MG82_12PL & MG82_13PL & MG82_14PL & \
+ MG82_15PL & MG82_16PL & MG82_17PL & MG82_18PL)
+
+//
+// Beginning of MG83:
+//
+#if (G81PL >= G83PL) || (G81PL == 0)
+#define MG83_11PL ~(1)
+#else
+#define MG83_11PL 0xFFFF
+#endif
+#if (G82PL >= G83PL) || (G82PL == 0)
+#define MG83_12PL ~(1 << 1)
+#else
+#define MG83_12PL 0xFFFF
+#endif
+#if (G84PL >= G83PL) || (G84PL == 0)
+#define MG83_14PL ~(1 << 3)
+#else
+#define MG83_14PL 0xFFFF
+#endif
+#if (G85PL >= G83PL) || (G85PL == 0)
+#define MG83_15PL ~(1 << 4)
+#else
+#define MG83_15PL 0xFFFF
+#endif
+#if (G86PL >= G83PL) || (G86PL == 0)
+#define MG83_16PL ~(1 << 5)
+#else
+#define MG83_16PL 0xFFFF
+#endif
+#if (G87PL >= G83PL) || (G87PL == 0)
+#define MG83_17PL ~(1 << 6)
+#else
+#define MG83_17PL 0xFFFF
+#endif
+#if (G88PL >= G83PL) || (G88PL == 0)
+#define MG83_18PL ~(1 << 7)
+#else
+#define MG83_18PL 0xFFFF
+#endif
+#define MG83_13PL 0x00FB
+#define MG83 (MG83_11PL & MG83_12PL & MG83_13PL & MG83_14PL & \
+ MG83_15PL & MG83_16PL & MG83_17PL & MG83_18PL)
+
+//
+// Beginning of MG84:
+//
+#if (G81PL >= G84PL) || (G81PL == 0)
+#define MG84_11PL ~(1)
+#else
+#define MG84_11PL 0xFFFF
+#endif
+#if (G82PL >= G84PL) || (G82PL == 0)
+#define MG84_12PL ~(1 << 1)
+#else
+#define MG84_12PL 0xFFFF
+#endif
+#if (G83PL >= G84PL) || (G83PL == 0)
+#define MG84_13PL ~(1 << 2)
+#else
+#define MG84_13PL 0xFFFF
+#endif
+#if (G85PL >= G84PL) || (G85PL == 0)
+#define MG84_15PL ~(1 << 4)
+#else
+#define MG84_15PL 0xFFFF
+#endif
+#if (G86PL >= G84PL) || (G86PL == 0)
+#define MG84_16PL ~(1 << 5)
+#else
+#define MG84_16PL 0xFFFF
+#endif
+#if (G87PL >= G84PL) || (G87PL == 0)
+#define MG84_17PL ~(1 << 6)
+#else
+#define MG84_17PL 0xFFFF
+#endif
+#if (G88PL >= G84PL) || (G88PL == 0)
+#define MG84_18PL ~(1 << 7)
+#else
+#define MG84_18PL 0xFFFF
+#endif
+#define MG84_14PL 0x00F7
+#define MG84 (MG84_11PL & MG84_12PL & MG84_13PL & MG84_14PL & \
+ MG84_15PL & MG84_16PL & MG84_17PL & MG84_18PL)
+
+//
+// Beginning of MG85:
+//
+#if (G81PL >= G85PL) || (G81PL == 0)
+#define MG85_11PL ~(1)
+#else
+#define MG85_11PL 0xFFFF
+#endif
+#if (G82PL >= G85PL) || (G82PL == 0)
+#define MG85_12PL ~(1 << 1)
+#else
+#define MG85_12PL 0xFFFF
+#endif
+#if (G83PL >= G85PL) || (G83PL == 0)
+#define MG85_13PL ~(1 << 2)
+#else
+#define MG85_13PL 0xFFFF
+#endif
+#if (G84PL >= G85PL) || (G84PL == 0)
+#define MG85_14PL ~(1 << 3)
+#else
+#define MG85_14PL 0xFFFF
+#endif
+#if (G86PL >= G85PL) || (G86PL == 0)
+#define MG85_16PL ~(1 << 5)
+#else
+#define MG85_16PL 0xFFFF
+#endif
+#if (G87PL >= G85PL) || (G87PL == 0)
+#define MG85_17PL ~(1 << 6)
+#else
+#define MG85_17PL 0xFFFF
+#endif
+#if (G88PL >= G85PL) || (G88PL == 0)
+#define MG85_18PL ~(1 << 7)
+#else
+#define MG85_18PL 0xFFFF
+#endif
+#define MG85_15PL 0x00EF
+#define MG85 (MG85_11PL & MG85_12PL & MG85_13PL & MG85_14PL & \
+ MG85_15PL & MG85_16PL & MG85_17PL & MG85_18PL)
+
+//
+// Beginning of MG86:
+//
+#if (G81PL >= G86PL) || (G81PL == 0)
+#define MG86_11PL ~(1)
+#else
+#define MG86_11PL 0xFFFF
+#endif
+#if (G82PL >= G86PL) || (G82PL == 0)
+#define MG86_12PL ~(1 << 1)
+#else
+#define MG86_12PL 0xFFFF
+#endif
+#if (G83PL >= G86PL) || (G83PL == 0)
+#define MG86_13PL ~(1 << 2)
+#else
+#define MG86_13PL 0xFFFF
+#endif
+#if (G84PL >= G86PL) || (G84PL == 0)
+#define MG86_14PL ~(1 << 3)
+#else
+#define MG86_14PL 0xFFFF
+#endif
+#if (G85PL >= G86PL) || (G85PL == 0)
+#define MG86_15PL ~(1 << 4)
+#else
+#define MG86_15PL 0xFFFF
+#endif
+#if (G87PL >= G86PL) || (G87PL == 0)
+#define MG86_17PL ~(1 << 6)
+#else
+#define MG86_17PL 0xFFFF
+#endif
+#if (G88PL >= G86PL) || (G88PL == 0)
+#define MG86_18PL ~(1 << 7)
+#else
+#define MG86_18PL 0xFFFF
+#endif
+#define MG86_16PL 0x00DF
+#define MG86 (MG86_11PL & MG86_12PL & MG86_13PL & MG86_14PL & \
+ MG86_15PL & MG86_16PL & MG86_17PL & MG86_18PL)
+
+//
+// Beginning of MG87:
+//
+#if (G81PL >= G87PL) || (G81PL == 0)
+#define MG87_11PL ~(1)
+#else
+#define MG87_11PL 0xFFFF
+#endif
+#if (G82PL >= G87PL) || (G82PL == 0)
+#define MG87_12PL ~(1 << 1)
+#else
+#define MG87_12PL 0xFFFF
+#endif
+#if (G83PL >= G87PL) || (G83PL == 0)
+#define MG87_13PL ~(1 << 2)
+#else
+#define MG87_13PL 0xFFFF
+#endif
+#if (G84PL >= G87PL) || (G84PL == 0)
+#define MG87_14PL ~(1 << 3)
+#else
+#define MG87_14PL 0xFFFF
+#endif
+#if (G85PL >= G87PL) || (G85PL == 0)
+#define MG87_15PL ~(1 << 4)
+#else
+#define MG87_15PL 0xFFFF
+#endif
+#if (G86PL >= G87PL) || (G86PL == 0)
+#define MG87_16PL ~(1 << 5)
+#else
+#define MG87_16PL 0xFFFF
+#endif
+#if (G88PL >= G87PL) || (G88PL == 0)
+#define MG87_18PL ~(1 << 7)
+#else
+#define MG87_18PL 0xFFFF
+#endif
+#define MG87_17PL 0x00BF
+#define MG87 (MG87_11PL & MG87_12PL & MG87_13PL & MG87_14PL & \
+ MG87_15PL & MG87_16PL & MG87_17PL & MG87_18PL)
+
+//
+// Beginning of MG88:
+//
+#if (G81PL >= G88PL) || (G81PL == 0)
+#define MG88_11PL ~(1)
+#else
+#define MG88_11PL 0xFFFF
+#endif
+#if (G82PL >= G88PL) || (G82PL == 0)
+#define MG88_12PL ~(1 << 1)
+#else
+#define MG88_12PL 0xFFFF
+#endif
+#if (G83PL >= G88PL) || (G83PL == 0)
+#define MG88_13PL ~(1 << 2)
+#else
+#define MG88_13PL 0xFFFF
+#endif
+#if (G84PL >= G88PL) || (G84PL == 0)
+#define MG88_14PL ~(1 << 3)
+#else
+#define MG88_14PL 0xFFFF
+#endif
+#if (G85PL >= G88PL) || (G85PL == 0)
+#define MG88_15PL ~(1 << 4)
+#else
+#define MG88_15PL 0xFFFF
+#endif
+#if (G86PL >= G88PL) || (G86PL == 0)
+#define MG88_16PL ~(1 << 5)
+#else
+#define MG88_16PL 0xFFFF
+#endif
+#if (G87PL >= G88PL) || (G87PL == 0)
+#define MG88_17PL ~(1 << 6)
+#else
+#define MG88_17PL 0xFFFF
+#endif
+#define MG88_18PL 0x007F
+#define MG88 (MG88_11PL & MG88_12PL & MG88_13PL & MG88_14PL & \
+ MG88_15PL & MG88_16PL & MG88_17PL & MG88_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG91 to MG98:
+//
+
+//
+// Beginning of MG91:
+//
+#if (G92PL >= G91PL) || (G92PL == 0)
+#define MG91_12PL ~(1 << 1)
+#else
+#define MG91_12PL 0xFFFF
+#endif
+#if (G93PL >= G91PL) || (G93PL == 0)
+#define MG91_13PL ~(1 << 2)
+#else
+#define MG91_13PL 0xFFFF
+#endif
+#if (G94PL >= G91PL) || (G94PL == 0)
+#define MG91_14PL ~(1 << 3)
+#else
+#define MG91_14PL 0xFFFF
+#endif
+#if (G95PL >= G91PL) || (G95PL == 0)
+#define MG91_15PL ~(1 << 4)
+#else
+#define MG91_15PL 0xFFFF
+#endif
+#if (G96PL >= G91PL) || (G96PL == 0)
+#define MG91_16PL ~(1 << 5)
+#else
+#define MG91_16PL 0xFFFF
+#endif
+#if (G97PL >= G91PL) || (G97PL == 0)
+#define MG91_17PL ~(1 << 6)
+#else
+#define MG91_17PL 0xFFFF
+#endif
+#if (G98PL >= G91PL) || (G98PL == 0)
+#define MG91_18PL ~(1 << 7)
+#else
+#define MG91_18PL 0xFFFF
+#endif
+#define MG91_11PL 0x00FE
+#define MG91 (MG91_11PL & MG91_12PL & MG91_13PL & MG91_14PL & \
+ MG91_15PL & MG91_16PL & MG91_17PL & MG91_18PL)
+
+//
+// Beginning of MG92:
+//
+#if (G91PL >= G92PL) || (G91PL == 0)
+#define MG92_11PL ~(1)
+#else
+#define MG92_11PL 0xFFFF
+#endif
+#if (G93PL >= G92PL) || (G93PL == 0)
+#define MG92_13PL ~(1 << 2)
+#else
+#define MG92_13PL 0xFFFF
+#endif
+#if (G94PL >= G92PL) || (G94PL == 0)
+#define MG92_14PL ~(1 << 3)
+#else
+#define MG92_14PL 0xFFFF
+#endif
+#if (G95PL >= G92PL) || (G95PL == 0)
+#define MG92_15PL ~(1 << 4)
+#else
+#define MG92_15PL 0xFFFF
+#endif
+#if (G96PL >= G92PL) || (G96PL == 0)
+#define MG92_16PL ~(1 << 5)
+#else
+#define MG92_16PL 0xFFFF
+#endif
+#if (G97PL >= G92PL) || (G97PL == 0)
+#define MG92_17PL ~(1 << 6)
+#else
+#define MG92_17PL 0xFFFF
+#endif
+#if (G98PL >= G92PL) || (G98PL == 0)
+#define MG92_18PL ~(1 << 7)
+#else
+#define MG92_18PL 0xFFFF
+#endif
+#define MG92_12PL 0x00FD
+#define MG92 (MG92_11PL & MG92_12PL & MG92_13PL & MG92_14PL & \
+ MG92_15PL & MG92_16PL & MG92_17PL & MG92_18PL)
+
+//
+// Beginning of MG93:
+//
+#if (G91PL >= G93PL) || (G91PL == 0)
+#define MG93_11PL ~(1)
+#else
+#define MG93_11PL 0xFFFF
+#endif
+#if (G92PL >= G93PL) || (G92PL == 0)
+#define MG93_12PL ~(1 << 1)
+#else
+#define MG93_12PL 0xFFFF
+#endif
+#if (G94PL >= G93PL) || (G94PL == 0)
+#define MG93_14PL ~(1 << 3)
+#else
+#define MG93_14PL 0xFFFF
+#endif
+#if (G95PL >= G93PL) || (G95PL == 0)
+#define MG93_15PL ~(1 << 4)
+#else
+#define MG93_15PL 0xFFFF
+#endif
+#if (G96PL >= G93PL) || (G96PL == 0)
+#define MG93_16PL ~(1 << 5)
+#else
+#define MG93_16PL 0xFFFF
+#endif
+#if (G97PL >= G93PL) || (G97PL == 0)
+#define MG93_17PL ~(1 << 6)
+#else
+#define MG93_17PL 0xFFFF
+#endif
+#if (G98PL >= G93PL) || (G98PL == 0)
+#define MG93_18PL ~(1 << 7)
+#else
+#define MG93_18PL 0xFFFF
+#endif
+#define MG93_13PL 0x00FB
+#define MG93 (MG93_11PL & MG93_12PL & MG93_13PL & MG93_14PL & \
+ MG93_15PL & MG93_16PL & MG93_17PL & MG93_18PL)
+
+//
+// Beginning of MG94:
+//
+#if (G91PL >= G94PL) || (G91PL == 0)
+#define MG94_11PL ~(1)
+#else
+#define MG94_11PL 0xFFFF
+#endif
+#if (G92PL >= G94PL) || (G92PL == 0)
+#define MG94_12PL ~(1 << 1)
+#else
+#define MG94_12PL 0xFFFF
+#endif
+#if (G93PL >= G94PL) || (G93PL == 0)
+#define MG94_13PL ~(1 << 2)
+#else
+#define MG94_13PL 0xFFFF
+#endif
+#if (G95PL >= G94PL) || (G95PL == 0)
+#define MG94_15PL ~(1 << 4)
+#else
+#define MG94_15PL 0xFFFF
+#endif
+#if (G96PL >= G94PL) || (G96PL == 0)
+#define MG94_16PL ~(1 << 5)
+#else
+#define MG94_16PL 0xFFFF
+#endif
+#if (G97PL >= G94PL) || (G97PL == 0)
+#define MG94_17PL ~(1 << 6)
+#else
+#define MG94_17PL 0xFFFF
+#endif
+#if (G98PL >= G94PL) || (G98PL == 0)
+#define MG94_18PL ~(1 << 7)
+#else
+#define MG94_18PL 0xFFFF
+#endif
+#define MG94_14PL 0x00F7
+#define MG94 (MG94_11PL & MG94_12PL & MG94_13PL & MG94_14PL & \
+ MG94_15PL & MG94_16PL & MG94_17PL & MG94_18PL)
+
+//
+// Beginning of MG95:
+//
+#if (G91PL >= G95PL) || (G91PL == 0)
+#define MG95_11PL ~(1)
+#else
+#define MG95_11PL 0xFFFF
+#endif
+#if (G92PL >= G95PL) || (G92PL == 0)
+#define MG95_12PL ~(1 << 1)
+#else
+#define MG95_12PL 0xFFFF
+#endif
+#if (G93PL >= G95PL) || (G93PL == 0)
+#define MG95_13PL ~(1 << 2)
+#else
+#define MG95_13PL 0xFFFF
+#endif
+#if (G94PL >= G95PL) || (G94PL == 0)
+#define MG95_14PL ~(1 << 3)
+#else
+#define MG95_14PL 0xFFFF
+#endif
+#if (G96PL >= G95PL) || (G96PL == 0)
+#define MG95_16PL ~(1 << 5)
+#else
+#define MG95_16PL 0xFFFF
+#endif
+#if (G97PL >= G95PL) || (G97PL == 0)
+#define MG95_17PL ~(1 << 6)
+#else
+#define MG95_17PL 0xFFFF
+#endif
+#if (G98PL >= G95PL) || (G98PL == 0)
+#define MG95_18PL ~(1 << 7)
+#else
+#define MG95_18PL 0xFFFF
+#endif
+#define MG95_15PL 0x00EF
+#define MG95 (MG95_11PL & MG95_12PL & MG95_13PL & MG95_14PL & \
+ MG95_15PL & MG95_16PL & MG95_17PL & MG95_18PL)
+
+//
+// Beginning of MG96:
+//
+#if (G91PL >= G96PL) || (G91PL == 0)
+#define MG96_11PL ~(1)
+#else
+#define MG96_11PL 0xFFFF
+#endif
+#if (G92PL >= G96PL) || (G92PL == 0)
+#define MG96_12PL ~(1 << 1)
+#else
+#define MG96_12PL 0xFFFF
+#endif
+#if (G93PL >= G96PL) || (G93PL == 0)
+#define MG96_13PL ~(1 << 2)
+#else
+#define MG96_13PL 0xFFFF
+#endif
+#if (G94PL >= G96PL) || (G94PL == 0)
+#define MG96_14PL ~(1 << 3)
+#else
+#define MG96_14PL 0xFFFF
+#endif
+#if (G95PL >= G96PL) || (G95PL == 0)
+#define MG96_15PL ~(1 << 4)
+#else
+#define MG96_15PL 0xFFFF
+#endif
+#if (G97PL >= G96PL) || (G97PL == 0)
+#define MG96_17PL ~(1 << 6)
+#else
+#define MG96_17PL 0xFFFF
+#endif
+#if (G98PL >= G96PL) || (G98PL == 0)
+#define MG96_18PL ~(1 << 7)
+#else
+#define MG96_18PL 0xFFFF
+#endif
+#define MG96_16PL 0x00DF
+#define MG96 (MG96_11PL & MG96_12PL & MG96_13PL & MG96_14PL & \
+ MG96_15PL & MG96_16PL & MG96_17PL & MG96_18PL)
+
+//
+// Beginning of MG97:
+//
+#if (G91PL >= G97PL) || (G91PL == 0)
+#define MG97_11PL ~(1)
+#else
+#define MG97_11PL 0xFFFF
+#endif
+#if (G92PL >= G97PL) || (G92PL == 0)
+#define MG97_12PL ~(1 << 1)
+#else
+#define MG97_12PL 0xFFFF
+#endif
+#if (G93PL >= G97PL) || (G93PL == 0)
+#define MG97_13PL ~(1 << 2)
+#else
+#define MG97_13PL 0xFFFF
+#endif
+#if (G94PL >= G97PL) || (G94PL == 0)
+#define MG97_14PL ~(1 << 3)
+#else
+#define MG97_14PL 0xFFFF
+#endif
+#if (G95PL >= G97PL) || (G95PL == 0)
+#define MG97_15PL ~(1 << 4)
+#else
+#define MG97_15PL 0xFFFF
+#endif
+#if (G96PL >= G97PL) || (G96PL == 0)
+#define MG97_16PL ~(1 << 5)
+#else
+#define MG97_16PL 0xFFFF
+#endif
+#if (G98PL >= G97PL) || (G98PL == 0)
+#define MG97_18PL ~(1 << 7)
+#else
+#define MG97_18PL 0xFFFF
+#endif
+#define MG97_17PL 0x00BF
+#define MG97 (MG97_11PL & MG97_12PL & MG97_13PL & MG97_14PL & \
+ MG97_15PL & MG97_16PL & MG97_17PL & MG97_18PL)
+
+//
+// Beginning of MG98:
+//
+#if (G91PL >= G98PL) || (G91PL == 0)
+#define MG98_11PL ~(1)
+#else
+#define MG98_11PL 0xFFFF
+#endif
+#if (G92PL >= G98PL) || (G92PL == 0)
+#define MG98_12PL ~(1 << 1)
+#else
+#define MG98_12PL 0xFFFF
+#endif
+#if (G93PL >= G98PL) || (G93PL == 0)
+#define MG98_13PL ~(1 << 2)
+#else
+#define MG98_13PL 0xFFFF
+#endif
+#if (G94PL >= G98PL) || (G94PL == 0)
+#define MG98_14PL ~(1 << 3)
+#else
+#define MG98_14PL 0xFFFF
+#endif
+#if (G95PL >= G98PL) || (G95PL == 0)
+#define MG98_15PL ~(1 << 4)
+#else
+#define MG98_15PL 0xFFFF
+#endif
+#if (G96PL >= G98PL) || (G96PL == 0)
+#define MG98_16PL ~(1 << 5)
+#else
+#define MG98_16PL 0xFFFF
+#endif
+#if (G97PL >= G98PL) || (G97PL == 0)
+#define MG98_17PL ~(1 << 6)
+#else
+#define MG98_17PL 0xFFFF
+#endif
+#define MG98_18PL 0x007F
+#define MG98 (MG98_11PL & MG98_12PL & MG98_13PL & MG98_14PL & \
+ MG98_15PL & MG98_16PL & MG98_17PL & MG98_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG101 to MG108:
+//
+
+//
+// Beginning of MG101:
+//
+#if (G102PL >= G101PL) || (G102PL == 0)
+#define MG101_12PL ~(1 << 1)
+#else
+#define MG101_12PL 0xFFFF
+#endif
+#if (G103PL >= G101PL) || (G103PL == 0)
+#define MG101_13PL ~(1 << 2)
+#else
+#define MG101_13PL 0xFFFF
+#endif
+#if (G104PL >= G101PL) || (G104PL == 0)
+#define MG101_14PL ~(1 << 3)
+#else
+#define MG101_14PL 0xFFFF
+#endif
+#if (G105PL >= G101PL) || (G105PL == 0)
+#define MG101_15PL ~(1 << 4)
+#else
+#define MG101_15PL 0xFFFF
+#endif
+#if (G106PL >= G101PL) || (G106PL == 0)
+#define MG101_16PL ~(1 << 5)
+#else
+#define MG101_16PL 0xFFFF
+#endif
+#if (G107PL >= G101PL) || (G107PL == 0)
+#define MG101_17PL ~(1 << 6)
+#else
+#define MG101_17PL 0xFFFF
+#endif
+#if (G108PL >= G101PL) || (G108PL == 0)
+#define MG101_18PL ~(1 << 7)
+#else
+#define MG101_18PL 0xFFFF
+#endif
+#define MG101_11PL 0x00FE
+#define MG101 (MG101_11PL & MG101_12PL & MG101_13PL & MG101_14PL & \
+ MG101_15PL & MG101_16PL & MG101_17PL & MG101_18PL)
+
+//
+// Beginning of MG102:
+//
+#if (G101PL >= G102PL) || (G101PL == 0)
+#define MG102_11PL ~(1)
+#else
+#define MG102_11PL 0xFFFF
+#endif
+#if (G103PL >= G102PL) || (G103PL == 0)
+#define MG102_13PL ~(1 << 2)
+#else
+#define MG102_13PL 0xFFFF
+#endif
+#if (G104PL >= G102PL) || (G104PL == 0)
+#define MG102_14PL ~(1 << 3)
+#else
+#define MG102_14PL 0xFFFF
+#endif
+#if (G105PL >= G102PL) || (G105PL == 0)
+#define MG102_15PL ~(1 << 4)
+#else
+#define MG102_15PL 0xFFFF
+#endif
+#if (G106PL >= G102PL) || (G106PL == 0)
+#define MG102_16PL ~(1 << 5)
+#else
+#define MG102_16PL 0xFFFF
+#endif
+#if (G107PL >= G102PL) || (G107PL == 0)
+#define MG102_17PL ~(1 << 6)
+#else
+#define MG102_17PL 0xFFFF
+#endif
+#if (G108PL >= G102PL) || (G108PL == 0)
+#define MG102_18PL ~(1 << 7)
+#else
+#define MG102_18PL 0xFFFF
+#endif
+#define MG102_12PL 0x00FD
+#define MG102 (MG102_11PL & MG102_12PL & MG102_13PL & MG102_14PL & \
+ MG102_15PL & MG102_16PL & MG102_17PL & MG102_18PL)
+
+//
+// Beginning of MG103:
+//
+#if (G101PL >= G103PL) || (G101PL == 0)
+#define MG103_11PL ~(1)
+#else
+#define MG103_11PL 0xFFFF
+#endif
+#if (G102PL >= G103PL) || (G102PL == 0)
+#define MG103_12PL ~(1 << 1)
+#else
+#define MG103_12PL 0xFFFF
+#endif
+#if (G104PL >= G103PL) || (G104PL == 0)
+#define MG103_14PL ~(1 << 3)
+#else
+#define MG103_14PL 0xFFFF
+#endif
+#if (G105PL >= G103PL) || (G105PL == 0)
+#define MG103_15PL ~(1 << 4)
+#else
+#define MG103_15PL 0xFFFF
+#endif
+#if (G106PL >= G103PL) || (G106PL == 0)
+#define MG103_16PL ~(1 << 5)
+#else
+#define MG103_16PL 0xFFFF
+#endif
+#if (G107PL >= G103PL) || (G107PL == 0)
+#define MG103_17PL ~(1 << 6)
+#else
+#define MG103_17PL 0xFFFF
+#endif
+#if (G108PL >= G103PL) || (G108PL == 0)
+#define MG103_18PL ~(1 << 7)
+#else
+#define MG103_18PL 0xFFFF
+#endif
+#define MG103_13PL 0x00FB
+#define MG103 (MG103_11PL & MG103_12PL & MG103_13PL & MG103_14PL & \
+ MG103_15PL & MG103_16PL & MG103_17PL & MG103_18PL)
+
+//
+// Beginning of MG104:
+//
+#if (G101PL >= G104PL) || (G101PL == 0)
+#define MG104_11PL ~(1)
+#else
+#define MG104_11PL 0xFFFF
+#endif
+#if (G102PL >= G104PL) || (G102PL == 0)
+#define MG104_12PL ~(1 << 1)
+#else
+#define MG104_12PL 0xFFFF
+#endif
+#if (G103PL >= G104PL) || (G103PL == 0)
+#define MG104_13PL ~(1 << 2)
+#else
+#define MG104_13PL 0xFFFF
+#endif
+#if (G105PL >= G104PL) || (G105PL == 0)
+#define MG104_15PL ~(1 << 4)
+#else
+#define MG104_15PL 0xFFFF
+#endif
+#if (G106PL >= G104PL) || (G106PL == 0)
+#define MG104_16PL ~(1 << 5)
+#else
+#define MG104_16PL 0xFFFF
+#endif
+#if (G107PL >= G104PL) || (G107PL == 0)
+#define MG104_17PL ~(1 << 6)
+#else
+#define MG104_17PL 0xFFFF
+#endif
+#if (G108PL >= G104PL) || (G108PL == 0)
+#define MG104_18PL ~(1 << 7)
+#else
+#define MG104_18PL 0xFFFF
+#endif
+#define MG104_14PL 0x00F7
+#define MG104 (MG104_11PL & MG104_12PL & MG104_13PL & MG104_14PL & \
+ MG104_15PL & MG104_16PL & MG104_17PL & MG104_18PL)
+
+//
+// Beginning of MG105:
+//
+#if (G101PL >= G105PL) || (G101PL == 0)
+#define MG105_11PL ~(1)
+#else
+#define MG105_11PL 0xFFFF
+#endif
+#if (G102PL >= G105PL) || (G102PL == 0)
+#define MG105_12PL ~(1 << 1)
+#else
+#define MG105_12PL 0xFFFF
+#endif
+#if (G103PL >= G105PL) || (G103PL == 0)
+#define MG105_13PL ~(1 << 2)
+#else
+#define MG105_13PL 0xFFFF
+#endif
+#if (G104PL >= G105PL) || (G104PL == 0)
+#define MG105_14PL ~(1 << 3)
+#else
+#define MG105_14PL 0xFFFF
+#endif
+#if (G106PL >= G105PL) || (G106PL == 0)
+#define MG105_16PL ~(1 << 5)
+#else
+#define MG105_16PL 0xFFFF
+#endif
+#if (G107PL >= G105PL) || (G107PL == 0)
+#define MG105_17PL ~(1 << 6)
+#else
+#define MG105_17PL 0xFFFF
+#endif
+#if (G108PL >= G105PL) || (G108PL == 0)
+#define MG105_18PL ~(1 << 7)
+#else
+#define MG105_18PL 0xFFFF
+#endif
+#define MG105_15PL 0x00EF
+#define MG105 (MG105_11PL & MG105_12PL & MG105_13PL & MG105_14PL & \
+ MG105_15PL & MG105_16PL & MG105_17PL & MG105_18PL)
+
+//
+// Beginning of MG106:
+//
+#if (G101PL >= G106PL) || (G101PL == 0)
+#define MG106_11PL ~(1)
+#else
+#define MG106_11PL 0xFFFF
+#endif
+#if (G102PL >= G106PL) || (G102PL == 0)
+#define MG106_12PL ~(1 << 1)
+#else
+#define MG106_12PL 0xFFFF
+#endif
+#if (G103PL >= G106PL) || (G103PL == 0)
+#define MG106_13PL ~(1 << 2)
+#else
+#define MG106_13PL 0xFFFF
+#endif
+#if (G104PL >= G106PL) || (G104PL == 0)
+#define MG106_14PL ~(1 << 3)
+#else
+#define MG106_14PL 0xFFFF
+#endif
+#if (G105PL >= G106PL) || (G105PL == 0)
+#define MG106_15PL ~(1 << 4)
+#else
+#define MG106_15PL 0xFFFF
+#endif
+#if (G107PL >= G106PL) || (G107PL == 0)
+#define MG106_17PL ~(1 << 6)
+#else
+#define MG106_17PL 0xFFFF
+#endif
+#if (G108PL >= G106PL) || (G108PL == 0)
+#define MG106_18PL ~(1 << 7)
+#else
+#define MG106_18PL 0xFFFF
+#endif
+#define MG106_16PL 0x00DF
+#define MG106 (MG106_11PL & MG106_12PL & MG106_13PL & MG106_14PL & \
+ MG106_15PL & MG106_16PL & MG106_17PL & MG106_18PL)
+
+//
+// Beginning of MG107:
+//
+#if (G101PL >= G107PL) || (G101PL == 0)
+#define MG107_11PL ~(1)
+#else
+#define MG107_11PL 0xFFFF
+#endif
+#if (G102PL >= G107PL) || (G102PL == 0)
+#define MG107_12PL ~(1 << 1)
+#else
+#define MG107_12PL 0xFFFF
+#endif
+#if (G103PL >= G107PL) || (G103PL == 0)
+#define MG107_13PL ~(1 << 2)
+#else
+#define MG107_13PL 0xFFFF
+#endif
+#if (G104PL >= G107PL) || (G104PL == 0)
+#define MG107_14PL ~(1 << 3)
+#else
+#define MG107_14PL 0xFFFF
+#endif
+#if (G105PL >= G107PL) || (G105PL == 0)
+#define MG107_15PL ~(1 << 4)
+#else
+#define MG107_15PL 0xFFFF
+#endif
+#if (G106PL >= G107PL) || (G106PL == 0)
+#define MG107_16PL ~(1 << 5)
+#else
+#define MG107_16PL 0xFFFF
+#endif
+#if (G108PL >= G107PL) || (G108PL == 0)
+#define MG107_18PL ~(1 << 7)
+#else
+#define MG107_18PL 0xFFFF
+#endif
+#define MG107_17PL 0x00BF
+#define MG107 (MG107_11PL & MG107_12PL & MG107_13PL & MG107_14PL & \
+ MG107_15PL & MG107_16PL & MG107_17PL & MG107_18PL)
+
+//
+// Beginning of MG108:
+//
+#if (G101PL >= G108PL) || (G101PL == 0)
+#define MG108_11PL ~(1)
+#else
+#define MG108_11PL 0xFFFF
+#endif
+#if (G102PL >= G108PL) || (G102PL == 0)
+#define MG108_12PL ~(1 << 1)
+#else
+#define MG108_12PL 0xFFFF
+#endif
+#if (G103PL >= G108PL) || (G103PL == 0)
+#define MG108_13PL ~(1 << 2)
+#else
+#define MG108_13PL 0xFFFF
+#endif
+#if (G104PL >= G108PL) || (G104PL == 0)
+#define MG108_14PL ~(1 << 3)
+#else
+#define MG108_14PL 0xFFFF
+#endif
+#if (G105PL >= G108PL) || (G105PL == 0)
+#define MG108_15PL ~(1 << 4)
+#else
+#define MG108_15PL 0xFFFF
+#endif
+#if (G106PL >= G108PL) || (G106PL == 0)
+#define MG108_16PL ~(1 << 5)
+#else
+#define MG108_16PL 0xFFFF
+#endif
+#if (G107PL >= G108PL) || (G107PL == 0)
+#define MG108_17PL ~(1 << 6)
+#else
+#define MG108_17PL 0xFFFF
+#endif
+#define MG108_18PL 0x007F
+#define MG108 (MG108_11PL & MG108_12PL & MG108_13PL & MG108_14PL & \
+ MG108_15PL & MG108_16PL & MG108_17PL & MG108_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG111 to MG118:
+//
+
+//
+// Beginning of MG111:
+//
+#if (G112PL >= G111PL) || (G112PL == 0)
+#define MG111_12PL ~(1 << 1)
+#else
+#define MG111_12PL 0xFFFF
+#endif
+#if (G113PL >= G111PL) || (G113PL == 0)
+#define MG111_13PL ~(1 << 2)
+#else
+#define MG111_13PL 0xFFFF
+#endif
+#if (G114PL >= G111PL) || (G114PL == 0)
+#define MG111_14PL ~(1 << 3)
+#else
+#define MG111_14PL 0xFFFF
+#endif
+#if (G115PL >= G111PL) || (G115PL == 0)
+#define MG111_15PL ~(1 << 4)
+#else
+#define MG111_15PL 0xFFFF
+#endif
+#if (G116PL >= G111PL) || (G116PL == 0)
+#define MG111_16PL ~(1 << 5)
+#else
+#define MG111_16PL 0xFFFF
+#endif
+#if (G117PL >= G111PL) || (G117PL == 0)
+#define MG111_17PL ~(1 << 6)
+#else
+#define MG111_17PL 0xFFFF
+#endif
+#if (G118PL >= G111PL) || (G118PL == 0)
+#define MG111_18PL ~(1 << 7)
+#else
+#define MG111_18PL 0xFFFF
+#endif
+#define MG111_11PL 0x00FE
+#define MG111 (MG111_11PL & MG111_12PL & MG111_13PL & MG111_14PL & \
+ MG111_15PL & MG111_16PL & MG111_17PL & MG111_18PL)
+
+//
+// Beginning of MG112:
+//
+#if (G111PL >= G112PL) || (G111PL == 0)
+#define MG112_11PL ~(1)
+#else
+#define MG112_11PL 0xFFFF
+#endif
+#if (G113PL >= G112PL) || (G113PL == 0)
+#define MG112_13PL ~(1 << 2)
+#else
+#define MG112_13PL 0xFFFF
+#endif
+#if (G114PL >= G112PL) || (G114PL == 0)
+#define MG112_14PL ~(1 << 3)
+#else
+#define MG112_14PL 0xFFFF
+#endif
+#if (G115PL >= G112PL) || (G115PL == 0)
+#define MG112_15PL ~(1 << 4)
+#else
+#define MG112_15PL 0xFFFF
+#endif
+#if (G116PL >= G112PL) || (G116PL == 0)
+#define MG112_16PL ~(1 << 5)
+#else
+#define MG112_16PL 0xFFFF
+#endif
+#if (G117PL >= G112PL) || (G117PL == 0)
+#define MG112_17PL ~(1 << 6)
+#else
+#define MG112_17PL 0xFFFF
+#endif
+#if (G118PL >= G112PL) || (G118PL == 0)
+#define MG112_18PL ~(1 << 7)
+#else
+#define MG112_18PL 0xFFFF
+#endif
+#define MG112_12PL 0x00FD
+#define MG112 (MG112_11PL & MG112_12PL & MG112_13PL & MG112_14PL & \
+ MG112_15PL & MG112_16PL & MG112_17PL & MG112_18PL)
+
+//
+// Beginning of MG113:
+//
+#if (G111PL >= G113PL) || (G111PL == 0)
+#define MG113_11PL ~(1)
+#else
+#define MG113_11PL 0xFFFF
+#endif
+#if (G112PL >= G113PL) || (G112PL == 0)
+#define MG113_12PL ~(1 << 1)
+#else
+#define MG113_12PL 0xFFFF
+#endif
+#if (G114PL >= G113PL) || (G114PL == 0)
+#define MG113_14PL ~(1 << 3)
+#else
+#define MG113_14PL 0xFFFF
+#endif
+#if (G115PL >= G113PL) || (G115PL == 0)
+#define MG113_15PL ~(1 << 4)
+#else
+#define MG113_15PL 0xFFFF
+#endif
+#if (G116PL >= G113PL) || (G116PL == 0)
+#define MG113_16PL ~(1 << 5)
+#else
+#define MG113_16PL 0xFFFF
+#endif
+#if (G117PL >= G113PL) || (G117PL == 0)
+#define MG113_17PL ~(1 << 6)
+#else
+#define MG113_17PL 0xFFFF
+#endif
+#if (G118PL >= G113PL) || (G118PL == 0)
+#define MG113_18PL ~(1 << 7)
+#else
+#define MG113_18PL 0xFFFF
+#endif
+#define MG113_13PL 0x00FB
+#define MG113 (MG113_11PL & MG113_12PL & MG113_13PL & MG113_14PL & \
+ MG113_15PL & MG113_16PL & MG113_17PL & MG113_18PL)
+
+//
+// Beginning of MG114:
+//
+#if (G111PL >= G114PL) || (G111PL == 0)
+#define MG114_11PL ~(1)
+#else
+#define MG114_11PL 0xFFFF
+#endif
+#if (G112PL >= G114PL) || (G112PL == 0)
+#define MG114_12PL ~(1 << 1)
+#else
+#define MG114_12PL 0xFFFF
+#endif
+#if (G113PL >= G114PL) || (G113PL == 0)
+#define MG114_13PL ~(1 << 2)
+#else
+#define MG114_13PL 0xFFFF
+#endif
+#if (G115PL >= G114PL) || (G115PL == 0)
+#define MG114_15PL ~(1 << 4)
+#else
+#define MG114_15PL 0xFFFF
+#endif
+#if (G116PL >= G114PL) || (G116PL == 0)
+#define MG114_16PL ~(1 << 5)
+#else
+#define MG114_16PL 0xFFFF
+#endif
+#if (G117PL >= G114PL) || (G117PL == 0)
+#define MG114_17PL ~(1 << 6)
+#else
+#define MG114_17PL 0xFFFF
+#endif
+#if (G118PL >= G114PL) || (G118PL == 0)
+#define MG114_18PL ~(1 << 7)
+#else
+#define MG114_18PL 0xFFFF
+#endif
+#define MG114_14PL 0x00F7
+#define MG114 (MG114_11PL & MG114_12PL & MG114_13PL & MG114_14PL & \
+ MG114_15PL & MG114_16PL & MG114_17PL & MG114_18PL)
+
+//
+// Beginning of MG115:
+//
+#if (G111PL >= G115PL) || (G111PL == 0)
+#define MG115_11PL ~(1)
+#else
+#define MG115_11PL 0xFFFF
+#endif
+#if (G112PL >= G115PL) || (G112PL == 0)
+#define MG115_12PL ~(1 << 1)
+#else
+#define MG115_12PL 0xFFFF
+#endif
+#if (G113PL >= G115PL) || (G113PL == 0)
+#define MG115_13PL ~(1 << 2)
+#else
+#define MG115_13PL 0xFFFF
+#endif
+#if (G114PL >= G115PL) || (G114PL == 0)
+#define MG115_14PL ~(1 << 3)
+#else
+#define MG115_14PL 0xFFFF
+#endif
+#if (G116PL >= G115PL) || (G116PL == 0)
+#define MG115_16PL ~(1 << 5)
+#else
+#define MG115_16PL 0xFFFF
+#endif
+#if (G117PL >= G115PL) || (G117PL == 0)
+#define MG115_17PL ~(1 << 6)
+#else
+#define MG115_17PL 0xFFFF
+#endif
+#if (G118PL >= G115PL) || (G118PL == 0)
+#define MG115_18PL ~(1 << 7)
+#else
+#define MG115_18PL 0xFFFF
+#endif
+#define MG115_15PL 0x00EF
+#define MG115 (MG115_11PL & MG115_12PL & MG115_13PL & MG115_14PL & \
+ MG115_15PL & MG115_16PL & MG115_17PL & MG115_18PL)
+
+//
+// Beginning of MG116:
+//
+#if (G111PL >= G116PL) || (G111PL == 0)
+#define MG116_11PL ~(1)
+#else
+#define MG116_11PL 0xFFFF
+#endif
+#if (G112PL >= G116PL) || (G112PL == 0)
+#define MG116_12PL ~(1 << 1)
+#else
+#define MG116_12PL 0xFFFF
+#endif
+#if (G113PL >= G116PL) || (G113PL == 0)
+#define MG116_13PL ~(1 << 2)
+#else
+#define MG116_13PL 0xFFFF
+#endif
+#if (G114PL >= G116PL) || (G114PL == 0)
+#define MG116_14PL ~(1 << 3)
+#else
+#define MG116_14PL 0xFFFF
+#endif
+#if (G115PL >= G116PL) || (G115PL == 0)
+#define MG116_15PL ~(1 << 4)
+#else
+#define MG116_15PL 0xFFFF
+#endif
+#if (G117PL >= G116PL) || (G117PL == 0)
+#define MG116_17PL ~(1 << 6)
+#else
+#define MG116_17PL 0xFFFF
+#endif
+#if (G118PL >= G116PL) || (G118PL == 0)
+#define MG116_18PL ~(1 << 7)
+#else
+#define MG116_18PL 0xFFFF
+#endif
+#define MG116_16PL 0x00DF
+#define MG116 (MG116_11PL & MG116_12PL & MG116_13PL & MG116_14PL & \
+ MG116_15PL & MG116_16PL & MG116_17PL & MG116_18PL)
+
+//
+// Beginning of MG117:
+//
+#if (G111PL >= G117PL) || (G111PL == 0)
+#define MG117_11PL ~(1)
+#else
+#define MG117_11PL 0xFFFF
+#endif
+#if (G112PL >= G117PL) || (G112PL == 0)
+#define MG117_12PL ~(1 << 1)
+#else
+#define MG117_12PL 0xFFFF
+#endif
+#if (G113PL >= G117PL) || (G113PL == 0)
+#define MG117_13PL ~(1 << 2)
+#else
+#define MG117_13PL 0xFFFF
+#endif
+#if (G114PL >= G117PL) || (G114PL == 0)
+#define MG117_14PL ~(1 << 3)
+#else
+#define MG117_14PL 0xFFFF
+#endif
+#if (G115PL >= G117PL) || (G115PL == 0)
+#define MG117_15PL ~(1 << 4)
+#else
+#define MG117_15PL 0xFFFF
+#endif
+#if (G116PL >= G117PL) || (G116PL == 0)
+#define MG117_16PL ~(1 << 5)
+#else
+#define MG117_16PL 0xFFFF
+#endif
+#if (G118PL >= G117PL) || (G118PL == 0)
+#define MG117_18PL ~(1 << 7)
+#else
+#define MG117_18PL 0xFFFF
+#endif
+#define MG117_17PL 0x00BF
+#define MG117 (MG117_11PL & MG117_12PL & MG117_13PL & MG117_14PL & \
+ MG117_15PL & MG117_16PL & MG117_17PL & MG117_18PL)
+
+//
+// Beginning of MG118:
+//
+#if (G111PL >= G118PL) || (G111PL == 0)
+#define MG118_11PL ~(1)
+#else
+#define MG118_11PL 0xFFFF
+#endif
+#if (G112PL >= G118PL) || (G112PL == 0)
+#define MG118_12PL ~(1 << 1)
+#else
+#define MG118_12PL 0xFFFF
+#endif
+#if (G113PL >= G118PL) || (G113PL == 0)
+#define MG118_13PL ~(1 << 2)
+#else
+#define MG118_13PL 0xFFFF
+#endif
+#if (G114PL >= G118PL) || (G114PL == 0)
+#define MG118_14PL ~(1 << 3)
+#else
+#define MG118_14PL 0xFFFF
+#endif
+#if (G115PL >= G118PL) || (G115PL == 0)
+#define MG118_15PL ~(1 << 4)
+#else
+#define MG118_15PL 0xFFFF
+#endif
+#if (G116PL >= G118PL) || (G116PL == 0)
+#define MG118_16PL ~(1 << 5)
+#else
+#define MG118_16PL 0xFFFF
+#endif
+#if (G117PL >= G118PL) || (G117PL == 0)
+#define MG118_17PL ~(1 << 6)
+#else
+#define MG118_17PL 0xFFFF
+#endif
+#define MG118_18PL 0x007F
+#define MG118 (MG118_11PL & MG118_12PL & MG118_13PL & MG118_14PL & \
+ MG118_15PL & MG118_16PL & MG118_17PL & MG118_18PL)
+
+//
+// Automatically generate PIEIER1 interrupt masks MG121 to MG128:
+//
+
+//
+// Beginning of MG121:
+//
+#if (G122PL >= G121PL) || (G122PL == 0)
+#define MG121_12PL ~(1 << 1)
+#else
+#define MG121_12PL 0xFFFF
+#endif
+#if (G123PL >= G121PL) || (G123PL == 0)
+#define MG121_13PL ~(1 << 2)
+#else
+#define MG121_13PL 0xFFFF
+#endif
+#if (G124PL >= G121PL) || (G124PL == 0)
+#define MG121_14PL ~(1 << 3)
+#else
+#define MG121_14PL 0xFFFF
+#endif
+#if (G125PL >= G121PL) || (G125PL == 0)
+#define MG121_15PL ~(1 << 4)
+#else
+#define MG121_15PL 0xFFFF
+#endif
+#if (G126PL >= G121PL) || (G126PL == 0)
+#define MG121_16PL ~(1 << 5)
+#else
+#define MG121_16PL 0xFFFF
+#endif
+#if (G127PL >= G121PL) || (G127PL == 0)
+#define MG121_17PL ~(1 << 6)
+#else
+#define MG121_17PL 0xFFFF
+#endif
+#if (G128PL >= G121PL) || (G128PL == 0)
+#define MG121_18PL ~(1 << 7)
+#else
+#define MG121_18PL 0xFFFF
+#endif
+#define MG121_11PL 0x00FE
+#define MG121 (MG121_11PL & MG121_12PL & MG121_13PL & MG121_14PL & \
+ MG121_15PL & MG121_16PL & MG121_17PL & MG121_18PL)
+
+//
+// Beginning of MG121:
+//
+#if (G121PL >= G122PL) || (G121PL == 0)
+#define MG122_11PL ~(1)
+#else
+#define MG122_11PL 0xFFFF
+#endif
+#if (G123PL >= G122PL) || (G123PL == 0)
+#define MG122_13PL ~(1 << 2)
+#else
+#define MG122_13PL 0xFFFF
+#endif
+#if (G124PL >= G122PL) || (G124PL == 0)
+#define MG122_14PL ~(1 << 3)
+#else
+#define MG122_14PL 0xFFFF
+#endif
+#if (G125PL >= G122PL) || (G125PL == 0)
+#define MG122_15PL ~(1 << 4)
+#else
+#define MG122_15PL 0xFFFF
+#endif
+#if (G126PL >= G122PL) || (G126PL == 0)
+#define MG122_16PL ~(1 << 5)
+#else
+#define MG122_16PL 0xFFFF
+#endif
+#if (G127PL >= G122PL) || (G127PL == 0)
+#define MG122_17PL ~(1 << 6)
+#else
+#define MG122_17PL 0xFFFF
+#endif
+#if (G128PL >= G122PL) || (G128PL == 0)
+#define MG122_18PL ~(1 << 7)
+#else
+#define MG122_18PL 0xFFFF
+#endif
+#define MG122_12PL 0x00FD
+#define MG122 (MG122_11PL & MG122_12PL & MG122_13PL & MG122_14PL & \
+ MG122_15PL & MG122_16PL & MG122_17PL & MG122_18PL)
+
+//
+// Beginning of MG123:
+//
+#if (G121PL >= G123PL) || (G121PL == 0)
+#define MG123_11PL ~(1)
+#else
+#define MG123_11PL 0xFFFF
+#endif
+#if (G122PL >= G123PL) || (G122PL == 0)
+#define MG123_12PL ~(1 << 1)
+#else
+#define MG123_12PL 0xFFFF
+#endif
+#if (G124PL >= G123PL) || (G124PL == 0)
+#define MG123_14PL ~(1 << 3)
+#else
+#define MG123_14PL 0xFFFF
+#endif
+#if (G125PL >= G123PL) || (G125PL == 0)
+#define MG123_15PL ~(1 << 4)
+#else
+#define MG123_15PL 0xFFFF
+#endif
+#if (G126PL >= G123PL) || (G126PL == 0)
+#define MG123_16PL ~(1 << 5)
+#else
+#define MG123_16PL 0xFFFF
+#endif
+#if (G127PL >= G123PL) || (G127PL == 0)
+#define MG123_17PL ~(1 << 6)
+#else
+#define MG123_17PL 0xFFFF
+#endif
+#if (G128PL >= G123PL) || (G128PL == 0)
+#define MG123_18PL ~(1 << 7)
+#else
+#define MG123_18PL 0xFFFF
+#endif
+#define MG123_13PL 0x00FB
+#define MG123 (MG123_11PL & MG123_12PL & MG123_13PL & MG123_14PL & \
+ MG123_15PL & MG123_16PL & MG123_17PL & MG123_18PL)
+
+//
+// Beginning of MG124:
+//
+#if (G121PL >= G124PL) || (G121PL == 0)
+#define MG124_11PL ~(1)
+#else
+#define MG124_11PL 0xFFFF
+#endif
+#if (G122PL >= G124PL) || (G122PL == 0)
+#define MG124_12PL ~(1 << 1)
+#else
+#define MG124_12PL 0xFFFF
+#endif
+#if (G123PL >= G124PL) || (G123PL == 0)
+#define MG124_13PL ~(1 << 2)
+#else
+#define MG124_13PL 0xFFFF
+#endif
+#if (G125PL >= G124PL) || (G125PL == 0)
+#define MG124_15PL ~(1 << 4)
+#else
+#define MG124_15PL 0xFFFF
+#endif
+#if (G126PL >= G124PL) || (G126PL == 0)
+#define MG124_16PL ~(1 << 5)
+#else
+#define MG124_16PL 0xFFFF
+#endif
+#if (G127PL >= G124PL) || (G127PL == 0)
+#define MG124_17PL ~(1 << 6)
+#else
+#define MG124_17PL 0xFFFF
+#endif
+#if (G128PL >= G124PL) || (G128PL == 0)
+#define MG124_18PL ~(1 << 7)
+#else
+#define MG124_18PL 0xFFFF
+#endif
+#define MG124_14PL 0x00F7
+#define MG124 (MG124_11PL & MG124_12PL & MG124_13PL & MG124_14PL & \
+ MG124_15PL & MG124_16PL & MG124_17PL & MG124_18PL)
+
+//
+// Beginning of MG125:
+//
+#if (G121PL >= G125PL) || (G121PL == 0)
+#define MG125_11PL ~(1)
+#else
+#define MG125_11PL 0xFFFF
+#endif
+#if (G122PL >= G125PL) || (G122PL == 0)
+#define MG125_12PL ~(1 << 1)
+#else
+#define MG125_12PL 0xFFFF
+#endif
+#if (G123PL >= G125PL) || (G123PL == 0)
+#define MG125_13PL ~(1 << 2)
+#else
+#define MG125_13PL 0xFFFF
+#endif
+#if (G124PL >= G125PL) || (G124PL == 0)
+#define MG125_14PL ~(1 << 3)
+#else
+#define MG125_14PL 0xFFFF
+#endif
+#if (G126PL >= G125PL) || (G126PL == 0)
+#define MG125_16PL ~(1 << 5)
+#else
+#define MG125_16PL 0xFFFF
+#endif
+#if (G127PL >= G125PL) || (G127PL == 0)
+#define MG125_17PL ~(1 << 6)
+#else
+#define MG125_17PL 0xFFFF
+#endif
+#if (G128PL >= G125PL) || (G128PL == 0)
+#define MG125_18PL ~(1 << 7)
+#else
+#define MG125_18PL 0xFFFF
+#endif
+#define MG125_15PL 0x00EF
+#define MG125 (MG125_11PL & MG125_12PL & MG125_13PL & MG125_14PL & \
+ MG125_15PL & MG125_16PL & MG125_17PL & MG125_18PL)
+
+//
+// Beginning of MG126:
+//
+#if (G121PL >= G126PL) || (G121PL == 0)
+#define MG126_11PL ~(1)
+#else
+#define MG126_11PL 0xFFFF
+#endif
+#if (G122PL >= G126PL) || (G122PL == 0)
+#define MG126_12PL ~(1 << 1)
+#else
+#define MG126_12PL 0xFFFF
+#endif
+#if (G123PL >= G126PL) || (G123PL == 0)
+#define MG126_13PL ~(1 << 2)
+#else
+#define MG126_13PL 0xFFFF
+#endif
+#if (G124PL >= G126PL) || (G124PL == 0)
+#define MG126_14PL ~(1 << 3)
+#else
+#define MG126_14PL 0xFFFF
+#endif
+#if (G125PL >= G126PL) || (G125PL == 0)
+#define MG126_15PL ~(1 << 4)
+#else
+#define MG126_15PL 0xFFFF
+#endif
+#if (G127PL >= G126PL) || (G127PL == 0)
+#define MG126_17PL ~(1 << 6)
+#else
+#define MG126_17PL 0xFFFF
+#endif
+#if (G128PL >= G126PL) || (G128PL == 0)
+#define MG126_18PL ~(1 << 7)
+#else
+#define MG126_18PL 0xFFFF
+#endif
+#define MG126_16PL 0x00DF
+#define MG126 (MG126_11PL & MG126_12PL & MG126_13PL & MG126_14PL & \
+ MG126_15PL & MG126_16PL & MG126_17PL & MG126_18PL)
+
+//
+// Beginning of MG127:
+//
+#if (G121PL >= G127PL) || (G121PL == 0)
+#define MG127_11PL ~(1)
+#else
+#define MG127_11PL 0xFFFF
+#endif
+#if (G122PL >= G127PL) || (G122PL == 0)
+#define MG127_12PL ~(1 << 1)
+#else
+#define MG127_12PL 0xFFFF
+#endif
+#if (G123PL >= G127PL) || (G123PL == 0)
+#define MG127_13PL ~(1 << 2)
+#else
+#define MG127_13PL 0xFFFF
+#endif
+#if (G124PL >= G127PL) || (G124PL == 0)
+#define MG127_14PL ~(1 << 3)
+#else
+#define MG127_14PL 0xFFFF
+#endif
+#if (G125PL >= G127PL) || (G125PL == 0)
+#define MG127_15PL ~(1 << 4)
+#else
+#define MG127_15PL 0xFFFF
+#endif
+#if (G126PL >= G127PL) || (G126PL == 0)
+#define MG127_16PL ~(1 << 5)
+#else
+#define MG127_16PL 0xFFFF
+#endif
+#if (G128PL >= G127PL) || (G128PL == 0)
+#define MG127_18PL ~(1 << 7)
+#else
+#define MG127_18PL 0xFFFF
+#endif
+#define MG127_17PL 0x00BF
+#define MG127 (MG127_11PL & MG127_12PL & MG127_13PL & MG127_14PL & \
+ MG127_15PL & MG127_16PL & MG127_17PL & MG127_18PL)
+
+//
+// Beginning of MG128:
+//
+#if (G121PL >= G128PL) || (G121PL == 0)
+#define MG128_11PL ~(1)
+#else
+#define MG128_11PL 0xFFFF
+#endif
+#if (G122PL >= G128PL) || (G122PL == 0)
+#define MG128_12PL ~(1 << 1)
+#else
+#define MG128_12PL 0xFFFF
+#endif
+#if (G123PL >= G128PL) || (G123PL == 0)
+#define MG128_13PL ~(1 << 2)
+#else
+#define MG128_13PL 0xFFFF
+#endif
+#if (G124PL >= G128PL) || (G124PL == 0)
+#define MG128_14PL ~(1 << 3)
+#else
+#define MG128_14PL 0xFFFF
+#endif
+#if (G125PL >= G128PL) || (G125PL == 0)
+#define MG128_15PL ~(1 << 4)
+#else
+#define MG128_15PL 0xFFFF
+#endif
+#if (G126PL >= G128PL) || (G126PL == 0)
+#define MG128_16PL ~(1 << 5)
+#else
+#define MG128_16PL 0xFFFF
+#endif
+#if (G127PL >= G128PL) || (G127PL == 0)
+#define MG128_17PL ~(1 << 6)
+#else
+#define MG128_17PL 0xFFFF
+#endif
+#define MG128_18PL 0x007F
+#define MG128 (MG128_11PL & MG128_12PL & MG128_13PL & MG128_14PL & \
+ MG128_15PL & MG128_16PL & MG128_17PL & MG128_18PL)
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // eof
+
+//
+// End of File
+//
+
diff --git a/bsp/include/DSP2833x_Sci.h b/bsp/include/DSP2833x_Sci.h
new file mode 100644
index 0000000..4cd3ca4
--- /dev/null
+++ b/bsp/include/DSP2833x_Sci.h
@@ -0,0 +1,251 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 1, 2007 15:57:02 $
+//###########################################################################
+//
+// FILE: DSP2833x_Sci.h
+//
+// TITLE: DSP2833x Device SCI Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_SCI_H
+#define DSP2833x_SCI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// SCI Individual Register Bit Definitions
+//
+
+//
+// SCICCR communication control register bit definitions
+//
+struct SCICCR_BITS { // bit description
+ Uint16 SCICHAR:3; // 2:0 Character length control
+ Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
+ Uint16 LOOPBKENA:1; // 4 Loop Back enable
+ Uint16 PARITYENA:1; // 5 Parity enable
+ Uint16 PARITY:1; // 6 Even or Odd Parity
+ Uint16 STOPBITS:1; // 7 Number of Stop Bits
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union SCICCR_REG {
+ Uint16 all;
+ struct SCICCR_BITS bit;
+};
+
+//
+// SCICTL1 control register 1 bit definitions
+//
+struct SCICTL1_BITS { // bit description
+ Uint16 RXENA:1; // 0 SCI receiver enable
+ Uint16 TXENA:1; // 1 SCI transmitter enable
+ Uint16 SLEEP:1; // 2 SCI sleep
+ Uint16 TXWAKE:1; // 3 Transmitter wakeup method
+ Uint16 rsvd:1; // 4 reserved
+ Uint16 SWRESET:1; // 5 Software reset
+ Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
+ Uint16 rsvd1:9; // 15:7 reserved
+};
+
+union SCICTL1_REG {
+ Uint16 all;
+ struct SCICTL1_BITS bit;
+};
+
+//
+// SCICTL2 control register 2 bit definitions
+//
+struct SCICTL2_BITS { // bit description
+ Uint16 TXINTENA:1; // 0 Transmit interrupt enable
+ Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
+ Uint16 rsvd:4; // 5:2 reserved
+ Uint16 TXEMPTY:1; // 6 Transmitter empty flag
+ Uint16 TXRDY:1; // 7 Transmitter ready flag
+ Uint16 rsvd1:8; // 15:8 reserved
+};
+
+union SCICTL2_REG {
+ Uint16 all;
+ struct SCICTL2_BITS bit;
+};
+
+//
+// SCIRXST Receiver status register bit definitions
+//
+struct SCIRXST_BITS { // bit description
+ Uint16 rsvd:1; // 0 reserved
+ Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
+ Uint16 PE:1; // 2 Parity error flag
+ Uint16 OE:1; // 3 Overrun error flag
+ Uint16 FE:1; // 4 Framing error flag
+ Uint16 BRKDT:1; // 5 Break-detect flag
+ Uint16 RXRDY:1; // 6 Receiver ready flag
+ Uint16 RXERROR:1; // 7 Receiver error flag
+};
+
+union SCIRXST_REG {
+ Uint16 all;
+ struct SCIRXST_BITS bit;
+};
+
+//
+// SCIRXBUF Receiver Data Buffer with FIFO bit definitions
+//
+struct SCIRXBUF_BITS { // bits description
+ Uint16 RXDT:8; // 7:0 Receive word
+ Uint16 rsvd:6; // 13:8 reserved
+ Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
+ Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
+};
+
+union SCIRXBUF_REG {
+ Uint16 all;
+ struct SCIRXBUF_BITS bit;
+};
+
+//
+// SCIPRI Priority control register bit definitions
+//
+struct SCIPRI_BITS { // bit description
+ Uint16 rsvd:3; // 2:0 reserved
+ Uint16 FREE:1; // 3 Free emulation suspend mode
+ Uint16 SOFT:1; // 4 Soft emulation suspend mode
+ Uint16 rsvd1:3; // 7:5 reserved
+};
+
+union SCIPRI_REG {
+ Uint16 all;
+ struct SCIPRI_BITS bit;
+};
+
+//
+// SCI FIFO Transmit register bit definitions
+//
+struct SCIFFTX_BITS { // bit description
+ Uint16 TXFFIL:5; // 4:0 Interrupt level
+ Uint16 TXFFIENA:1; // 5 Interrupt enable
+ Uint16 TXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 TXFFINT:1; // 7 INT flag
+ Uint16 TXFFST:5; // 12:8 FIFO status
+ Uint16 TXFIFOXRESET:1; // 13 FIFO reset
+ Uint16 SCIFFENA:1; // 14 Enhancement enable
+ Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
+};
+
+union SCIFFTX_REG {
+ Uint16 all;
+ struct SCIFFTX_BITS bit;
+};
+
+//
+// SCI FIFO recieve register bit definitions
+//
+struct SCIFFRX_BITS { // bits description
+ Uint16 RXFFIL:5; // 4:0 Interrupt level
+ Uint16 RXFFIENA:1; // 5 Interrupt enable
+ Uint16 RXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 RXFFINT:1; // 7 INT flag
+ Uint16 RXFFST:5; // 12:8 FIFO status
+ Uint16 RXFIFORESET:1; // 13 FIFO reset
+ Uint16 RXFFOVRCLR:1; // 14 Clear overflow
+ Uint16 RXFFOVF:1; // 15 FIFO overflow
+};
+
+union SCIFFRX_REG {
+ Uint16 all;
+ struct SCIFFRX_BITS bit;
+};
+
+//
+// SCI FIFO control register bit definitions
+//
+struct SCIFFCT_BITS { // bits description
+ Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
+ Uint16 rsvd:5; // 12:8 reserved
+ Uint16 CDC:1; // 13 Auto baud mode enable
+ Uint16 ABDCLR:1; // 14 Auto baud clear
+ Uint16 ABD:1; // 15 Auto baud detect
+};
+
+union SCIFFCT_REG {
+ Uint16 all;
+ struct SCIFFCT_BITS bit;
+};
+
+//
+// SCI Register File
+//
+struct SCI_REGS {
+ union SCICCR_REG SCICCR; // Communications control register
+ union SCICTL1_REG SCICTL1; // Control register 1
+ Uint16 SCIHBAUD; // Baud rate (high) register
+ Uint16 SCILBAUD; // Baud rate (low) register
+ union SCICTL2_REG SCICTL2; // Control register 2
+ union SCIRXST_REG SCIRXST; // Recieve status register
+ Uint16 SCIRXEMU; // Recieve emulation buffer register
+ union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
+ Uint16 rsvd1; // reserved
+ Uint16 SCITXBUF; // Transmit data buffer
+ union SCIFFTX_REG SCIFFTX; // FIFO transmit register
+ union SCIFFRX_REG SCIFFRX; // FIFO recieve register
+ union SCIFFCT_REG SCIFFCT; // FIFO control register
+ Uint16 rsvd2; // reserved
+ Uint16 rsvd3; // reserved
+ union SCIPRI_REG SCIPRI; // FIFO Priority control
+};
+
+//
+// SCI External References & Function Declarations
+//
+extern volatile struct SCI_REGS SciaRegs;
+extern volatile struct SCI_REGS ScibRegs;
+extern volatile struct SCI_REGS ScicRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_SCI_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Spi.h b/bsp/include/DSP2833x_Spi.h
new file mode 100644
index 0000000..4131f66
--- /dev/null
+++ b/bsp/include/DSP2833x_Spi.h
@@ -0,0 +1,208 @@
+// TI File $Revision: /main/3 $
+// Checkin $Date: April 17, 2008 11:08:27 $
+//###########################################################################
+//
+// FILE: DSP2833x_Spi.h
+//
+// TITLE: DSP2833x Device SPI Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_SPI_H
+#define DSP2833x_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// SPI Individual Register Bit Definitions
+//
+
+//
+// SPI FIFO Transmit register bit definitions
+//
+struct SPIFFTX_BITS { // bit description
+ Uint16 TXFFIL:5; // 4:0 Interrupt level
+ Uint16 TXFFIENA:1; // 5 Interrupt enable
+ Uint16 TXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 TXFFINT:1; // 7 INT flag
+ Uint16 TXFFST:5; // 12:8 FIFO status
+ Uint16 TXFIFO:1; // 13 FIFO reset
+ Uint16 SPIFFENA:1; // 14 Enhancement enable
+ Uint16 SPIRST:1; // 15 Reset SPI
+};
+
+union SPIFFTX_REG {
+ Uint16 all;
+ struct SPIFFTX_BITS bit;
+};
+
+//
+// SPI FIFO recieve register bit definitions
+//
+struct SPIFFRX_BITS { // bits description
+ Uint16 RXFFIL:5; // 4:0 Interrupt level
+ Uint16 RXFFIENA:1; // 5 Interrupt enable
+ Uint16 RXFFINTCLR:1; // 6 Clear INT flag
+ Uint16 RXFFINT:1; // 7 INT flag
+ Uint16 RXFFST:5; // 12:8 FIFO status
+ Uint16 RXFIFORESET:1; // 13 FIFO reset
+ Uint16 RXFFOVFCLR:1; // 14 Clear overflow
+ Uint16 RXFFOVF:1; // 15 FIFO overflow
+};
+
+union SPIFFRX_REG {
+ Uint16 all;
+ struct SPIFFRX_BITS bit;
+};
+
+//
+// SPI FIFO control register bit definitions
+//
+struct SPIFFCT_BITS { // bits description
+ Uint16 TXDLY:8; // 7:0 FIFO transmit delay
+ Uint16 rsvd:8; // 15:8 reserved
+};
+
+union SPIFFCT_REG {
+ Uint16 all;
+ struct SPIFFCT_BITS bit;
+};
+
+//
+// SPI configuration register bit definitions
+//
+struct SPICCR_BITS { // bits description
+ Uint16 SPICHAR:4; // 3:0 Character length control
+ Uint16 SPILBK:1; // 4 Loop-back enable/disable
+ Uint16 rsvd1:1; // 5 reserved
+ Uint16 CLKPOLARITY:1; // 6 Clock polarity
+ Uint16 SPISWRESET:1; // 7 SPI SW Reset
+ Uint16 rsvd2:8; // 15:8 reserved
+};
+
+union SPICCR_REG {
+ Uint16 all;
+ struct SPICCR_BITS bit;
+};
+
+//
+// SPI operation control register bit definitions
+//
+struct SPICTL_BITS { // bits description
+ Uint16 SPIINTENA:1; // 0 Interrupt enable
+ Uint16 TALK:1; // 1 Master/Slave transmit enable
+ Uint16 MASTER_SLAVE:1; // 2 Network control mode
+ Uint16 CLK_PHASE:1; // 3 Clock phase select
+ Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
+ Uint16 rsvd:11; // 15:5 reserved
+};
+
+union SPICTL_REG {
+ Uint16 all;
+ struct SPICTL_BITS bit;
+};
+
+//
+// SPI status register bit definitions
+//
+struct SPISTS_BITS { // bits description
+ Uint16 rsvd1:5; // 4:0 reserved
+ Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
+ Uint16 INT_FLAG:1; // 6 SPI interrupt flag
+ Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
+ Uint16 rsvd2:8; // 15:8 reserved
+};
+
+union SPISTS_REG {
+ Uint16 all;
+ struct SPISTS_BITS bit;
+};
+
+//
+// SPI priority control register bit definitions
+//
+struct SPIPRI_BITS { // bits description
+ Uint16 rsvd1:4; // 3:0 reserved
+ Uint16 FREE:1; // 4 Free emulation mode control
+ Uint16 SOFT:1; // 5 Soft emulation mode control
+ Uint16 rsvd2:1; // 6 reserved
+ Uint16 rsvd3:9; // 15:7 reserved
+};
+
+union SPIPRI_REG {
+ Uint16 all;
+ struct SPIPRI_BITS bit;
+};
+
+//
+// SPI Register File
+//
+struct SPI_REGS {
+ union SPICCR_REG SPICCR; // Configuration register
+ union SPICTL_REG SPICTL; // Operation control register
+ union SPISTS_REG SPISTS; // Status register
+ Uint16 rsvd1; // reserved
+ Uint16 SPIBRR; // Baud Rate
+ Uint16 rsvd2; // reserved
+ Uint16 SPIRXEMU; // Emulation buffer
+ Uint16 SPIRXBUF; // Serial input buffer
+ Uint16 SPITXBUF; // Serial output buffer
+ Uint16 SPIDAT; // Serial data
+ union SPIFFTX_REG SPIFFTX; // FIFO transmit register
+ union SPIFFRX_REG SPIFFRX; // FIFO recieve register
+ union SPIFFCT_REG SPIFFCT; // FIFO control register
+ Uint16 rsvd3[2]; // reserved
+ union SPIPRI_REG SPIPRI; // FIFO Priority control
+};
+
+//
+// SPI External References & Function Declarations
+//
+extern volatile struct SPI_REGS SpiaRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_SPI_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_SysCtrl.h b/bsp/include/DSP2833x_SysCtrl.h
new file mode 100644
index 0000000..751c95f
--- /dev/null
+++ b/bsp/include/DSP2833x_SysCtrl.h
@@ -0,0 +1,484 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: May 12, 2008 09:34:58 $
+//###########################################################################
+//
+// FILE: DSP2833x_SysCtrl.h
+//
+// TITLE: DSP2833x Device System Control Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_SYS_CTRL_H
+#define DSP2833x_SYS_CTRL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// System Control Individual Register Bit Definitions
+//
+
+//
+// PLL Status Register
+//
+struct PLLSTS_BITS { // bits description
+ Uint16 PLLLOCKS:1; // 0 PLL lock status
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 PLLOFF:1; // 2 PLL off bit
+ Uint16 MCLKSTS:1; // 3 Missing clock status bit
+ Uint16 MCLKCLR:1; // 4 Missing clock clear bit
+ Uint16 OSCOFF:1; // 5 Oscillator clock off
+ Uint16 MCLKOFF:1; // 6 Missing clock detect
+ Uint16 DIVSEL:2; // 7 Divide Select
+ Uint16 rsvd2:7; // 15:7 reserved
+};
+
+union PLLSTS_REG {
+ Uint16 all;
+ struct PLLSTS_BITS bit;
+};
+
+//
+// High speed peripheral clock register bit definitions
+//
+struct HISPCP_BITS { // bits description
+ Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union HISPCP_REG {
+ Uint16 all;
+ struct HISPCP_BITS bit;
+};
+
+//
+// Low speed peripheral clock register bit definitions
+//
+struct LOSPCP_BITS { // bits description
+ Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
+ Uint16 rsvd1:13; // 15:3 reserved
+};
+
+union LOSPCP_REG {
+ Uint16 all;
+ struct LOSPCP_BITS bit;
+};
+
+//
+// Peripheral clock control register 0 bit definitions
+//
+struct PCLKCR0_BITS { // bits description
+ Uint16 rsvd1:2; // 1:0 reserved
+ Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
+ Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
+ Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
+ Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
+ Uint16 rsvd2:2; // 7:6 reserved
+ Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
+ Uint16 rsvd3:1; // 9 reserved
+ Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
+ Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
+ Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
+ Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
+ Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
+ Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
+};
+
+union PCLKCR0_REG {
+ Uint16 all;
+ struct PCLKCR0_BITS bit;
+};
+
+//
+// Peripheral clock control register 1 bit definitions
+//
+struct PCLKCR1_BITS { // bits description
+ Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
+ Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
+ Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
+ Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
+ Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
+ Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
+ Uint16 rsvd1:2; // 7:6 reserved
+ Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
+ Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
+ Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
+ Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
+ Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
+ Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
+ Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
+ Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
+};
+
+union PCLKCR1_REG {
+ Uint16 all;
+ struct PCLKCR1_BITS bit;
+};
+
+//
+// Peripheral clock control register 2 bit definitions
+//
+struct PCLKCR3_BITS { // bits description
+ Uint16 rsvd1:8; // 7:0 reserved
+ Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
+ Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
+ Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
+ Uint16 DMAENCLK:1; // 11 Enable the DMA clock
+ Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
+ Uint16 GPIOINENCLK:1; // Enable GPIO input clock
+ Uint16 rsvd2:2; // 15:14 reserved
+};
+
+union PCLKCR3_REG {
+ Uint16 all;
+ struct PCLKCR3_BITS bit;
+};
+
+//
+// PLL control register bit definitions
+//
+struct PLLCR_BITS { // bits description
+ Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
+ Uint16 rsvd1:12; // 15:4 reserved
+};
+
+union PLLCR_REG {
+ Uint16 all;
+ struct PLLCR_BITS bit;
+};
+
+//
+// Low Power Mode 0 control register bit definitions
+//
+struct LPMCR0_BITS { // bits description
+ Uint16 LPM:2; // 1:0 Set the low power mode
+ Uint16 QUALSTDBY:6; // 7:2 Qualification
+ Uint16 rsvd1:7; // 14:8 reserved
+ Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
+};
+
+union LPMCR0_REG {
+ Uint16 all;
+ struct LPMCR0_BITS bit;
+};
+
+//
+// Dual-mapping configuration register bit definitions
+//
+struct MAPCNF_BITS { // bits description
+ Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
+ Uint16 rsvd1:15; // 15:1 reserved
+};
+
+union MAPCNF_REG {
+ Uint16 all;
+ struct MAPCNF_BITS bit;
+};
+
+//
+// System Control Register File
+//
+struct SYS_CTRL_REGS {
+ Uint16 rsvd1; // 0
+ union PLLSTS_REG PLLSTS; // 1
+ Uint16 rsvd2[8]; // 2-9
+
+ //
+ // 10: High-speed peripheral clock pre-scaler
+ //
+ union HISPCP_REG HISPCP;
+
+ union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
+ union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
+ union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
+ union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
+ Uint16 rsvd3; // 15: reserved
+ union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
+ union PLLCR_REG PLLCR; // 17: PLL control register
+
+ //
+ // No bit definitions are defined for SCSR because
+ // a read-modify-write instruction can clear the WDOVERRIDE bit
+ //
+ Uint16 SCSR; // 18: System control and status register
+
+ Uint16 WDCNTR; // 19: WD counter register
+ Uint16 rsvd4; // 20
+ Uint16 WDKEY; // 21: WD reset key register
+ Uint16 rsvd5[3]; // 22-24
+
+ //
+ // No bit definitions are defined for WDCR because
+ // the proper value must be written to the WDCHK field
+ // whenever writing to this register.
+ //
+ Uint16 WDCR; // 25: WD timer control register
+
+ Uint16 rsvd6[4]; // 26-29
+ union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
+ Uint16 rsvd7[1]; // 31
+};
+
+//
+// CSM Registers
+//
+
+//
+// CSM Status & Control register bit definitions
+//
+struct CSMSCR_BITS { // bit description
+ Uint16 SECURE:1; // 0 Secure flag
+ Uint16 rsvd1:14; // 14-1 reserved
+ Uint16 FORCESEC:1; // 15 Force Secure control bit
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union CSMSCR_REG {
+ Uint16 all;
+ struct CSMSCR_BITS bit;
+};
+
+//
+// CSM Register File
+//
+struct CSM_REGS {
+ Uint16 KEY0; // KEY reg bits 15-0
+ Uint16 KEY1; // KEY reg bits 31-16
+ Uint16 KEY2; // KEY reg bits 47-32
+ Uint16 KEY3; // KEY reg bits 63-48
+ Uint16 KEY4; // KEY reg bits 79-64
+ Uint16 KEY5; // KEY reg bits 95-80
+ Uint16 KEY6; // KEY reg bits 111-96
+ Uint16 KEY7; // KEY reg bits 127-112
+ Uint16 rsvd1; // reserved
+ Uint16 rsvd2; // reserved
+ Uint16 rsvd3; // reserved
+ Uint16 rsvd4; // reserved
+ Uint16 rsvd5; // reserved
+ Uint16 rsvd6; // reserved
+ Uint16 rsvd7; // reserved
+ union CSMSCR_REG CSMSCR; // CSM Status & Control register
+};
+
+//
+// Password locations
+//
+struct CSM_PWL {
+ Uint16 PSWD0; // PSWD bits 15-0
+ Uint16 PSWD1; // PSWD bits 31-16
+ Uint16 PSWD2; // PSWD bits 47-32
+ Uint16 PSWD3; // PSWD bits 63-48
+ Uint16 PSWD4; // PSWD bits 79-64
+ Uint16 PSWD5; // PSWD bits 95-80
+ Uint16 PSWD6; // PSWD bits 111-96
+ Uint16 PSWD7; // PSWD bits 127-112
+};
+
+//
+// Defines for Flash Registers
+//
+#define FLASH_SLEEP 0x0000;
+#define FLASH_STANDBY 0x0001;
+#define FLASH_ACTIVE 0x0003;
+
+//
+// Flash Option Register bit definitions
+//
+struct FOPT_BITS { // bit description
+ Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
+ Uint16 rsvd:15; // 1-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FOPT_REG {
+ Uint16 all;
+ struct FOPT_BITS bit;
+};
+
+//
+// Flash Power Modes Register bit definitions
+//
+struct FPWR_BITS { // bit description
+ Uint16 PWR:2; // 0-1 Power Mode bits
+ Uint16 rsvd:14; // 2-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FPWR_REG {
+ Uint16 all;
+ struct FPWR_BITS bit;
+};
+
+//
+// Flash Status Register bit definitions
+//
+struct FSTATUS_BITS { // bit description
+ Uint16 PWRS:2; // 0-1 Power Mode Status bits
+ Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
+ Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
+ Uint16 rsvd1:4; // 4-7 reserved
+ Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
+ Uint16 rsvd2:7; // 9-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FSTATUS_REG {
+ Uint16 all;
+ struct FSTATUS_BITS bit;
+};
+
+//
+// Flash Sleep to Standby Wait Counter Register bit definitions
+//
+struct FSTDBYWAIT_BITS { // bit description
+ //
+ // 0-8 Bank/Pump Sleep to Standby Wait Count bits
+ //
+ Uint16 STDBYWAIT:9;
+
+ Uint16 rsvd:7; // 9-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FSTDBYWAIT_REG {
+ Uint16 all;
+ struct FSTDBYWAIT_BITS bit;
+};
+
+//
+// Flash Standby to Active Wait Counter Register bit definitions
+//
+struct FACTIVEWAIT_BITS { // bit description
+ //
+ // 0-8 Bank/Pump Standby to Active Wait Count bits
+ //
+ Uint16 ACTIVEWAIT:9;
+
+ Uint16 rsvd:7; // 9-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FACTIVEWAIT_REG {
+ Uint16 all;
+ struct FACTIVEWAIT_BITS bit;
+};
+
+//
+// Bank Read Access Wait State Register bit definitions
+//
+struct FBANKWAIT_BITS { // bit description
+ Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
+ Uint16 rsvd1:4; // 4-7 reserved
+ Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
+ Uint16 rsvd2:4; // 12-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FBANKWAIT_REG {
+ Uint16 all;
+ struct FBANKWAIT_BITS bit;
+};
+
+//
+// OTP Read Access Wait State Register bit definitions
+//
+struct FOTPWAIT_BITS { // bit description
+ Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
+ Uint16 rsvd:11; // 5-15 reserved
+};
+
+//
+// Allow access to the bit fields or entire register
+//
+union FOTPWAIT_REG {
+ Uint16 all;
+ struct FOTPWAIT_BITS bit;
+};
+
+struct FLASH_REGS {
+ union FOPT_REG FOPT; // Option Register
+ Uint16 rsvd1; // reserved
+ union FPWR_REG FPWR; // Power Modes Register
+ union FSTATUS_REG FSTATUS; // Status Register
+
+ //
+ // Pump/Bank Sleep to Standby Wait State Register
+ //
+ union FSTDBYWAIT_REG FSTDBYWAIT;
+
+ //
+ // Pump/Bank Standby to Active Wait State Register
+ //
+ union FACTIVEWAIT_REG FACTIVEWAIT;
+
+ union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
+ union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
+};
+
+//
+// System Control External References & Function Declarations
+//
+extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
+extern volatile struct CSM_REGS CsmRegs;
+extern volatile struct CSM_PWL CsmPwl;
+extern volatile struct FLASH_REGS FlashRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_SYS_CTRL_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_XIntrupt.h b/bsp/include/DSP2833x_XIntrupt.h
new file mode 100644
index 0000000..3e32c25
--- /dev/null
+++ b/bsp/include/DSP2833x_XIntrupt.h
@@ -0,0 +1,109 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:52:39 $
+//###########################################################################
+//
+// FILE: DSP2833x_XIntrupt.h
+//
+// TITLE: DSP2833x Device External Interrupt Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_XINTRUPT_H
+#define DSP2833x_XINTRUPT_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct XINTCR_BITS {
+ Uint16 ENABLE:1; // 0 enable/disable
+ Uint16 rsvd1:1; // 1 reserved
+ Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
+ Uint16 rsvd2:12; //15:4 reserved
+};
+
+union XINTCR_REG {
+ Uint16 all;
+ struct XINTCR_BITS bit;
+};
+
+struct XNMICR_BITS {
+ Uint16 ENABLE:1; // 0 enable/disable
+ Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
+ Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
+ Uint16 rsvd2:12; // 15:4 reserved
+};
+
+union XNMICR_REG {
+ Uint16 all;
+ struct XNMICR_BITS bit;
+};
+
+//
+// External Interrupt Register File
+//
+struct XINTRUPT_REGS {
+ union XINTCR_REG XINT1CR;
+ union XINTCR_REG XINT2CR;
+ union XINTCR_REG XINT3CR;
+ union XINTCR_REG XINT4CR;
+ union XINTCR_REG XINT5CR;
+ union XINTCR_REG XINT6CR;
+ union XINTCR_REG XINT7CR;
+ union XNMICR_REG XNMICR;
+ Uint16 XINT1CTR;
+ Uint16 XINT2CTR;
+ Uint16 rsvd[5];
+ Uint16 XNMICTR;
+};
+
+//
+// External Interrupt References & Function Declarations
+//
+extern volatile struct XINTRUPT_REGS XIntruptRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_XINTF_H definition
+
+//
+// End of file
+//
+
diff --git a/bsp/include/DSP2833x_Xintf.h b/bsp/include/DSP2833x_Xintf.h
new file mode 100644
index 0000000..3890e91
--- /dev/null
+++ b/bsp/include/DSP2833x_Xintf.h
@@ -0,0 +1,154 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: July 27, 2009 13:57:25 $
+//###########################################################################
+//
+// FILE: DSP2833x_Xintf.h
+//
+// TITLE: DSP2833x Device External Interface Register Definitions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP2833x_XINTF_H
+#define DSP2833x_XINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//
+// XINTF timing register bit definitions
+//
+struct XTIMING_BITS { // bits description
+ Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
+ Uint16 XWRACTIVE:3; // 4:2 Write access active timing
+ Uint16 XWRLEAD:2; // 6:5 Write access lead timing
+ Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
+ Uint16 XRDACTIVE:3; // 11:9 Read access active timing
+ Uint16 XRDLEAD:2; // 13:12 Read access lead timing
+ Uint16 USEREADY:1; // 14 Extend access using HW waitstates
+ Uint16 READYMODE:1; // 15 Ready mode
+ Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
+ Uint16 rsvd1:4; // 21:18 reserved
+ Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
+ Uint16 rsvd3:9; // 31:23 reserved
+};
+
+union XTIMING_REG {
+ Uint32 all;
+ struct XTIMING_BITS bit;
+};
+
+//
+// XINTF control register bit definitions
+//
+struct XINTCNF2_BITS { // bits description
+ Uint16 WRBUFF:2; // 1:0 Write buffer depth
+ Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
+ Uint16 CLKOFF:1; // 3 Disable XCLKOUT
+ Uint16 rsvd1:2; // 5:4 reserved
+ Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
+ Uint16 rsvd2:1; // 8 reserved
+ Uint16 HOLD:1; // 9 Hold enable/disable
+ Uint16 HOLDS:1; // 10 Current state of HOLDn input
+ Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
+ Uint16 rsvd3:4; // 15:12 reserved
+ Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
+ Uint16 rsvd4:13; // 31:19 reserved
+};
+
+union XINTCNF2_REG {
+ Uint32 all;
+ struct XINTCNF2_BITS bit;
+};
+
+//
+// XINTF bank switching register bit definitions
+//
+struct XBANK_BITS { // bits description
+ Uint16 BANK:3; // 2:0 Zone for which banking is enabled
+ Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
+ Uint16 rsvd:10; // 15:6 reserved
+};
+
+union XBANK_REG {
+ Uint16 all;
+ struct XBANK_BITS bit;
+};
+
+struct XRESET_BITS {
+ Uint16 XHARDRESET:1;
+ Uint16 rsvd1:15;
+};
+
+union XRESET_REG {
+ Uint16 all;
+ struct XRESET_BITS bit;
+};
+
+//
+// XINTF Register File
+//
+struct XINTF_REGS {
+ union XTIMING_REG XTIMING0;
+ Uint32 rsvd1[5];
+ union XTIMING_REG XTIMING6;
+ union XTIMING_REG XTIMING7;
+ Uint32 rsvd2[2];
+ union XINTCNF2_REG XINTCNF2;
+ Uint32 rsvd3;
+ union XBANK_REG XBANK;
+ Uint16 rsvd4;
+ Uint16 XREVISION;
+ Uint16 rsvd5[2];
+ union XRESET_REG XRESET;
+};
+
+//
+// XINTF External References & Function Declarations
+//
+extern volatile struct XINTF_REGS XintfRegs;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif // end of DSP2833x_XINTF_H definition
+
+//
+// End of File
+//
+
diff --git a/bsp/include/DSP28x_Project.h b/bsp/include/DSP28x_Project.h
new file mode 100644
index 0000000..b827bb6
--- /dev/null
+++ b/bsp/include/DSP28x_Project.h
@@ -0,0 +1,53 @@
+
+// TI File $Revision: /main/1 $
+// Checkin $Date: April 22, 2008 14:35:56 $
+//###########################################################################
+//
+// FILE: DSP28x_Project.h
+//
+// TITLE: DSP28x Project Headerfile and Examples Include File
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef DSP28x_PROJECT_H
+#define DSP28x_PROJECT_H
+
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+#endif // end of DSP28x_PROJECT_H definition
+
diff --git a/bsp/source/DSP2833x_ADC_cal.asm b/bsp/source/DSP2833x_ADC_cal.asm
new file mode 100644
index 0000000..a1605d0
--- /dev/null
+++ b/bsp/source/DSP2833x_ADC_cal.asm
@@ -0,0 +1,74 @@
+;; TI File $Revision: /main/1 $
+;; Checkin $Date: July 30, 2007 10:29:23 $
+;;###########################################################################
+;;
+;; FILE: ADC_cal.asm
+;;
+;; TITLE: 2833x Boot Rom ADC Cal routine.
+;;
+;; Functions:
+;;
+;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and
+;; ADCOFFTRIM registers
+;; Notes:
+;;
+;;###########################################################################
+;; $TI Release: F2833x Support Library v2.00.00.00 $
+;; $Release Date: Mon May 27 06:46:54 CDT 2019 $
+;; $Copyright:
+;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;;###########################################################################
+
+ .def _ADC_cal
+ .asg "0x711C", ADCREFSEL_LOC
+
+;-----------------------------------------------
+; _ADC_cal
+;-----------------------------------------------
+;-----------------------------------------------
+; This is the ADC cal routine.This routine is programmed into
+; reserved memory by the factory. 0xAAAA and 0xBBBB are place-
+; holders for calibration data.
+;The actual values programmed by TI are device specific.
+;
+; This function assumes that the clocks have been
+; enabled to the ADC module.
+;-----------------------------------------------
+
+ .sect ".adc_cal"
+
+_ADC_cal
+ MOVW DP, #ADCREFSEL_LOC >> 6
+ MOV @28, #0xAAAA ; actual value may not be 0xAAAA
+ MOV @29, #0xBBBB ; actual value may not be 0xBBBB
+ LRETR
+;eof ----------
diff --git a/bsp/source/DSP2833x_Adc.c b/bsp/source/DSP2833x_Adc.c
new file mode 100644
index 0000000..18b8f1f
--- /dev/null
+++ b/bsp/source/DSP2833x_Adc.c
@@ -0,0 +1,99 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: October 23, 2007 13:34:09 $
+//###########################################################################
+//
+// FILE: DSP2833x_Adc.c
+//
+// TITLE: DSP2833x ADC Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// Defines
+//
+#define ADC_usDELAY 5000L
+
+//
+// InitAdc - This function initializes ADC to a known state.
+//
+void
+InitAdc(void)
+{
+ extern void DSP28x_usDelay(Uint32 Count);
+
+ //
+ // *IMPORTANT*
+ // The ADC_cal function, which copies the ADC calibration values from
+ // TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs
+ // automatically in the Boot ROM. If the boot ROM code is bypassed during
+ // the debug process, the following function MUST be called for the ADC to
+ // function according to specification. The clocks to the ADC MUST be
+ // enabled before calling this function. See the device data manual and/or
+ // the ADC Reference Manual for more information.
+ //
+ EALLOW;
+ SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
+ ADC_cal();
+ EDIS;
+
+ //
+ // To powerup the ADC the ADCENCLK bit should be set first to enable
+ // clocks, followed by powering up the bandgap, reference circuitry, and
+ // ADC core. Before the first conversion is performed a 5ms delay must be
+ // observed after power up to give all analog circuits time to power up
+ // and settle
+ //
+
+ //
+ // Please note that for the delay function below to operate correctly the
+ // CPU_RATE define statement in the DSP2833x_Examples.h file must
+ // contain the correct CPU clock period in nanoseconds.
+ //
+ AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
+ DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_CSMPasswords.asm b/bsp/source/DSP2833x_CSMPasswords.asm
new file mode 100644
index 0000000..3ed225f
--- /dev/null
+++ b/bsp/source/DSP2833x_CSMPasswords.asm
@@ -0,0 +1,95 @@
+;// TI File $Revision: /main/3 $
+;// Checkin $Date: June 26, 2007 16:41:07 $
+;//###########################################################################
+;//
+;// FILE: DSP2833x_CSMPasswords.asm
+;//
+;// TITLE: DSP2833x Code Security Module Passwords.
+;//
+;// DESCRIPTION:
+;//
+;// This file is used to specify password values to
+;// program into the CSM password locations in Flash
+;// at 0x33FFF8 - 0x33FFFF.
+;//
+;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are
+;// all programmed to 0x0000
+;//
+;//###########################################################################
+;// $TI Release: F2833x Support Library v2.00.00.00 $
+;// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+;// $Copyright:
+;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+
+; The "csmpasswords" section contains the actual CSM passwords that will be
+; linked and programmed into to the CSM password locations (PWL) in flash.
+; These passwords must be known in order to unlock the CSM module.
+; All 0xFFFF's (erased) is the default value for the password locations (PWL).
+
+; It is recommended that all passwords be left as 0xFFFF during code
+; development. Passwords of 0xFFFF do not activate code security and dummy
+; reads of the CSM PWL registers is all that is required to unlock the CSM.
+; When code development is complete, modify the passwords to activate the
+; code security module.
+
+ .sect "csmpasswds"
+
+ .int 0xFFFF ;PWL0 (LSW of 128-bit password)
+ .int 0xFFFF ;PWL1
+ .int 0xFFFF ;PWL2
+ .int 0xFFFF ;PWL3
+ .int 0xFFFF ;PWL4
+ .int 0xFFFF ;PWL5
+ .int 0xFFFF ;PWL6
+ .int 0xFFFF ;PWL7 (MSW of 128-bit password)
+
+;----------------------------------------------------------------------
+
+; For code security operation, all addresses between 0x33FF80 and
+; 0X33fff5 cannot be used as program code or data. These locations
+; must be programmed to 0x0000 when the code security password locations
+; (PWL) are programmed. If security is not a concern, then these addresses
+; can be used for code or data.
+
+; The section "csm_rsvd" can be used to program these locations to 0x0000.
+
+ .sect "csm_rsvd"
+ .loop (33FFF5h - 33FF80h + 1)
+ .int 0x0000
+ .endloop
+
+;//===========================================================================
+;// End of file.
+;//===========================================================================
+
+
diff --git a/bsp/source/DSP2833x_CodeStartBranch.asm b/bsp/source/DSP2833x_CodeStartBranch.asm
new file mode 100644
index 0000000..88d19e9
--- /dev/null
+++ b/bsp/source/DSP2833x_CodeStartBranch.asm
@@ -0,0 +1,117 @@
+;// TI File $Revision: /main/1 $
+;// Checkin $Date: August 18, 2006 13:45:55 $
+;//###########################################################################
+;//
+;// FILE: DSP2833x_CodeStartBranch.asm
+;//
+;// TITLE: Branch for redirecting code execution after boot.
+;//
+;// For these examples, code_start is the first code that is executed after
+;// exiting the boot ROM code.
+;//
+;// The codestart section in the linker cmd file is used to physically place
+;// this code at the correct memory location. This section should be placed
+;// at the location the BOOT ROM will re-direct the code to. For example,
+;// for boot to FLASH this code will be located at 0x3f7ff6.
+;//
+;// In addition, the example DSP2833x projects are setup such that the codegen
+;// entry point is also set to the code_start label. This is done by linker
+;// option -e in the project build options. When the debugger loads the code,
+;// it will automatically set the PC to the "entry point" address indicated by
+;// the -e linker option. In this case the debugger is simply assigning the PC,
+;// it is not the same as a full reset of the device.
+;//
+;// The compiler may warn that the entry point for the project is other then
+;// _c_init00. _c_init00 is the C environment setup and is run before
+;// main() is entered. The code_start code will re-direct the execution
+;// to _c_init00 and thus there is no worry and this warning can be ignored.
+;//
+;//###########################################################################
+;// $TI Release: F2833x Support Library v2.00.00.00 $
+;// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+;// $Copyright:
+;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+
+
+***********************************************************************
+
+WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
+
+ .ref _c_int00
+ .global code_start
+
+***********************************************************************
+* Function: codestart section
+*
+* Description: Branch to code starting point
+***********************************************************************
+
+ .sect "codestart"
+
+code_start:
+ .if WD_DISABLE == 1
+ LB wd_disable ;Branch to watchdog disable code
+ .else
+ LB _c_int00 ;Branch to start of boot.asm in RTS library
+ .endif
+
+;end codestart section
+
+
+***********************************************************************
+* Function: wd_disable
+*
+* Description: Disables the watchdog timer
+***********************************************************************
+ .if WD_DISABLE == 1
+
+ .text
+wd_disable:
+ SETC OBJMODE ;Set OBJMODE for 28x object code
+ EALLOW ;Enable EALLOW protected register access
+ MOVZ DP, #7029h>>6 ;Set data page for WDCR register
+ MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
+ EDIS ;Disable EALLOW protected register access
+ LB _c_int00 ;Branch to start of boot.asm in RTS library
+
+ .endif
+
+;end wd_disable
+
+
+
+ .end
+
+;//===========================================================================
+;// End of file.
+;//===========================================================================
diff --git a/bsp/source/DSP2833x_CpuTimers.c b/bsp/source/DSP2833x_CpuTimers.c
new file mode 100644
index 0000000..1c7c63f
--- /dev/null
+++ b/bsp/source/DSP2833x_CpuTimers.c
@@ -0,0 +1,195 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: July 9, 2009 10:51:59 $
+//###########################################################################
+//
+// FILE: DSP2833x_CpuTimers.c
+//
+// TITLE: CPU 32-bit Timers Initialization & Support Functions.
+//
+// NOTES: CpuTimer2 is reserved for use with DSP BIOS and
+// other realtime operating systems.
+//
+// Do not use these this timer in your application if you ever plan
+// on integrating DSP-BIOS or another realtime OS.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // Headerfile Include File
+#include "DSP2833x_Examples.h" // Examples Include File
+
+//
+// Defines
+//
+struct CPUTIMER_VARS CpuTimer0;
+
+//
+// When using DSP BIOS & other RTOS, comment out CPU Timer 2 code.
+//
+struct CPUTIMER_VARS CpuTimer1;
+struct CPUTIMER_VARS CpuTimer2;
+
+//
+// InitCpuTimers - This function initializes all three CPU timers to a known
+// state.
+//
+void
+InitCpuTimers(void)
+{
+ //
+ // CPU Timer 0 - Initialize address pointers to respective timer registers
+ //
+ CpuTimer0.RegsAddr = &CpuTimer0Regs;
+
+ //
+ // Initialize timer period to maximum
+ //
+ CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
+
+ //
+ // Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
+ //
+ CpuTimer0Regs.TPR.all = 0;
+ CpuTimer0Regs.TPRH.all = 0;
+
+ //
+ // Make sure timer is stopped
+ //
+ CpuTimer0Regs.TCR.bit.TSS = 1;
+
+ //
+ // Reload all counter register with period value
+ //
+ CpuTimer0Regs.TCR.bit.TRB = 1;
+
+ //
+ // Reset interrupt counters
+ //
+ CpuTimer0.InterruptCount = 0;
+
+ //
+ // CpuTimer2 is reserved for DSP BIOS & other RTOS
+ // Do not use this timer if you ever plan on integrating
+ // DSP-BIOS or another realtime OS.
+ //
+
+ //
+ // Initialize address pointers to respective timer registers
+ //
+ CpuTimer1.RegsAddr = &CpuTimer1Regs;
+ CpuTimer2.RegsAddr = &CpuTimer2Regs;
+
+ //
+ // Initialize timer period to maximum
+ //
+ CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
+ CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
+
+ //
+ // Make sure timers are stopped
+ //
+ CpuTimer1Regs.TCR.bit.TSS = 1;
+ CpuTimer2Regs.TCR.bit.TSS = 1;
+
+ //
+ // Reload all counter register with period value
+ //
+ CpuTimer1Regs.TCR.bit.TRB = 1;
+ CpuTimer2Regs.TCR.bit.TRB = 1;
+
+ //
+ // Reset interrupt counters
+ //
+ CpuTimer1.InterruptCount = 0;
+ CpuTimer2.InterruptCount = 0;
+}
+
+//
+// ConfigCpuTimer - This function initializes the selected timer to the period
+// specified by the "Freq" and "Period" parameters. The "Freq" is entered as
+// "MHz" and the period in "uSeconds". The timer is held in the stopped state
+// after configuration.
+//
+void
+ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
+{
+ Uint32 temp;
+
+ //
+ // Initialize timer period
+ //
+ Timer->CPUFreqInMHz = Freq;
+ Timer->PeriodInUSec = Period;
+ temp = (long) (Freq * Period);
+ Timer->RegsAddr->PRD.all = temp;
+
+ //
+ // Set pre-scale counter to divide by 1 (SYSCLKOUT)
+ //
+ Timer->RegsAddr->TPR.all = 0;
+ Timer->RegsAddr->TPRH.all = 0;
+
+ //
+ // Initialize timer control register
+ //
+
+ //
+ // 1 = Stop timer, 0 = Start/Restart Timer
+ //
+ Timer->RegsAddr->TCR.bit.TSS = 1;
+
+ Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
+ Timer->RegsAddr->TCR.bit.SOFT = 1;
+ Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run
+
+ //
+ // 0 = Disable/ 1 = Enable Timer Interrupt
+ //
+ Timer->RegsAddr->TCR.bit.TIE = 1;
+
+ //
+ // Reset interrupt counter
+ //
+ Timer->InterruptCount = 0;
+}
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_DBGIER.asm b/bsp/source/DSP2833x_DBGIER.asm
new file mode 100644
index 0000000..7bfa955
--- /dev/null
+++ b/bsp/source/DSP2833x_DBGIER.asm
@@ -0,0 +1,59 @@
+;// TI File $Revision: /main/1 $
+;// Checkin $Date: August 18, 2006 13:46:03 $
+;//###########################################################################
+;//
+;// FILE: DSP2833x_DBGIER.asm
+;//
+;// TITLE: Set the DBGIER register
+;//
+;// DESCRIPTION:
+;//
+;// Function to set the DBGIER register (for realtime emulation).
+;// Function Prototype: void SetDBGIER(Uint16)
+;// Useage: SetDBGIER(value);
+;// Input Parameters: Uint16 value = value to put in DBGIER register.
+;// Return Value: none
+;//
+;//###########################################################################
+;// $TI Release: F2833x Support Library v2.00.00.00 $
+;// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+;// $Copyright:
+;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+ .global _SetDBGIER
+ .text
+
+_SetDBGIER:
+ MOV *SP++,AL
+ POP DBGIER
+ LRETR
+
diff --git a/bsp/source/DSP2833x_DMA.c b/bsp/source/DSP2833x_DMA.c
new file mode 100644
index 0000000..7e64fe9
--- /dev/null
+++ b/bsp/source/DSP2833x_DMA.c
@@ -0,0 +1,1316 @@
+//###########################################################################
+//
+// FILE: DSP2833x_DMA.c
+//
+// TITLE: DSP2833x Device DMA Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // Headerfile Include File
+#include "DSP2833x_Examples.h" // Examples Include File
+
+//
+// DMAInitialize - This function initializes the DMA to a known state.
+//
+void
+DMAInitialize(void)
+{
+ EALLOW;
+
+ //
+ // Perform a hard reset on DMA
+ //
+ DmaRegs.DMACTRL.bit.HARDRESET = 1;
+ asm (" nop"); // one NOP required after HARDRESET
+
+ //
+ // Allow DMA to run free on emulation suspend
+ //
+ DmaRegs.DEBUGCTRL.bit.FREE = 1;
+
+ EDIS;
+}
+
+//
+// DMACH1AddrConfig -
+//
+void
+DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+ EALLOW;
+
+ //
+ // Set up SOURCE address
+ //
+
+ //
+ // Point to beginning of source buffer
+ //
+ DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ //
+ // Set up DESTINATION address
+ //
+
+ //
+ // Point to beginning of destination buffer
+ //
+ DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ EDIS;
+}
+
+//
+// DMACH1BurstConfig -
+//
+void
+DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+ EALLOW;
+
+ //
+ // Set up BURST registers:
+ //
+
+ //
+ // Number of words(X-1) x-ferred in a burst
+ //
+ DmaRegs.CH1.BURST_SIZE.all = bsize;
+
+ //
+ // Increment source addr between each word x-ferred
+ //
+ DmaRegs.CH1.SRC_BURST_STEP = srcbstep;
+
+ //
+ // Increment dest addr between each word x-ferred
+ //
+ DmaRegs.CH1.DST_BURST_STEP = desbstep;
+
+ EDIS;
+}
+
+//
+// DMACH1TransferConfig -
+//
+void
+DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+ EALLOW;
+
+ //
+ // Set up TRANSFER registers:
+ //
+
+ //
+ // Number of bursts per transfer, DMA interrupt will occur after
+ // completed transfer
+ //
+ DmaRegs.CH1.TRANSFER_SIZE = tsize;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH1.DST_TRANSFER_STEP = deststep;
+
+ EDIS;
+}
+
+//
+// DMACH1WrapConfig -
+//
+void
+DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16
+ deswstep)
+{
+ EALLOW;
+
+ //
+ // Set up WRAP registers
+ //
+ DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
+ DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap
+
+ //
+ // Wrap destination address after N bursts
+ //
+ DmaRegs.CH1.DST_WRAP_SIZE = deswsize;
+
+ DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap
+
+ EDIS;
+}
+
+//
+// DMACH1ModeConfig -
+//
+void
+DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont,
+ Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize,
+ Uint16 chintmode, Uint16 chinte)
+{
+ EALLOW;
+
+ //
+ // Set up MODE Register:
+ //
+
+ //
+ // Passed DMA channel as peripheral interrupt source
+ //
+ DmaRegs.CH1.MODE.bit.PERINTSEL = persel;
+
+ DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
+ DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable
+ DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable
+ DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
+ DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
+ DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
+ DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16/32-bit data size transfers
+
+ //
+ // Generate interrupt to CPU at beginning/end of transfer
+ //
+ DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode;
+
+ //
+ // Channel Interrupt to CPU enable
+ //
+ DmaRegs.CH1.MODE.bit.CHINTE = chinte;
+
+ //
+ // Clear any spurious flags:
+ //
+ DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;// Clear any spurious interrupt flags
+ DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
+ DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
+
+ //
+ // Initialize PIE vector for CPU interrupt:
+ //
+ PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE
+
+ EDIS;
+}
+
+//
+// StartDMACH1 - This function starts DMA Channel 1.
+//
+void
+StartDMACH1(void)
+{
+ EALLOW;
+ DmaRegs.CH1.CONTROL.bit.RUN = 1;
+ EDIS;
+}
+
+//
+// DMACH2AddrConfig -
+//
+void
+DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+ EALLOW;
+
+ //
+ // Set up SOURCE address:
+ //
+
+ //
+ // Point to beginning of source buffer
+ //
+ DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;
+ DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ //
+ // Set up DESTINATION address:
+ //
+
+ //
+ // Point to beginning of destination buffer
+ //
+ DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;
+ DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ EDIS;
+}
+
+//
+// DMACH2BurstConfig -
+//
+void
+DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+ EALLOW;
+
+ //
+ // Set up BURST registers:
+ //
+
+ //
+ // Number of words(X-1) x-ferred in a burst
+ //
+ DmaRegs.CH2.BURST_SIZE.all = bsize;
+
+ //
+ // Increment source addr between each word x-ferred
+ //
+ DmaRegs.CH2.SRC_BURST_STEP = srcbstep;
+
+ //
+ // Increment dest addr between each word x-ferred
+ //
+ DmaRegs.CH2.DST_BURST_STEP = desbstep;
+
+ EDIS;
+}
+
+//
+// DMACH2TransferConfig -
+//
+void
+DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+ EALLOW;
+
+ //
+ // Set up TRANSFER registers:
+ //
+
+ //
+ // Number of bursts per transfer, DMA interrupt will occur
+ // after completed transfer
+ //
+ DmaRegs.CH2.TRANSFER_SIZE = tsize;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH2.DST_TRANSFER_STEP = deststep;
+
+ EDIS;
+}
+
+//
+// DMACH2WrapConfig -
+//
+void
+DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep)
+{
+ EALLOW;
+
+ //
+ // Set up WRAP registers:
+ //
+
+ //
+ // Wrap source address after N bursts
+ //
+ DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize;
+
+ //
+ // Step for source wrap
+ //
+ DmaRegs.CH2.SRC_WRAP_STEP = srcwstep;
+
+ //
+ // Wrap destination address after N bursts
+ //
+ DmaRegs.CH2.DST_WRAP_SIZE = deswsize;
+
+ //
+ // Step for destination wrap
+ //
+ DmaRegs.CH2.DST_WRAP_STEP = deswstep;
+
+ EDIS;
+}
+
+//
+// DMACH2ModeConfig -
+//
+void
+DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont,
+ Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize,
+ Uint16 chintmode, Uint16 chinte)
+{
+ EALLOW;
+
+ //
+ // Set up MODE Register
+ //
+
+ //
+ // Passed DMA channel as peripheral interrupt source
+ //
+ DmaRegs.CH2.MODE.bit.PERINTSEL = persel;
+
+ //
+ // Peripheral interrupt enable
+ //
+ DmaRegs.CH2.MODE.bit.PERINTE = perinte;
+
+ //
+ // Oneshot enable
+ //
+ DmaRegs.CH2.MODE.bit.ONESHOT = oneshot;
+
+ //
+ // Continous enable
+ //
+ DmaRegs.CH2.MODE.bit.CONTINUOUS = cont;
+
+ //
+ // Peripheral sync enable/disable
+ //
+ DmaRegs.CH2.MODE.bit.SYNCE = synce;
+
+ //
+ // Sync effects source or destination
+ //
+ DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel;
+
+ //
+ // Enable/disable the overflow interrupt
+ //
+ DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte;
+
+ //
+ // 16-bit/32-bit data size transfers
+ //
+ DmaRegs.CH2.MODE.bit.DATASIZE = datasize;
+
+ //
+ // Generate interrupt to CPU at beginning/end of transfer
+ //
+ DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode;
+
+ //
+ // Channel Interrupt to CPU enable
+ //
+ DmaRegs.CH2.MODE.bit.CHINTE = chinte;
+
+ //
+ // Clear any spurious flags:
+ //
+
+ //
+ // Clear any spurious interrupt flags
+ //
+ DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;
+
+ //
+ // Clear any spurious sync flags
+ //
+ DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1;
+
+ //
+ // Clear any spurious sync error flags
+ //
+ DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;
+
+ //
+ // Initialize PIE vector for CPU interrupt
+ //
+ PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE
+
+ EDIS;
+}
+
+//
+// StartDMACH2 - This function starts DMA Channel 2.
+//
+void
+StartDMACH2(void)
+{
+ EALLOW;
+ DmaRegs.CH2.CONTROL.bit.RUN = 1;
+ EDIS;
+}
+
+//
+// DMACH3AddrConfig -
+//
+void
+DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+ EALLOW;
+
+ //
+ // Set up SOURCE address:
+ //
+
+ //
+ // Point to beginning of source buffer
+ //
+ DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;
+ DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ //
+ // Set up DESTINATION address:
+ //
+
+ //
+ // Point to beginning of destination buffer
+ //
+ DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ EDIS;
+}
+
+//
+// DMACH3BurstConfig -
+//
+void
+DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+ EALLOW;
+
+ //
+ // Set up BURST registers:
+ //
+
+ //
+ // Number of words(X-1) x-ferred in a burst
+ //
+ DmaRegs.CH3.BURST_SIZE.all = bsize;
+
+ //
+ // Increment source addr between each word x-ferred
+ //
+ DmaRegs.CH3.SRC_BURST_STEP = srcbstep;
+
+ //
+ // Increment dest addr between each word x-ferred
+ //
+ DmaRegs.CH3.DST_BURST_STEP = desbstep;
+
+ EDIS;
+}
+
+//
+// DMACH3TransferConfig -
+//
+void
+DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+ EALLOW;
+
+ //
+ // Set up TRANSFER registers:
+ //
+
+ //
+ // Number of bursts per transfer, DMA interrupt will occur after
+ // completed transfer
+ //
+ DmaRegs.CH3.TRANSFER_SIZE = tsize;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH3.DST_TRANSFER_STEP = deststep;
+
+ EDIS;
+}
+
+//
+// DMACH3WrapConfig -
+//
+void
+DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep)
+{
+ EALLOW;
+
+ //
+ // Set up WRAP registers:
+ //
+ DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
+ DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap
+
+ //
+ // Wrap destination address after N bursts
+ //
+ DmaRegs.CH3.DST_WRAP_SIZE = deswsize;
+
+ //
+ // Step for destination wrap
+ //
+ DmaRegs.CH3.DST_WRAP_STEP = deswstep;
+
+ EDIS;
+}
+
+//
+// DMACH3ModeConfig -
+//
+void
+DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont,
+ Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize,
+ Uint16 chintmode, Uint16 chinte)
+{
+ EALLOW;
+
+ //
+ // Set up MODE Register:
+ //
+
+ //
+ // Passed DMA channel as peripheral interrupt source
+ //
+ DmaRegs.CH3.MODE.bit.PERINTSEL = persel;
+
+ //
+ // Peripheral interrupt enable
+ //
+ DmaRegs.CH3.MODE.bit.PERINTE = perinte;
+
+ DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable
+ DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable
+ DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
+
+ //
+ // Sync effects source or destination
+ //
+ DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel;
+
+ //
+ // Enable/disable the overflow interrupt
+ //
+ DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte;
+
+ //
+ // 16-bit/32-bit data size transfers
+ //
+ DmaRegs.CH3.MODE.bit.DATASIZE = datasize;
+
+ //
+ // Generate interrupt to CPU at beginning/end of transfer
+ //
+ DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode;
+
+ //
+ // Channel Interrupt to CPU enable
+ //
+ DmaRegs.CH3.MODE.bit.CHINTE = chinte;
+
+ //
+ // Clear any spurious flags:
+ //
+
+ //
+ // Clear any spurious interrupt flags
+ //
+ DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1;
+
+ DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
+
+ //
+ // Clear any spurious sync error flags
+ //
+ DmaRegs.CH3.CONTROL.bit.ERRCLR = 1;
+
+ //
+ // Initialize PIE vector for CPU interrupt:
+ //
+ PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE
+
+ EDIS;
+}
+
+//
+// StartDMACH3 - This function starts DMA Channel 3.
+//
+void
+StartDMACH3(void)
+{
+ EALLOW;
+ DmaRegs.CH3.CONTROL.bit.RUN = 1;
+ EDIS;
+}
+
+//
+// DMACH4AddrConfig -
+//
+void
+DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+ EALLOW;
+
+ //
+ // Set up SOURCE address:
+ //
+
+ //
+ // Point to beginning of source buffer
+ //
+ DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ //
+ // Set up DESTINATION address:
+ //
+
+ //
+ // Point to beginning of destination buffer
+ //
+ DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ EDIS;
+}
+
+//
+// DMACH4BurstConfig -
+//
+void
+DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+ EALLOW;
+
+ //
+ // Set up BURST registers:
+ //
+
+ //
+ // Number of words(X-1) x-ferred in a burst
+ //
+ DmaRegs.CH4.BURST_SIZE.all = bsize;
+
+ //
+ // Increment source addr between each word x-ferred
+ //
+ DmaRegs.CH4.SRC_BURST_STEP = srcbstep;
+
+ //
+ // Increment dest addr between each word x-ferred
+ //
+ DmaRegs.CH4.DST_BURST_STEP = desbstep;
+
+ EDIS;
+}
+
+//
+// DMACH4TransferConfig -
+//
+void
+DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+ EALLOW;
+
+ //
+ // Set up TRANSFER registers:
+ //
+
+ //
+ // Number of bursts per transfer, DMA interrupt will occur after completed
+ // transfer
+ //
+ DmaRegs.CH4.TRANSFER_SIZE = tsize;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH4.DST_TRANSFER_STEP = deststep;
+
+ EDIS;
+}
+
+//
+// DMACH4WrapConfig -
+//
+void
+DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep)
+{
+ EALLOW;
+
+ //
+ // Set up WRAP registers:
+ //
+ DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts
+ DmaRegs.CH4.SRC_WRAP_STEP = srcwstep;// Step for source wrap
+
+ //
+ // Wrap destination address after N bursts
+ //
+ DmaRegs.CH4.DST_WRAP_SIZE = deswsize;
+
+ DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
+
+ EDIS;
+}
+
+//
+// DMACH4ModeConfig -
+//
+void
+DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont,
+ Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize,
+ Uint16 chintmode, Uint16 chinte)
+{
+ EALLOW;
+
+ //
+ // Set up MODE Register:
+ //
+
+ //
+ // Passed DMA channel as peripheral interrupt source
+ //
+ DmaRegs.CH4.MODE.bit.PERINTSEL = persel;
+
+ //
+ // Peripheral interrupt enable
+ //
+ DmaRegs.CH4.MODE.bit.PERINTE = perinte;
+
+ DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable
+ DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable
+ DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
+
+ //
+ // Sync effects source or destination
+ //
+ DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel;
+
+ //
+ // Enable/disable the overflow interrupt
+ //
+ DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte;
+
+ //
+ // 16-bit/32-bit data size transfers
+ //
+ DmaRegs.CH4.MODE.bit.DATASIZE = datasize;
+
+ //
+ // Generate interrupt to CPU at beginning/end of transfer
+ //
+ DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode;
+
+ //
+ // Channel Interrupt to CPU enable
+ //
+ DmaRegs.CH4.MODE.bit.CHINTE = chinte;
+
+ //
+ // Clear any spurious flags:
+ //
+
+ //
+ // Clear any spurious interrupt flags
+ //
+ DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1;
+
+ DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
+
+ //
+ // Clear any spurious sync error flags
+ //
+ DmaRegs.CH4.CONTROL.bit.ERRCLR = 1;
+
+ //
+ // Initialize PIE vector for CPU interrupt:
+ //
+ PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE
+
+ EDIS;
+}
+
+//
+// StartDMACH4 - This function starts DMA Channel 4.
+//
+void
+StartDMACH4(void)
+{
+ EALLOW;
+ DmaRegs.CH4.CONTROL.bit.RUN = 1;
+ EDIS;
+}
+
+//
+// DMACH5AddrConfig -
+//
+void
+DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+ EALLOW;
+
+ //
+ // Set up SOURCE address:
+ //
+
+ //
+ // Point to beginning of source buffer
+ //
+ DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ //
+ // Set up DESTINATION address:
+ //
+
+ //
+ // Point to beginning of destination buffer
+ //
+ DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ EDIS;
+}
+
+//
+// DMACH5BurstConfig -
+//
+void
+DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+ EALLOW;
+
+ //
+ // Set up BURST registers:
+ //
+
+ //
+ // Number of words(X-1) x-ferred in a burst
+ //
+ DmaRegs.CH5.BURST_SIZE.all = bsize;
+
+ //
+ // Increment source addr between each word x-ferred
+ //
+ DmaRegs.CH5.SRC_BURST_STEP = srcbstep;
+
+ //
+ // Increment dest addr between each word x-ferred
+ //
+ DmaRegs.CH5.DST_BURST_STEP = desbstep;
+
+ EDIS;
+}
+
+//
+// DMACH5TransferConfig -
+//
+void
+DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+ EALLOW;
+
+ //
+ // Set up TRANSFER registers:
+ //
+
+ //
+ // Number of bursts per transfer, DMA interrupt will occur after completed
+ // transfer
+ //
+ DmaRegs.CH5.TRANSFER_SIZE = tsize;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH5.DST_TRANSFER_STEP = deststep;
+
+ EDIS;
+}
+
+//
+// DMACH5WrapConfig -
+//
+void
+DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep)
+{
+ EALLOW;
+
+ //
+ // Set up WRAP registers:
+ //
+ DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts
+ DmaRegs.CH5.SRC_WRAP_STEP = srcwstep;// Step for source wrap
+
+ //
+ // Wrap destination address after N bursts
+ //
+ DmaRegs.CH5.DST_WRAP_SIZE = deswsize;
+
+ DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
+
+ EDIS;
+}
+
+//
+// DMACH5ModeConfig -
+//
+void
+DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont,
+ Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize,
+ Uint16 chintmode, Uint16 chinte)
+{
+ EALLOW;
+
+ //
+ // Set up MODE Register:
+ //
+
+ //
+ // Passed DMA channel as peripheral interrupt source
+ //
+ DmaRegs.CH5.MODE.bit.PERINTSEL = persel;
+
+ //
+ // Peripheral interrupt enable
+ //
+ DmaRegs.CH5.MODE.bit.PERINTE = perinte;
+
+ DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable
+ DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable
+ DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
+
+ //
+ // Sync effects source or destination
+ //
+ DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel;
+
+ //
+ // Enable/disable the overflow interrupt
+ //
+ DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte;
+
+ //
+ // 16-bit/32-bit data size transfers
+ //
+ DmaRegs.CH5.MODE.bit.DATASIZE = datasize;
+
+ //
+ // Generate interrupt to CPU at beginning/end of transfer
+ //
+ DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode;
+
+ //
+ // Channel Interrupt to CPU enable
+ //
+ DmaRegs.CH5.MODE.bit.CHINTE = chinte;
+
+ //
+ // Clear any spurious flags:
+ //
+
+ //
+ // Clear any spurious interrupt flags
+ //
+ DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1;
+
+ DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
+
+ //
+ // Clear any spurious sync error flags
+ //
+ DmaRegs.CH5.CONTROL.bit.ERRCLR = 1;
+
+ //
+ // Initialize PIE vector for CPU interrupt:
+ //
+ PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE
+
+ EDIS;
+}
+
+//
+// StartDMACH5 - This function starts DMA Channel 5.
+//
+void
+StartDMACH5(void)
+{
+ EALLOW;
+ DmaRegs.CH5.CONTROL.bit.RUN = 1;
+ EDIS;
+}
+
+//
+// DMACH6AddrConfig -
+//
+void
+DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+ EALLOW;
+
+ //
+ // Set up SOURCE address:
+ //
+
+ //
+ // Point to beginning of source buffer
+ //
+ DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
+
+ //
+ // Set up DESTINATION address:
+ //
+
+ //
+ // Point to beginning of destination buffer
+ //
+ DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
+
+ EDIS;
+}
+
+//
+// DMACH6BurstConfig -
+//
+void
+DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+ EALLOW;
+
+ //
+ // Set up BURST registers:
+ //
+
+ //
+ // Number of words(X-1) x-ferred in a burst
+ //
+ DmaRegs.CH6.BURST_SIZE.all = bsize;
+
+ //
+ // Increment source addr between each word x-ferred
+ //
+ DmaRegs.CH6.SRC_BURST_STEP = srcbstep;
+
+ //
+ // Increment dest addr between each word x-ferred
+ //
+ DmaRegs.CH6.DST_BURST_STEP = desbstep;
+
+ EDIS;
+}
+
+//
+// DMACH6TransferConfig -
+//
+void
+DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+ EALLOW;
+
+ //
+ // Set up TRANSFER registers:
+ //
+
+ //
+ // Number of bursts per transfer, DMA interrupt will occur after completed
+ // transfer
+ //
+ DmaRegs.CH6.TRANSFER_SIZE = tsize;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep;
+
+ //
+ // TRANSFER_STEP is ignored when WRAP occurs
+ //
+ DmaRegs.CH6.DST_TRANSFER_STEP = deststep;
+
+ EDIS;
+}
+
+//
+// DMACH6WrapConfig -
+//
+void
+DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
+ int16 deswstep)
+{
+ EALLOW;
+
+ //
+ // Set up WRAP registers:
+ //
+ DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts
+ DmaRegs.CH6.SRC_WRAP_STEP = srcwstep;// Step for source wrap
+
+ //
+ // Wrap destination address after N bursts
+ //
+ DmaRegs.CH6.DST_WRAP_SIZE = deswsize;
+
+ DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
+
+ EDIS;
+}
+
+//
+// DMACH6ModeConfig -
+//
+void
+DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont,
+ Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize,
+ Uint16 chintmode, Uint16 chinte)
+{
+ EALLOW;
+
+ //
+ // Set up MODE Register:
+ //
+
+ //
+ // Passed DMA channel as peripheral interrupt source
+ //
+ DmaRegs.CH6.MODE.bit.PERINTSEL = persel;
+
+ //
+ // Peripheral interrupt enable
+ //
+ DmaRegs.CH6.MODE.bit.PERINTE = perinte;
+
+ DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable
+ DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable
+ DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
+
+ //
+ // Sync effects source or destination
+ //
+ DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel;
+
+ //
+ // Enable/disable the overflow interrupt
+ //
+ DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte;
+
+ //
+ // 16-bit/32-bit data size transfers
+ //
+ DmaRegs.CH6.MODE.bit.DATASIZE = datasize;
+
+ //
+ // Generate interrupt to CPU at beginning/end of transfer
+ //
+ DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode;
+
+ //
+ // Channel Interrupt to CPU enable
+ //
+ DmaRegs.CH6.MODE.bit.CHINTE = chinte;
+
+ //
+ // Clear any spurious flags:
+ //
+
+ //
+ // Clear any spurious interrupt flags
+ //
+ DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1;
+
+ DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
+
+ //
+ // Clear any spurious sync error flags
+ //
+ DmaRegs.CH6.CONTROL.bit.ERRCLR = 1;
+
+ //
+ // Initialize PIE vector for CPU interrupt:
+ //
+ PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE
+
+ EDIS;
+}
+
+//
+// StartDMACH6 - This function starts DMA Channel 6.
+//
+void
+StartDMACH6(void)
+{
+ EALLOW;
+ DmaRegs.CH6.CONTROL.bit.RUN = 1;
+ EDIS;
+}
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_DisInt.asm b/bsp/source/DSP2833x_DisInt.asm
new file mode 100644
index 0000000..e5087e9
--- /dev/null
+++ b/bsp/source/DSP2833x_DisInt.asm
@@ -0,0 +1,96 @@
+;// TI File $Revision: /main/1 $
+;// Checkin $Date: August 18, 2006 13:46:09 $
+;//###########################################################################
+;//
+;// FILE: DSP2833x_DisInt.asm
+;//
+;// TITLE: Disable and Restore INTM and DBGM
+;//
+;// Function Prototypes:
+;//
+;// Uint16 DSP28x_DisableInt();
+;// and void DSP28x_RestoreInt(Uint16 Stat0);
+;//
+;// Usage:
+;//
+;// DSP28x_DisableInt() sets both the INTM and DBGM
+;// bits to disable maskable interrupts. Before doing
+;// this, the current value of ST1 is stored on the stack
+;// so that the values can be restored later. The value
+;// of ST1 before the masks are set is returned to the
+;// user in AL. This is then used to restore their state
+;// via the DSP28x_RestoreInt(Uint16 ST1) function.
+;//
+;// Example
+;//
+;// Uint16 StatusReg1
+;// StatusReg1 = DSP28x_DisableInt();
+;//
+;// ... May also want to disable INTM here
+;//
+;// ... code here
+;//
+;// DSP28x_RestoreInt(StatusReg1);
+;//
+;// ... Restore INTM enable
+;//
+;//###########################################################################
+;// $TI Release: F2833x Support Library v2.00.00.00 $
+;// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+;// $Copyright:
+;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+
+
+
+
+ .def _DSP28x_DisableInt
+ .def _DSP28x_RestoreInt
+
+
+_DSP28x_DisableInt:
+ PUSH ST1
+ SETC INTM,DBGM
+ MOV AL, *--SP
+ LRETR
+
+_DSP28x_RestoreInt:
+ MOV *SP++, AL
+ POP ST1
+ LRETR
+
+
+;//===========================================================================
+;// End of file.
+;//===========================================================================
+
+
diff --git a/bsp/source/DSP2833x_ECan.c b/bsp/source/DSP2833x_ECan.c
new file mode 100644
index 0000000..d4bc418
--- /dev/null
+++ b/bsp/source/DSP2833x_ECan.c
@@ -0,0 +1,495 @@
+// TI File $Revision: /main/8 $
+// Checkin $Date: June 25, 2008 15:19:07 $
+//###########################################################################
+//
+// FILE: DSP2833x_ECan.c
+//
+// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitECan - This function initializes the eCAN module to a known state.
+//
+void
+InitECan(void)
+{
+ InitECana();
+#if DSP28_ECANB
+ InitECanb();
+#endif // if DSP28_ECANB
+}
+
+//
+// InitECana - Initialize eCAN-A module
+//
+void
+InitECana(void)
+{
+ //
+ // Create a shadow register structure for the CAN control registers. This
+ // is needed, since only 32-bit access is allowed to these registers.
+ // 16-bit access to these registers could potentially corrupt the register
+ // contents or return false data. This is especially true while writing
+ // to/reading from a bit (or group of bits) among bits 16 - 31
+ //
+ struct ECAN_REGS ECanaShadow;
+
+ EALLOW; // EALLOW enables access to protected bits
+
+ //
+ // Configure eCAN RX and TX pins for CAN operation using eCAN regs
+ //
+ ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
+ ECanaShadow.CANTIOC.bit.TXFUNC = 1;
+ ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
+
+ ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
+ ECanaShadow.CANRIOC.bit.RXFUNC = 1;
+ ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
+
+ //
+ // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
+ // HECC mode also enables time-stamping feature
+ //
+ ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
+ ECanaShadow.CANMC.bit.SCB = 1;
+ ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
+
+ //
+ // Initialize all bits of 'Master Control Field' to zero
+ // Some bits of MSGCTRL register come up in an unknown state. For proper
+ // operation, all bits (including reserved bits) of MSGCTRL must be
+ // initialized to zero
+ //
+ ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
+ ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
+
+ //
+ // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
+ // as a matter of precaution.
+ //
+ ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
+
+ ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
+
+ ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
+ ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
+
+ //
+ // Configure bit timing parameters for eCANA
+ //
+ ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
+ ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
+ ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
+
+ ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+
+ do
+ {
+ ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+ } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set
+
+ ECanaShadow.CANBTC.all = 0;
+
+ //
+ // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
+ //
+ #if (CPU_FRQ_150MHZ)
+ //
+ // The following block for all 150 MHz SYSCLKOUT
+ // (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at End of File
+ //
+ ECanaShadow.CANBTC.bit.BRPREG = 4;
+ ECanaShadow.CANBTC.bit.TSEG2REG = 2;
+ ECanaShadow.CANBTC.bit.TSEG1REG = 10;
+ #endif
+
+ //
+ // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
+ //
+ #if (CPU_FRQ_100MHZ)
+ //
+ // The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).
+ // Bit rate = 1 Mbps See Note at End of File
+ //
+ ECanaShadow.CANBTC.bit.BRPREG = 4;
+ ECanaShadow.CANBTC.bit.TSEG2REG = 1;
+ ECanaShadow.CANBTC.bit.TSEG1REG = 6;
+ #endif
+
+ ECanaShadow.CANBTC.bit.SAM = 1;
+ ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
+
+ ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
+ ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
+ ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
+
+ ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+
+ do
+ {
+ ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+ } while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
+
+ //
+ // Disable all Mailboxes
+ //
+ ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
+
+ EDIS;
+}
+
+#if (DSP28_ECANB)
+//
+// Initialize eCAN-B module
+//
+void
+InitECanb(void)
+{
+ //
+ // Create a shadow register structure for the CAN control registers. This
+ // is needed, since only 32-bit access is allowed to these registers.
+ // 16-bit access to these registers could potentially corrupt the register
+ // contents or return false data. This is especially true while writing
+ // to/reading from a bit (or group of bits) among bits 16 - 31
+ //
+ struct ECAN_REGS ECanbShadow;
+
+ EALLOW; // EALLOW enables access to protected bits
+
+ //
+ // Configure eCAN RX and TX pins for CAN operation using eCAN regs
+ //
+ ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
+ ECanbShadow.CANTIOC.bit.TXFUNC = 1;
+ ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
+
+ ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
+ ECanbShadow.CANRIOC.bit.RXFUNC = 1;
+ ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
+
+ //
+ // Configure eCAN for HECC mode - (read to access mailboxes 16 thru 31)
+ //
+ ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
+ ECanbShadow.CANMC.bit.SCB = 1;
+ ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
+
+ //
+ // Initialize all bits of 'Master Control Field' to zero
+ // Some bits of MSGCTRL register come up in an unknown state. For proper
+ // operation, all bits (including reserved bits) of MSGCTRL must be
+ // initialized to zero
+ //
+ ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
+ ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
+
+ //
+ // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
+ // as a matter of precaution.
+ //
+ ECanbRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
+
+ ECanbRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
+
+ ECanbRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
+ ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
+
+ //
+ // Configure bit timing parameters for eCANB
+ //
+ ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
+ ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
+ ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
+
+ ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+
+ do
+ {
+ ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+ } while(ECanbShadow.CANES.bit.CCE != 1); // Wait for CCE bit to be cleared
+
+ ECanbShadow.CANBTC.all = 0;
+
+ //
+ // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
+ //
+ #if (CPU_FRQ_150MHZ)
+ //
+ // The following block for all 150 MHz SYSCLKOUT
+ // (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at end of file
+ //
+ ECanbShadow.CANBTC.bit.BRPREG = 4;
+ ECanbShadow.CANBTC.bit.TSEG2REG = 2;
+ ECanbShadow.CANBTC.bit.TSEG1REG = 10;
+ #endif
+
+ //
+ // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
+ //
+ #if (CPU_FRQ_100MHZ)
+ //
+ // The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).
+ // Bit rate = 1 Mbps See Note at end of file
+ //
+ ECanbShadow.CANBTC.bit.BRPREG = 4;
+ ECanbShadow.CANBTC.bit.TSEG2REG = 1;
+ ECanbShadow.CANBTC.bit.TSEG1REG = 6;
+ #endif
+
+ ECanbShadow.CANBTC.bit.SAM = 1;
+ ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
+
+ ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
+ ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
+ ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
+
+ ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+
+ do
+ {
+ ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+ } while(ECanbShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
+
+ //
+ // Disable all Mailboxes
+ //
+ ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
+
+ EDIS;
+}
+#endif // if DSP28_ECANB
+
+//
+// InitECanGpio - This function initializes GPIO pins to function as eCAN pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// Only one GPIO pin should be enabled for CANTXA/B operation.
+// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
+// Comment out other unwanted lines.
+//
+void
+InitECanGpio(void)
+{
+ InitECanaGpio();
+#if (DSP28_ECANB)
+ InitECanbGpio();
+#endif // if DSP28_ECANB
+}
+
+//
+// InitECanaGpio - This function initializes GPIO pins to function as eCAN- A
+//
+void
+InitECanaGpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected CAN pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; //Enable pull-up for GPIO31 (CANTXA)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (CANTXA)
+
+ //
+ // Set qualification for selected CAN pins to asynch only
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // This will select asynch (no qualification) for the selected pins.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
+
+ //
+ // Configure eCAN-A pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be eCAN functional
+ // pins.
+ //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA
+
+ EDIS;
+}
+
+#if (DSP28_ECANB)
+//
+// InitECanbGpio - This function initializes GPIO pins to function as eCAN-B
+//
+void
+InitECanbGpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected CAN pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; //Enable pull-up for GPIO8 (CANTXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up for GPIO12(CANTXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up for GPIO16(CANTXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; //Enable pull-up for GPIO20(CANTXB)
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10(CANRXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13(CANRXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17(CANRXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21(CANRXB)
+
+ //
+ // Set qualification for selected CAN pins to asynch only
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
+
+ //
+ // Configure eCAN-B pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be eCAN functional
+ // pins.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB
+
+ EDIS;
+}
+#endif // if DSP28_ECANB
+
+//
+// Note: Bit timing parameters must be chosen based on the network parameters
+// such as the sampling point desired and the propagation delay of the network.
+// The propagation delay is a function of length of the cable, delay introduced
+// by the transceivers and opto/galvanic-isolators (if any).
+//
+// The parameters used in this file must be changed taking into account the
+// above mentioned factors in order to arrive at the bit-timing parameters
+// suitable for a network.
+//
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_ECap.c b/bsp/source/DSP2833x_ECap.c
new file mode 100644
index 0000000..1be462d
--- /dev/null
+++ b/bsp/source/DSP2833x_ECap.c
@@ -0,0 +1,304 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 15, 2007 16:54:36 $
+//###########################################################################
+//
+// FILE: DSP2833x_ECap.c
+//
+// TITLE: DSP2833x eCAP Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitECap - This function initializes the eCAP(s) to a known state.
+//
+void
+InitECap(void)
+{
+ //
+ // Initialize eCAP1/2/3
+ //
+}
+
+//
+// InitECapGpio - This function initializes GPIO pins to function as ECAP pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// For each eCAP peripheral
+// Only one GPIO pin should be enabled for ECAP operation.
+// Comment out other unwanted lines.
+//
+void
+InitECapGpio()
+{
+ InitECap1Gpio();
+#if (DSP28_ECAP2)
+ InitECap2Gpio();
+#endif // endif DSP28_ECAP2
+#if (DSP28_ECAP3)
+ InitECap3Gpio();
+#endif // endif DSP28_ECAP3
+#if (DSP28_ECAP4)
+ InitECap4Gpio();
+#endif // endif DSP28_ECAP4
+#if (DSP28_ECAP5)
+ InitECap5Gpio();
+#endif // endif DSP28_ECAP5
+#if (DSP28_ECAP6)
+ InitECap6Gpio();
+#endif // endif DSP28_ECAP6
+}
+
+//
+// InitECap1Gpio -
+//
+void
+InitECap1Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ //GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1)
+ GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1)
+
+ //
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // Comment out other unwanted lines.
+ //
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; //Synch to SYSCLKOUT GPIO5 (CAP1)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; //Synch to SYSCLKOUT GPIO24 (CAP1)
+ //GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; //Synch to SYSCLKOUT GPIO34 (CAP1)
+
+ //
+ // Configure eCAP-1 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be eCAP1 functional pins.
+ // Comment out other unwanted lines.
+ //
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1
+ GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1
+ //GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1
+
+ EDIS;
+}
+
+#if DSP28_ECAP2
+//
+// InitECap2Gpio -
+//
+void
+InitECap2Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2)
+
+ //
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; //Synch to SYSCLKOUT GPIO7 (CAP2)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; //Synch to SYSCLKOUT GPIO25 (CAP2)
+ //GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; //Synch to SYSCLKOUT GPIO37 (CAP2)
+
+ //
+ // Configure eCAP-2 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be eCAP2 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2
+ //GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2
+
+ EDIS;
+}
+#endif // endif DSP28_ECAP2
+
+#if DSP28_ECAP3
+//
+// InitECap3Gpio -
+//
+void
+InitECap3Gpio(void)
+{
+ EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3)
+// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3)
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3)
+
+/* Configure eCAP-3 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP3 functional pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3
+// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3
+
+ EDIS;
+}
+#endif // endif DSP28_ECAP3
+
+
+#if DSP28_ECAP4
+void InitECap4Gpio(void)
+{
+ EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4)
+// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4)
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4)
+
+/* Configure eCAP-4 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP4 functional pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4
+// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4
+
+ EDIS;
+}
+#endif // endif DSP28_ECAP4
+
+
+#if DSP28_ECAP5
+void InitECap5Gpio(void)
+{
+ EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5)
+// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5)
+// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5)
+
+/* Configure eCAP-5 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP5 functional pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5
+// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5
+
+ EDIS;
+}
+#endif // endif DSP28_ECAP5
+
+
+#if DSP28_ECAP6
+void InitECap6Gpio(void)
+{
+ EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6)
+// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6)
+// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6)
+
+/* Configure eCAP-5 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP6 functional pins.
+// Comment out other unwanted lines.
+
+ GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6
+// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6
+
+ EDIS;
+}
+#endif // endif DSP28_ECAP6
+
+
+
+//===========================================================================
+// End of file.
+//===========================================================================
diff --git a/bsp/source/DSP2833x_EPwm.c b/bsp/source/DSP2833x_EPwm.c
new file mode 100644
index 0000000..de2c28b
--- /dev/null
+++ b/bsp/source/DSP2833x_EPwm.c
@@ -0,0 +1,407 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:19 $
+//###########################################################################
+//
+// FILE: DSP2833x_EPwm.c
+//
+// TITLE: DSP2833x ePWM Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitEPwm - This function initializes the ePWM(s) to a known state.
+//
+void
+InitEPwm(void)
+{
+ //
+ // Initialize ePWM1/2/3/4/5/6
+ //
+}
+
+//
+// InitEPwmGpio - This function initializes GPIO pins to function as ePWM pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+void
+InitEPwmGpio(void)
+{
+ InitEPwm1Gpio();
+ InitEPwm2Gpio();
+ InitEPwm3Gpio();
+#if DSP28_EPWM4
+ InitEPwm4Gpio();
+#endif // endif DSP28_EPWM4
+#if DSP28_EPWM5
+ InitEPwm5Gpio();
+#endif // endif DSP28_EPWM5
+#if DSP28_EPWM6
+ InitEPwm6Gpio();
+#endif // endif DSP28_EPWM6
+}
+
+//
+// InitEPwm1Gpio - This function initializes GPIO pins to function as ePWM1
+//
+void
+InitEPwm1Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B)
+
+ //
+ // Configure ePWM-1 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be ePWM1 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
+
+ EDIS;
+}
+
+//
+// InitEPwm2Gpio - This function initializes GPIO pins to function as ePWM2
+//
+void
+InitEPwm2Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B)
+
+ //
+ // Configure ePWM-2 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be ePWM2 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
+
+ EDIS;
+}
+
+//
+// InitEPwm3Gpio - This function initializes GPIO pins to function as ePWM3
+//
+void
+InitEPwm3Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B)
+
+ //
+ // Configure ePWM-3 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be ePWM3 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
+
+ EDIS;
+}
+
+#if DSP28_EPWM4
+//
+// InitEPwm4Gpio - This function initializes GPIO pins to function as ePWM4
+//
+void
+InitEPwm4Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B)
+
+ //
+ // Configure ePWM-4 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be ePWM4 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
+
+ EDIS;
+}
+#endif // endif DSP28_EPWM4
+
+#if DSP28_EPWM5
+//
+// InitEPwm5Gpio - This function initializes GPIO pins to function as ePWM5
+//
+void
+InitEPwm5Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B)
+
+ //
+ // Configure ePWM-5 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be ePWM5 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
+
+ EDIS;
+}
+#endif // endif DSP28_EPWM5
+
+#if DSP28_EPWM6
+//
+// InitEPwm6Gpio - This function initializes GPIO pins to function as ePWM6
+//
+void
+InitEPwm6Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B)
+
+ //
+ // Configure ePWM-6 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be ePWM6 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
+ GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
+
+ EDIS;
+}
+#endif // endif DSP28_EPWM6
+
+//
+// InitEPwmSyncGpio - This function initializes GPIO pins to function as ePWM
+// Synch pins
+//
+void
+InitEPwmSyncGpio(void)
+{
+ EALLOW;
+
+ //
+ // Configure EPWMSYNCI
+ //
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; //Enable pull-up on GPIO6 (EPWMSYNCI)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;//Enable pull-up on GPIO32 (EPWMSYNCI)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // This will select synch to SYSCLKOUT for the selected pins.
+ // Comment out other unwanted lines.
+ //
+
+ //
+ // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI)
+ //
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0;
+
+ //
+ //Synch to SYSCLKOUT GPIO32 (EPWMSYNCI)
+ //
+ //GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0;
+
+ //
+ // Configure EPwmSync pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be EPwmSync
+ // functional pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; //Enable pull-up on GPIO6(EPWMSYNCI)
+ //GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;//Enable pull-up on GPIO32(EPWMSYNCI)
+
+ //
+ // Configure EPWMSYNC0
+ //
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+
+ //
+ // Enable pull-up on GPIO6 (EPWMSYNC0)
+ //
+ //GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;
+
+ //
+ // Enable pull-up on GPIO33 (EPWMSYNC0)
+ //
+ GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;
+
+ //
+ // Enable pull-up on GPIO6 (EPWMSYNC0)
+ //
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3;
+
+ //
+ // Enable pull-up on GPIO33 (EPWMSYNC0)
+ //
+ GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2;
+}
+
+//
+// InitTzGpio - This function initializes GPIO pins to function as Trip Zone
+// (TZ) pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+void
+InitTzGpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1)
+ GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2)
+ GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3)
+ GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4)
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5)
+
+ GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4)
+
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5)
+
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6)
+
+ //
+ // Configure TZ pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be TZ functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1
+ GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2
+ GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3
+ GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4
+
+ GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5
+
+ GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6
+
+ EDIS;
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_EQep.c b/bsp/source/DSP2833x_EQep.c
new file mode 100644
index 0000000..38ffa0e
--- /dev/null
+++ b/bsp/source/DSP2833x_EQep.c
@@ -0,0 +1,191 @@
+// TI File $Revision: /main/3 $
+// Checkin $Date: July 27, 2007 11:55:20 $
+//###########################################################################
+//
+// FILE: DSP2833x_EQep.c
+//
+// TITLE: DSP2833x eQEP Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitEQep - This function initializes the eQEP(s) to a known state.
+//
+void
+InitEQep(void)
+{
+ //
+ // Initialize eQEP1/2
+ //
+}
+
+//
+// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// For each eQEP peripheral
+// Only one GPIO pin should be enabled for EQEPxA operation.
+// Only one GPIO pin should be enabled for EQEPxB operation.
+// Only one GPIO pin should be enabled for EQEPxS operation.
+// Only one GPIO pin should be enabled for EQEPxI operation.
+// Comment out other unwanted lines.
+//
+void
+InitEQepGpio()
+{
+#if DSP28_EQEP1
+ InitEQep1Gpio();
+#endif // endif DSP28_EQEP1
+#if DSP28_EQEP2
+ InitEQep2Gpio();
+#endif // endif DSP28_EQEP2
+}
+
+//
+// InitEQep1Gpio - This function initializes GPIO pins to function as eQEP1
+//
+#if DSP28_EQEP1
+void
+InitEQep1Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B)
+ GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S)
+ GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I)
+
+ //
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I)
+
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; //Sync to SYSCLKOUT GPIO50(EQEP1A)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; //Sync to SYSCLKOUT GPIO51(EQEP1B)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; //Sync to SYSCLKOUT GPIO52(EQEP1S)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; //Sync to SYSCLKOUT GPIO53(EQEP1I)
+
+ //
+ // Configure eQEP-1 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be eQEP1 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A
+ GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B
+ GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S
+ GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I
+
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I
+
+ EDIS;
+}
+#endif // if DSP28_EQEP1
+
+//
+// InitEQep2Gpio - This function initializes GPIO pins to function as eQEP2
+//
+#if DSP28_EQEP2
+void
+InitEQep2Gpio(void)
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A)
+ GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B)
+ GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I)
+ GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S)
+
+ //
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S)
+
+ //
+ // Configure eQEP-2 pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be eQEP2 functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
+ GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
+ GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I
+ GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S
+
+ EDIS;
+}
+#endif // endif DSP28_EQEP2
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_GlobalVariableDefs.c b/bsp/source/DSP2833x_GlobalVariableDefs.c
new file mode 100644
index 0000000..0dc9084
--- /dev/null
+++ b/bsp/source/DSP2833x_GlobalVariableDefs.c
@@ -0,0 +1,407 @@
+// TI File $Revision: /main/4 $
+// Checkin $Date: June 2, 2008 11:12:33 $
+//###########################################################################
+//
+// FILE: DSP2833x_GlobalVariableDefs.c
+//
+// TITLE: DSP2833x Global Variables and Data Section Pragmas.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+
+//
+// Define Global Peripheral Variables
+//
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcRegsFile")
+#else
+#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
+#endif
+volatile struct ADC_REGS AdcRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("AdcMirrorFile")
+#else
+#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile");
+#endif
+volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer0RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer0Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer1RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer1Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("CpuTimer2RegsFile")
+#else
+#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
+#endif
+volatile struct CPUTIMER_REGS CpuTimer2Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("CsmPwlFile")
+#else
+#pragma DATA_SECTION(CsmPwl,"CsmPwlFile");
+#endif
+volatile struct CSM_PWL CsmPwl;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("CsmRegsFile")
+#else
+#pragma DATA_SECTION(CsmRegs,"CsmRegsFile");
+#endif
+volatile struct CSM_REGS CsmRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("DevEmuRegsFile")
+#else
+#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile");
+#endif
+volatile struct DEV_EMU_REGS DevEmuRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("DmaRegsFile")
+#else
+#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
+#endif
+volatile struct DMA_REGS DmaRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaRegsFile")
+#else
+#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile");
+#endif
+volatile struct ECAN_REGS ECanaRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaMboxesFile")
+#else
+#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile");
+#endif
+volatile struct ECAN_MBOXES ECanaMboxes;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaLAMRegsFile")
+#else
+#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile");
+#endif
+volatile struct LAM_REGS ECanaLAMRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaMOTSRegsFile")
+#else
+#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile");
+#endif
+volatile struct MOTS_REGS ECanaMOTSRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanaMOTORegsFile")
+#else
+#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile");
+#endif
+volatile struct MOTO_REGS ECanaMOTORegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbRegsFile")
+#else
+#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile");
+#endif
+volatile struct ECAN_REGS ECanbRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbMboxesFile")
+#else
+#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile");
+#endif
+volatile struct ECAN_MBOXES ECanbMboxes;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbLAMRegsFile")
+#else
+#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile");
+#endif
+volatile struct LAM_REGS ECanbLAMRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbMOTSRegsFile")
+#else
+#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile");
+#endif
+volatile struct MOTS_REGS ECanbMOTSRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECanbMOTORegsFile")
+#else
+#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile");
+#endif
+volatile struct MOTO_REGS ECanbMOTORegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm1RegsFile")
+#else
+#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm1Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm2RegsFile")
+#else
+#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm2Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm3RegsFile")
+#else
+#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm3Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm4RegsFile")
+#else
+#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm4Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm5RegsFile")
+#else
+#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm5Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EPwm6RegsFile")
+#else
+#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
+#endif
+volatile struct EPWM_REGS EPwm6Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap1RegsFile")
+#else
+#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
+#endif
+volatile struct ECAP_REGS ECap1Regs;
+
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap2RegsFile")
+#else
+#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
+#endif
+volatile struct ECAP_REGS ECap2Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap3RegsFile")
+#else
+#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
+#endif
+volatile struct ECAP_REGS ECap3Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap4RegsFile")
+#else
+#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
+#endif
+volatile struct ECAP_REGS ECap4Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap5RegsFile")
+#else
+#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
+#endif
+volatile struct ECAP_REGS ECap5Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ECap6RegsFile")
+#else
+#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
+#endif
+volatile struct ECAP_REGS ECap6Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep1RegsFile")
+#else
+#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
+#endif
+volatile struct EQEP_REGS EQep1Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("EQep2RegsFile")
+#else
+#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
+#endif
+volatile struct EQEP_REGS EQep2Regs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioCtrlRegsFile")
+#else
+#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
+#endif
+volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioDataRegsFile")
+#else
+#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
+#endif
+volatile struct GPIO_DATA_REGS GpioDataRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("GpioIntRegsFile")
+#else
+#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile");
+#endif
+volatile struct GPIO_INT_REGS GpioIntRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("I2caRegsFile")
+#else
+#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
+#endif
+volatile struct I2C_REGS I2caRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("McbspaRegsFile")
+#else
+#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
+#endif
+volatile struct MCBSP_REGS McbspaRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("McbspbRegsFile")
+#else
+#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
+#endif
+volatile struct MCBSP_REGS McbspbRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("PartIdRegsFile")
+#else
+#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile");
+#endif
+volatile struct PARTID_REGS PartIdRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("PieCtrlRegsFile")
+#else
+#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
+#endif
+volatile struct PIE_CTRL_REGS PieCtrlRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("PieVectTableFile")
+#else
+#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
+#endif
+volatile struct PIE_VECT_TABLE PieVectTable;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("SciaRegsFile")
+#else
+#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
+#endif
+volatile struct SCI_REGS SciaRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScibRegsFile")
+#else
+#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
+#endif
+volatile struct SCI_REGS ScibRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("ScicRegsFile")
+#else
+#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
+#endif
+volatile struct SCI_REGS ScicRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("SpiaRegsFile")
+#else
+#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
+#endif
+volatile struct SPI_REGS SpiaRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("SysCtrlRegsFile")
+#else
+#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile");
+#endif
+volatile struct SYS_CTRL_REGS SysCtrlRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("FlashRegsFile")
+#else
+#pragma DATA_SECTION(FlashRegs,"FlashRegsFile");
+#endif
+volatile struct FLASH_REGS FlashRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("XIntruptRegsFile")
+#else
+#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile");
+#endif
+volatile struct XINTRUPT_REGS XIntruptRegs;
+
+#ifdef __cplusplus
+#pragma DATA_SECTION("XintfRegsFile")
+#else
+#pragma DATA_SECTION(XintfRegs,"XintfRegsFile");
+#endif
+volatile struct XINTF_REGS XintfRegs;
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_Gpio.c b/bsp/source/DSP2833x_Gpio.c
new file mode 100644
index 0000000..c4da8a4
--- /dev/null
+++ b/bsp/source/DSP2833x_Gpio.c
@@ -0,0 +1,108 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:25 $
+//###########################################################################
+//
+// FILE: DSP2833x_Gpio.c
+//
+// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitGpio - This function initializes the Gpio to a known (default) state.
+//
+// For more details on configuring GPIO's as peripheral functions,
+// refer to the individual peripheral examples and/or GPIO setup example.
+//
+void
+InitGpio(void)
+{
+ EALLOW;
+
+ //
+ // Each GPIO pin can be:
+ // a) a GPIO input/output
+ // b) peripheral function 1
+ // c) peripheral function 2
+ // d) peripheral function 3
+ // By default, all are GPIO Inputs
+ //
+ GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15
+ GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31
+ GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39
+ GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63
+ GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79
+ GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95
+
+ GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs
+ GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs
+ GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs
+
+ //
+ // Each input can have different qualification
+ // a) input synchronized to SYSCLKOUT
+ // b) input qualified by a sampling window
+ // c) input sent asynchronously (valid for peripheral inputs only)
+ //
+ GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT
+ GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT
+ GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT
+ GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT
+
+ //
+ // Pull-ups can be enabled or disabled
+ //
+ GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31
+ GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63
+ GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79
+ //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31
+ //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34
+ //GpioCtrlRegs.GPCPUD.all = 0xFFFF; // Pullup's disabled GPIO64-GPIO79
+
+ EDIS;
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_I2C.c b/bsp/source/DSP2833x_I2C.c
new file mode 100644
index 0000000..ec364cd
--- /dev/null
+++ b/bsp/source/DSP2833x_I2C.c
@@ -0,0 +1,110 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:27 $
+//###########################################################################
+//
+// FILE: DSP2833x_I2C.c
+//
+// TITLE: DSP2833x SCI Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitI2C - This function initializes the I2C to a known state.
+//
+void
+InitI2C(void)
+{
+ //
+ // Initialize I2C-A
+ //
+}
+
+//
+// InitI2CGpio - This function initializes GPIO pins to function as I2C pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// Only one GPIO pin should be enabled for SDAA operation.
+// Only one GPIO pin shoudl be enabled for SCLA operation.
+// Comment out other unwanted lines.
+//
+void
+InitI2CGpio()
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
+ GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
+ GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
+
+ //
+ // Configure SCI pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be I2C functional
+ // pins. Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 to SDAA
+ GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 to SCLA
+
+ EDIS;
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_Mcbsp.c b/bsp/source/DSP2833x_Mcbsp.c
new file mode 100644
index 0000000..c7d465e
--- /dev/null
+++ b/bsp/source/DSP2833x_Mcbsp.c
@@ -0,0 +1,552 @@
+// TI File $Revision: /main/16 $
+// Checkin $Date: October 3, 2007 14:50:19 $
+//###########################################################################
+//
+// FILE: DSP2833x_McBSP.c
+//
+// TITLE: DSP2833x Device McBSP Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
+// generator (SRG) cycles required for the Mcbsp initialization routine.
+// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
+// generator (CLKG) cycles required for the Mcbsp initialization routine.
+// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY
+// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT
+//
+
+//
+// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h
+//
+
+//
+// For 150 MHz SYSCLKOUT(default)
+//
+#if CPU_FRQ_150MHZ
+ #define CPU_SPD 150E6
+
+ //
+ // SRG input is LSPCLK (SYSCLKOUT/4) for examples
+ //
+ #define MCBSP_SRG_FREQ CPU_SPD/4
+#endif
+
+//
+// For 100 MHz SYSCLKOUT
+//
+#if CPU_FRQ_100MHZ
+ #define CPU_SPD 100E6
+
+ //
+ // SRG input is LSPCLK (SYSCLKOUT/4) for examples
+ //
+ #define MCBSP_SRG_FREQ CPU_SPD/4
+#endif
+
+#define CLKGDV_VAL 1
+
+//
+// # of CPU cycles in 2 SRG cycles-init delay
+//
+#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ)
+
+//
+// # of CPU cycles in 2 CLKG cycles-init delay
+//
+#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL)))
+
+//
+// Function Prototypes
+//
+void delay_loop(void); // Delay function used for SRG initialization
+void clkg_delay_loop(void); // Delay function used for CLKG initialization
+
+//
+// InitMcbsp - This function initializes the McBSP to a known state.
+//
+void InitMcbsp(void)
+{
+ InitMcbspa();
+#if DSP28_MCBSPB
+ InitMcbspb();
+#endif // end DSP28_MCBSPB
+}
+
+//
+// InitMcbspa - This function initializes McBSPa to a known state.
+//
+void
+InitMcbspa(void)
+{
+ //
+ // McBSP-A register settings
+ //
+
+ //
+ // Reset FS generator, sample rate generator & transmitter
+ //
+ McbspaRegs.SPCR2.all=0x0000;
+
+ McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
+
+ //
+ // Enable loopback mode for test.
+ // Comment out for normal McBSP transfer mode.
+ //
+ McbspaRegs.SPCR1.bit.DLB = 1;
+
+ McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
+
+ //
+ // Single-phase frame, 1 word/frame, No companding (Receive)
+ //
+ McbspaRegs.RCR2.all=0x0;
+ McbspaRegs.RCR1.all=0x0;
+
+ //
+ // Single-phase frame, 1 word/frame, No companding (Transmit)
+ //
+ McbspaRegs.XCR2.all=0x0;
+ McbspaRegs.XCR1.all=0x0;
+
+ //
+ // FSX generated internally, FSR derived from an external source
+ //
+ McbspaRegs.PCR.bit.FSXM = 1;
+
+ //
+ // CLKX generated internally, CLKR derived from an external source
+ //
+ McbspaRegs.PCR.bit.CLKXM = 1;
+
+ //
+ // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
+ //
+ McbspaRegs.SRGR2.bit.CLKSM = 1;
+
+ McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
+
+ McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
+
+ //
+ // CLKG frequency = LSPCLK/(CLKGDV+1)
+ //
+ McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
+
+ delay_loop(); // Wait at least 2 SRG clock cycles
+
+ McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
+ clkg_delay_loop(); // Wait at least 2 CLKG cycles
+ McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
+ McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
+ McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
+}
+
+//
+// InitMcbspb - This function initializes McBSPb to a known state.
+//
+#if (DSP28_MCBSPB)
+void
+InitMcbspb(void)
+{
+ //
+ // McBSP-B register settings
+ //
+
+ //
+ // Reset FS generator, sample rate generator & transmitter
+ //
+ McbspbRegs.SPCR2.all=0x0000;
+
+ McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
+
+ //
+ // Enable loopback mode for test.
+ // Comment out for normal McBSP transfer mode.
+ //
+ McbspbRegs.SPCR1.bit.DLB = 1;
+
+ McbspbRegs.MFFINT.all=0x0; // Disable all interrupts
+
+ //
+ // Single-phase frame, 1 word/frame, No companding (Receive)
+ //
+ McbspbRegs.RCR2.all=0x0;
+ McbspbRegs.RCR1.all=0x0;
+
+ //
+ // Single-phase frame, 1 word/frame, No companding (Transmit)
+ //
+ McbspbRegs.XCR2.all=0x0;
+ McbspbRegs.XCR1.all=0x0;
+
+ //
+ // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
+ //
+ McbspbRegs.SRGR2.bit.CLKSM = 1;
+ McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
+
+ McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
+
+ //
+ // CLKG frequency = LSPCLK/(CLKGDV+1)
+ //
+ McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
+
+ //
+ // FSX generated internally, FSR derived from an external source
+ //
+ McbspbRegs.PCR.bit.FSXM = 1;
+
+ //
+ // CLKX generated internally, CLKR derived from an external source
+ //
+ McbspbRegs.PCR.bit.CLKXM = 1;
+
+ delay_loop(); // Wait at least 2 SRG clock cycles
+ McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
+ clkg_delay_loop(); // Wait at least 2 CLKG cycles
+ McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
+ McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
+ McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
+}
+#endif // end DSP28_MCBSPB
+
+//
+// InitMcbspa8bit - McBSP-A 8-bit Length
+//
+void
+InitMcbspa8bit(void)
+{
+ McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
+ McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
+}
+
+//
+// InitMcbspa12bit - McBSP-A 12 bit Length
+//
+void
+InitMcbspa12bit(void)
+{
+ McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
+ McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
+}
+
+//
+// InitMcbspa16bit - McBSP-A 16 bit Length
+//
+void
+InitMcbspa16bit(void)
+{
+ McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
+ McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
+}
+
+//
+// InitMcbspa20bit - McBSP-A 20 bit Length
+//
+void
+InitMcbspa20bit(void)
+{
+ McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
+ McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
+}
+
+//
+// InitMcbspa24bit - McBSP-A 24 bit Length
+//
+void
+InitMcbspa24bit(void)
+{
+ McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
+ McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
+}
+
+//
+// InitMcbspa32bit - McBSP-A 32 bit Length
+//
+void
+InitMcbspa32bit(void)
+{
+ McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
+ McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
+}
+
+//
+// McBSP-B Data Lengths
+//
+#if (DSP28_MCBSPB)
+//
+// InitMcbspb8bit - McBSP-B 8-bit Length
+//
+void
+InitMcbspb8bit(void)
+{
+ McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
+ McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
+}
+
+//
+// InitMcbspb12bit - McBSP-B 12 bit Length
+//
+void
+InitMcbspb12bit(void)
+{
+ McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
+ McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
+}
+
+//
+// InitMcbspb16bit - McBSP-B 16 bit Length
+//
+void
+InitMcbspb16bit(void)
+{
+ McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
+ McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
+}
+
+//
+// InitMcbspb20bit - McBSP-B 20 bit Length
+//
+void
+InitMcbspb20bit(void)
+{
+ McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
+ McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
+}
+
+//
+// InitMcbspb24bit - McBSP-B 24 bit Length
+//
+void
+InitMcbspb24bit(void)
+{
+ McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
+ McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
+}
+
+//
+// InitMcbspb32bit - McBSP-B 32 bit Length
+//
+void
+InitMcbspb32bit(void)
+{
+ McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
+ McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
+}
+
+#endif //end DSP28_MCBSPB
+
+//
+// InitMcbspGpio -
+//
+void
+InitMcbspGpio(void)
+{
+ InitMcbspaGpio();
+#if DSP28_MCBSPB
+ InitMcbspbGpio();
+#endif // end DSP28_MCBSPB
+}
+
+//
+// InitMcbspaGpio - This function initializes GPIO pins to function as McBSP-A
+//
+void
+InitMcbspaGpio(void)
+{
+ EALLOW;
+
+ //
+ // Configure McBSP-A pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be McBSP functional
+ // pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin
+ GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin
+ GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA)
+
+ //
+ // Set qualification for selected input pins to asynch only
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA)
+
+ EDIS;
+}
+
+//
+// InitMcbspbGpio - This function initializes GPIO pins to function as McBSP-B
+//
+#if DSP28_MCBSPB
+void
+InitMcbspbGpio(void)
+{
+ EALLOW;
+
+ //
+ // Configure McBSP-A pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be McBSP functional
+ // pins.
+ // Comment out other unwanted lines.
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin
+ GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin
+ GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin
+ GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; //Enable pull-up on GPIO24 (MDXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up on GPIO12 (MDXB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; //Enable pull-up on GPIO25 (MDRB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; //Enable pull-up on GPIO13 (MDRB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; //Enable pull-up on GPIO26 (MCLKXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; //Enable pull-up on GPIO14 (MCLKXB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; //Enable pull-up on GPIO3 (MCLKRB)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; //Enable pull-up on GPIO60 (MCLKRB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; //Enable pull-up on GPIO27 (MFSXB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; //Enable pull-up on GPIO15 (MFSXB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; //Enable pull-up on GPIO1 (MFSRB)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; //Enable pull-up on GPIO61 (MFSRB)
+
+ //
+ // Set qualification for selected input pins to asynch only
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB)
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB)
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB)
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB)
+ GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB)
+
+ EDIS;
+}
+#endif // end DSP28_MCBSPB
+
+//
+// delay_loop -
+//
+void
+delay_loop(void)
+{
+ long i;
+
+ //
+ // delay in McBsp init. must be at least 2 SRG cycles
+ //
+ for (i = 0; i < MCBSP_INIT_DELAY; i++)
+ {
+
+ }
+}
+
+//
+// clkg_delay_loop -
+//
+void
+clkg_delay_loop(void)
+{
+ long i;
+
+ //
+ // delay in McBsp init. must be at least 2 SRG cycles
+ //
+ for (i = 0; i < MCBSP_CLKG_DELAY; i++)
+ {
+
+ }
+}
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_MemCopy.c b/bsp/source/DSP2833x_MemCopy.c
new file mode 100644
index 0000000..0463eaa
--- /dev/null
+++ b/bsp/source/DSP2833x_MemCopy.c
@@ -0,0 +1,81 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:33 $
+//###########################################################################
+//
+// FILE: DSP2833x_MemCopy.c
+//
+// TITLE: Memory Copy Utility
+//
+// ASSUMPTIONS:
+//
+// DESCRIPTION:
+//
+// This function will copy the specified memory contents from
+// one location to another.
+//
+// Uint16 *SourceAddr Pointer to the first word to be moved
+// SourceAddr < SourceEndAddr
+// Uint16* SourceEndAddr Pointer to the last word to be moved
+// Uint16* DestAddr Pointer to the first destination word
+//
+// No checks are made for invalid memory locations or that the
+// end address is > then the first start address.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h"
+
+//
+// MemCopy -
+//
+void
+MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
+{
+ while(SourceAddr < SourceEndAddr)
+ {
+ *DestAddr++ = *SourceAddr++;
+ }
+ return;
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_PieCtrl.c b/bsp/source/DSP2833x_PieCtrl.c
new file mode 100644
index 0000000..a3dc719
--- /dev/null
+++ b/bsp/source/DSP2833x_PieCtrl.c
@@ -0,0 +1,126 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:35 $
+//###########################################################################
+//
+// FILE: DSP2833x_PieCtrl.c
+//
+// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitPieCtrl - This function initializes the PIE control registers to a known
+// state.
+//
+void
+InitPieCtrl(void)
+{
+ //
+ // Disable Interrupts at the CPU level
+ //
+ DINT;
+
+ //
+ // Disable the PIE
+ //
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
+
+ //
+ // Clear all PIEIER registers
+ //
+ PieCtrlRegs.PIEIER1.all = 0;
+ PieCtrlRegs.PIEIER2.all = 0;
+ PieCtrlRegs.PIEIER3.all = 0;
+ PieCtrlRegs.PIEIER4.all = 0;
+ PieCtrlRegs.PIEIER5.all = 0;
+ PieCtrlRegs.PIEIER6.all = 0;
+ PieCtrlRegs.PIEIER7.all = 0;
+ PieCtrlRegs.PIEIER8.all = 0;
+ PieCtrlRegs.PIEIER9.all = 0;
+ PieCtrlRegs.PIEIER10.all = 0;
+ PieCtrlRegs.PIEIER11.all = 0;
+ PieCtrlRegs.PIEIER12.all = 0;
+
+ //
+ // Clear all PIEIFR registers
+ //
+ PieCtrlRegs.PIEIFR1.all = 0;
+ PieCtrlRegs.PIEIFR2.all = 0;
+ PieCtrlRegs.PIEIFR3.all = 0;
+ PieCtrlRegs.PIEIFR4.all = 0;
+ PieCtrlRegs.PIEIFR5.all = 0;
+ PieCtrlRegs.PIEIFR6.all = 0;
+ PieCtrlRegs.PIEIFR7.all = 0;
+ PieCtrlRegs.PIEIFR8.all = 0;
+ PieCtrlRegs.PIEIFR9.all = 0;
+ PieCtrlRegs.PIEIFR10.all = 0;
+ PieCtrlRegs.PIEIFR11.all = 0;
+ PieCtrlRegs.PIEIFR12.all = 0;
+}
+
+//
+// EnableInterrupts - This function enables the PIE module and CPU interrupts
+//
+void
+EnableInterrupts()
+{
+ //
+ // Enable the PIE
+ //
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+
+ //
+ // Enables PIE to drive a pulse into the CPU
+ //
+ PieCtrlRegs.PIEACK.all = 0xFFFF;
+
+ //
+ // Enable Interrupts at the CPU level
+ //
+ EINT;
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_SWPrioritizedDefaultIsr.c b/bsp/source/DSP2833x_SWPrioritizedDefaultIsr.c
new file mode 100644
index 0000000..307f3d4
--- /dev/null
+++ b/bsp/source/DSP2833x_SWPrioritizedDefaultIsr.c
@@ -0,0 +1,2670 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: January 14, 2008 11:28:12 $
+//###########################################################################
+//
+// FILE: DSP2833x_SWPrioritizedDefaultIsr.c
+//
+// TITLE: DSP2833x Device Default Software Prioritized Interrupt
+// Service Routines.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+//
+// INT13_ISR - Connected to INT13 of CPU (use MINT13 mask):
+// Note CPU-Timer1 is reserved for TI use, however XINT13
+// ISR can be used by the user.
+//
+#if (INT13PL != 0)
+interrupt void
+INT13_ISR(void) // INT13 or CPU-Timer1
+{
+ IER |= MINT13; // Set "global" priority
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// INT14_ISR - Connected to INT14 of CPU (use MINT14 mask):
+//
+#if (INT14PL != 0)
+interrupt void
+INT14_ISR(void) // CPU-Timer2
+{
+ IER |= MINT14; // Set "global" priority
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// DATALOG_ISR - Connected to INT15 of CPU (use MINT15 mask):
+//
+#if (INT15PL != 0)
+interrupt void
+DATALOG_ISR(void) // Datalogging interrupt
+{
+ IER |= MINT15; // Set "global" priority
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// RTOSINT_ISR - Connected to INT16 of CPU (use MINT16 mask):
+//
+#if (INT16PL != 0)
+interrupt void
+RTOSINT_ISR(void) // RTOS interrupt
+{
+ IER |= MINT16; // Set "global" priority
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EMUINT_ISR - Emulation interrupt is connected to EMUINT of CPU(non-maskable)
+//
+interrupt void
+EMUINT_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// NMI_ISR - Non-maskable interrupt is connected to NMI of CPU (non-maskable):
+//
+interrupt void
+NMI_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);;
+}
+
+//
+// ILLEGAL_ISR - Illegal operation TRAP
+//
+interrupt void
+ILLEGAL_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER1_ISR - User Defined trap 1
+//
+interrupt void
+USER1_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER2_ISR - User Defined trap 2
+//
+interrupt void
+USER2_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER3_ISR - User Defined trap 3
+//
+interrupt void
+USER3_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER4_ISR - User Defined trap 4
+//
+interrupt void
+USER4_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER5_ISR - User Defined trap 5
+//
+interrupt void
+USER5_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER6_ISR - User Defined trap 6
+//
+interrupt void
+USER6_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER7_ISR - User Defined trap 7
+//
+interrupt void
+USER7_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER8_ISR - User Defined trap 8
+//
+interrupt void
+USER8_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER9_ISR - User Defined trap 9
+//
+interrupt void
+USER9_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER10_ISR - User Defined trap 10
+//
+interrupt void
+USER10_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER11_ISR - User Defined trap 11
+//
+interrupt void
+USER11_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// USER12_ISR - User Defined trap 12
+//
+interrupt void
+USER12_ISR(void)
+{
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// PIE Group 1 - MUXed into CPU INT1
+//
+
+//
+// EQ1INT_ISR - Connected to PIEIER1_1 (use MINT1 and MG11 masks):
+//
+#if (G11PL != 0)
+interrupt void
+SEQ1INT_ISR( void ) // ADC
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SEQ2INT_ISR - Connected to PIEIER1_2 (use MINT1 and MG12 masks):
+//
+#if (G12PL != 0)
+interrupt void
+SEQ2INT_ISR( void ) // ADC
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// XINT1_ISR - Connected to PIEIER1_4 (use MINT1 and MG14 masks):
+//
+#if (G14PL != 0)
+interrupt void
+XINT1_ISR(void)
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// XINT2_ISR - Connected to PIEIER1_5 (use MINT1 and MG15 masks):
+//
+#if (G15PL != 0)
+interrupt void
+XINT2_ISR(void)
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ADCINT_ISR - Connected to PIEIER1_6 (use MINT1 and MG16 masks):
+//
+#if (G16PL != 0)
+interrupt void
+ADCINT_ISR(void) // ADC
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// TINT0_ISR - Connected to PIEIER1_7 (use MINT1 and MG17 masks):
+//
+#if (G17PL != 0)
+interrupt void
+TINT0_ISR(void) // CPU-Timer 0
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// WAKEINT_ISR - Connected to PIEIER1_8 (use MINT1 and MG18 masks):
+//
+#if (G18PL != 0)
+interrupt void
+WAKEINT_ISR(void) // WD/LPM
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
+ IER |= M_INT1;
+ IER &= MINT1; // Set "global" priority
+ PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER1.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 2 - MUXed into CPU INT2
+//
+
+//
+// EPWM1_TZINT_ISR - Connected to PIEIER2_1 (use MINT2 and MG21 masks):
+//
+#if (G21PL != 0)
+interrupt void
+EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM2_TZINT_ISR - Connected to PIEIER2_2 (use MINT2 and MG22 masks):
+//
+#if (G22PL != 0)
+interrupt void
+EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM3_TZINT_ISR - Connected to PIEIER2_3 (use MINT2 and MG23 masks):
+//
+#if (G23PL != 0)
+interrupt void
+EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM4_TZINT_ISR - Connected to PIEIER2_4 (use MINT2 and MG24 masks):
+//
+#if (G24PL != 0)
+interrupt void
+EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM5_TZINT_ISR - Connected to PIEIER2_5 (use MINT2 and MG25 masks)
+//
+#if (G25PL != 0)
+interrupt void
+EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM6_TZINT_ISR - Connected to PIEIER2_6 (use MINT2 and MG26 masks)
+//
+#if (G26PL != 0)
+interrupt void
+EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
+ IER |= M_INT2;
+ IER &= MINT2; // Set "global" priority
+ PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER2.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 3 - MUXed into CPU INT3
+//
+
+//
+// EPWM1_INT_ISR - Connected to PIEIER3_1 (use MINT3 and MG31 masks)
+//
+#if (G31PL != 0)
+interrupt void
+EPWM1_INT_ISR(void) // ePWM1 Interrupt
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM2_INT_ISR - Connected to PIEIER3_2 (use MINT3 and MG32 masks)
+//
+#if (G32PL != 0)
+interrupt void
+EPWM2_INT_ISR(void) // ePWM2 Interrupt
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM3_INT_ISR - Connected to PIEIER3_3 (use MINT3 and MG33 masks)
+//
+#if (G33PL != 0)
+interrupt void
+EPWM3_INT_ISR(void) // ePWM3 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// Connected to PIEIER3_4 (use MINT3 and MG34 masks)
+//
+#if (G34PL != 0)
+interrupt void
+EPWM4_INT_ISR(void) // ePWM4 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM5_INT_ISR - Connected to PIEIER3_5 (use MINT3 and MG35 masks)
+//
+#if (G35PL != 0)
+interrupt void
+EPWM5_INT_ISR(void) // ePWM5 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EPWM6_INT_ISR - Connected to PIEIER3_6 (use MINT3 and MG36 masks)
+//
+#if (G36PL != 0)
+interrupt void
+EPWM6_INT_ISR(void) // ePWM6 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
+ IER |= M_INT3;
+ IER &= MINT3; // Set "global" priority
+ PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER3.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 4 - MUXed into CPU INT4
+//
+
+//
+// ECAP1_INT_ISR - Connected to PIEIER4_1 (use MINT4 and MG41 masks)
+//
+#if (G41PL != 0)
+interrupt void
+ECAP1_INT_ISR(void) // eCAP1 Interrupt
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
+//
+#if (G42PL != 0)
+interrupt void
+ECAP2_INT_ISR(void) // eCAP2 Interrupt
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAP3_INT_ISR - Connected to PIEIER4_3 (use MINT4 and MG43 masks)
+//
+#if (G43PL != 0)
+interrupt void
+ECAP3_INT_ISR(void) // eCAP3 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAP4_INT_ISR - Connected to PIEIER4_4 (use MINT4 and MG44 masks)
+//
+#if (G44PL != 0)
+interrupt void
+ECAP4_INT_ISR(void) // eCAP4 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here.
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAP5_INT_ISR - Connected to PIEIER4_5 (use MINT4 and MG45 masks):
+//
+#if (G45PL != 0)
+interrupt void
+ECAP5_INT_ISR(void) // eCAP5 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAP6_INT_ISR - Connected to PIEIER4_6 (use MINT4 and MG46 masks):
+//
+#if (G46PL != 0)
+interrupt void
+ECAP6_INT_ISR(void) // eCAP6 Interrupt
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
+ IER |= M_INT4;
+ IER &= MINT4; // Set "global" priority
+ PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER4.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 5 - MUXed into CPU INT5
+//
+
+//
+// Connected to PIEIER5_1 (use MINT5 and MG51 masks)
+//
+#if (G51PL != 0)
+interrupt void
+EQEP1_INT_ISR(void) // eQEP1 Interrupt
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
+ IER |= M_INT5;
+ IER &= MINT5; // Set "global" priority
+ PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ // Insert ISR Code here.......
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER5.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// EQEP2_INT_ISR - Connected to PIEIER5_2 (use MINT5 and MG52 masks)
+//
+#if (G52PL != 0)
+interrupt void
+EQEP2_INT_ISR(void) // eQEP2 Interrupt
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
+ IER |= M_INT5;
+ IER &= MINT5; // Set "global" priority
+ PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER5.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 6 - MUXed into CPU INT6
+//
+
+//
+// SPIRXINTA_ISR - Connected to PIEIER6_1 (use MINT6 and MG61 masks)
+//
+#if (G61PL != 0)
+interrupt void
+SPIRXINTA_ISR(void) // SPI-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SPITXINTA_ISR - Connected to PIEIER6_2 (use MINT6 and MG62 masks)
+//
+#if (G62PL != 0)
+interrupt void
+SPITXINTA_ISR(void) // SPI-A
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// MRINTB_ISR - Connected to PIEIER6_3 (use MINT6 and MG63 masks)
+//
+#if (G63PL != 0)
+interrupt void
+MRINTB_ISR(void) // McBSP-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// MXINTB_ISR - Connected to PIEIER6_4 (use MINT6 and MG64 masks)
+//
+#if (G64PL != 0)
+interrupt void
+MXINTB_ISR(void) // McBSP-B
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// MRINTA_ISR - Connected to PIEIER6_5 (use MINT6 and MG65 masks)
+//
+#if (G65PL != 0)
+interrupt void
+MRINTA_ISR(void) // McBSP-A
+{
+ //
+ // Set interrupt priority:
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// MXINTA_ISR - Connected to PIEIER6_6 (use MINT6 and MG66 masks)
+//
+#if (G66PL != 0)
+interrupt void
+MXINTA_ISR(void) // McBSP-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
+ IER |= M_INT6;
+ IER &= MINT6; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER6.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 7 - MUXed into CPU INT7
+//
+
+//
+// DINTCH1_ISR - Connected to PIEIER7_1 (use MINT7 and MG71 masks)
+//
+#if (G71PL != 0)
+interrupt void
+DINTCH1_ISR(void) // DMA
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// DINTCH2_ISR - Connected to PIEIER7_2 (use MINT7 and MG72 masks)
+//
+#if (G72PL != 0)
+interrupt void
+DINTCH2_ISR(void) // DMA
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// DINTCH3_ISR - Connected to PIEIER7_3 (use MINT7 and MG73 masks)
+//
+#if (G73PL != 0)
+interrupt void
+DINTCH3_ISR(void) // DMA
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// DINTCH4_ISR - Connected to PIEIER7_4 (use MINT7 and MG74 masks)
+//
+#if (G74PL != 0)
+interrupt void
+DINTCH4_ISR(void) // DMA
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved:
+ //
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// DINTCH5_ISR - Connected to PIEIER7_5 (use MINT7 and MG75 masks):
+//
+#if (G75PL != 0)
+interrupt void
+DINTCH5_ISR(void) // DMA
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// DINTCH6_ISR - Connected to PIEIER7_6 (use MINT7 and MG76 masks)
+//
+#if (G76PL != 0)
+interrupt void
+DINTCH6_ISR(void) // DMA
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
+ IER |= M_INT7;
+ IER &= MINT7; // Set "global" priority
+ PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER7.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 8 - MUXed into CPU INT8
+//
+
+//
+// I2CINT1A_ISR - Connected to PIEIER8_1 (use MINT8 and MG81 masks)
+//
+#if (G81PL != 0)
+interrupt void
+I2CINT1A_ISR(void) // I2C-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// I2CINT2A_ISR - Connected to PIEIER8_2 (use MINT8 and MG82 masks)
+//
+#if (G82PL != 0)
+interrupt void
+I2CINT2A_ISR(void) // I2C-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SCIRXINTC_ISR - Connected to PIEIER8_5 (use MINT8 and MG85 masks)
+//
+#if (G85PL != 0)
+interrupt void
+SCIRXINTC_ISR(void) // SCI-C
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SCITXINTC_ISR - Connected to PIEIER8_6 (use MINT8 and MG86 masks)
+//
+#if (G82PL != 0)
+interrupt void
+SCITXINTC_ISR(void) // SCI-C
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
+ IER |= M_INT8;
+ IER &= MINT8; // Set "global" priority
+ PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER8.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 9 - MUXed into CPU INT9
+//
+
+//
+// SCIRXINTA_ISR - Connected to PIEIER9_1 (use MINT9 and MG91 masks)
+//
+#if (G91PL != 0)
+interrupt void
+SCIRXINTA_ISR(void) // SCI-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SCITXINTA_ISR - Connected to PIEIER9_2 (use MINT9 and MG92 masks)
+//
+#if (G92PL != 0)
+interrupt void
+SCITXINTA_ISR(void) // SCI-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SCIRXINTB_ISR - Connected to PIEIER9_3 (use MINT9 and MG93 masks)
+//
+#if (G93PL != 0)
+interrupt void
+SCIRXINTB_ISR(void) // SCI-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// SCITXINTB_ISR - Connected to PIEIER9_4 (use MINT9 and MG94 masks)
+//
+#if (G94PL != 0)
+interrupt void
+SCITXINTB_ISR(void) // SCI-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAN0INTA_ISR - Connected to PIEIER9_5 (use MINT9 and MG95 masks)
+//
+#if (G95PL != 0)
+interrupt void
+ECAN0INTA_ISR(void) // eCAN-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAN1INTA_ISR - Connected to PIEIER9_6 (use MINT9 and MG96 masks)
+//
+#if (G96PL != 0)
+interrupt void
+ECAN1INTA_ISR(void) // eCAN-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAN0INTB_ISR - Connected to PIEIER9_7 (use MINT9 and MG97 masks)
+//
+#if (G97PL != 0)
+interrupt void
+ECAN0INTB_ISR(void) // eCAN-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// ECAN1INTB_ISR - Connected to PIEIER9_8 (use MINT9 and MG98 masks)
+//
+#if (G98PL != 0)
+interrupt void
+ECAN1INTB_ISR(void) // eCAN-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
+ IER |= M_INT9;
+ IER &= MINT9; // Set "global" priority
+ PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER9.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// PIE Group 10 - MUXed into CPU INT10
+//
+
+//
+// PIE Group 11 - MUXed into CPU INT11
+//
+
+//
+// PIE Group 12 - MUXed into CPU INT12
+//
+
+//
+// XINT3_ISR - Connected to PIEIER9_1 (use MINT12 and MG121 masks)
+//
+#if (G121PL != 0)
+interrupt void
+XINT3_ISR(void)
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// XINT4_ISR - Connected to PIEIER12_2 (use MINT12 and MG122 masks)
+//
+#if (G122PL != 0)
+interrupt void
+XINT4_ISR(void)
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// XINT5_ISR - Connected to PIEIER12_3 (use MINT12 and MG123 masks)
+//
+#if (G123PL != 0)
+interrupt void
+XINT5_ISR(void) // SCI-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// XINT6_ISR - Connected to PIEIER12_4 (use MINT12 and MG124 masks)
+//
+#if (G124PL != 0)
+interrupt void
+XINT6_ISR(void) // SCI-B
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// XINT7_ISR - Connected to PIEIER12_5 (use MINT12 and MG125 masks)
+//
+#if (G125PL != 0)
+interrupt void
+XINT7_ISR(void) // eCAN-A
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// LVF_ISR - Connected to PIEIER12_7 (use MINT12 and MG127 masks)
+//
+#if (G127PL != 0)
+interrupt void
+LVF_ISR(void) // FPU
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// LUF_ISR - Connected to PIEIER12_8 (use MINT12 and MG128 masks)
+//
+#if (G128PL != 0)
+interrupt void
+LUF_ISR(void) // FPU
+{
+ //
+ // Set interrupt priority
+ //
+ volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
+ IER |= M_INT12;
+ IER &= MINT12; // Set "global" priority
+ PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
+ PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
+ __asm(" NOP");
+ EINT;
+
+ //
+ // Insert ISR Code here
+ //
+
+ //
+ // Restore registers saved
+ //
+ DINT;
+ PieCtrlRegs.PIEIER12.all = TempPIEIER;
+
+ //
+ // Next two lines for debug only to halt the processor here
+ // Remove after inserting ISR Code
+ //
+ asm (" ESTOP0");
+ for(;;);
+}
+#endif
+
+//
+// Catch All Default ISRs
+//
+
+//
+// PIE_RESERVED - Reserved space. For test.
+//
+interrupt void
+PIE_RESERVED(void)
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// INT_NOTUSED_ISR - Reserved space. For test.
+//
+interrupt void
+INT_NOTUSED_ISR(void)
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// rsvd_ISR - For test
+//
+interrupt void
+rsvd_ISR(void)
+{
+ asm (" ESTOP0");
+ for(;;);
+}
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_SWPrioritizedPieVect.c b/bsp/source/DSP2833x_SWPrioritizedPieVect.c
new file mode 100644
index 0000000..a746e5e
--- /dev/null
+++ b/bsp/source/DSP2833x_SWPrioritizedPieVect.c
@@ -0,0 +1,573 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 4, 2007 14:25:31 $
+//###########################################################################
+//
+// FILE: DSP2833x_SWPiroritizedPieVect.c
+//
+// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h"
+
+const struct PIE_VECT_TABLE PieVectTableInit =
+{
+ PIE_RESERVED, // Reserved space
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+ PIE_RESERVED, // reserved
+
+ //
+ // Non-Peripheral Interrupts:
+ //
+ #if (INT13PL != 0)
+ INT13_ISR, // XINT13
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (INT14PL != 0)
+ INT14_ISR, // CPU-Timer2
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (INT15PL != 0)
+ DATALOG_ISR, // Datalogging interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (INT16PL != 0)
+ RTOSINT_ISR, // RTOS interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR, // reserved interrupt
+ NMI_ISR, // Non-maskable interrupt
+ ILLEGAL_ISR, // Illegal operation TRAP
+ USER1_ISR, // User Defined trap 1
+ USER2_ISR, // User Defined trap 2
+ USER3_ISR, // User Defined trap 3
+ USER4_ISR, // User Defined trap 4
+ USER5_ISR, // User Defined trap 5
+ USER6_ISR, // User Defined trap 6
+ USER7_ISR, // User Defined trap 7
+ USER8_ISR, // User Defined trap 8
+ USER9_ISR, // User Defined trap 9
+ USER10_ISR, // User Defined trap 10
+ USER11_ISR, // User Defined trap 11
+ USER12_ISR, // User Defined trap 12
+
+ //
+ // Group 1 PIE Vectors:
+ //
+ #if (G11PL != 0)
+ SEQ1INT_ISR, // ADC
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G12PL != 0)
+ SEQ2INT_ISR, // ADC
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+
+ #if (G14PL != 0)
+ XINT1_ISR, // External
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G15PL != 0)
+ XINT2_ISR, // External
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G16PL != 0)
+ ADCINT_ISR, // ADC
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G17PL != 0)
+ TINT0_ISR, // Timer 0
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G18PL != 0)
+ WAKEINT_ISR, // WD & Low Power
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ //
+ // Group 2 PIE Vectors:
+ //
+ #if (G21PL != 0)
+ EPWM1_TZINT_ISR, // ePWM1 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G22PL != 0)
+ EPWM2_TZINT_ISR, // ePWM2 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G23PL != 0)
+ EPWM3_TZINT_ISR, // ePWM3 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G24PL != 0)
+ EPWM4_TZINT_ISR, // ePWM4 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G25PL != 0)
+ EPWM5_TZINT_ISR, // ePWM5 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G26PL != 0)
+ EPWM6_TZINT_ISR, // ePWM6 Trip Zone
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 3 PIE Vectors:
+ //
+ #if (G31PL != 0)
+ EPWM1_INT_ISR, // ePWM1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G32PL != 0)
+ EPWM2_INT_ISR, // ePWM2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G33PL != 0)
+ EPWM3_INT_ISR, // ePWM3 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G34PL != 0)
+ EPWM4_INT_ISR, // ePWM4 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G35PL != 0)
+ EPWM5_INT_ISR, // ePWM5 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G36PL != 0)
+ EPWM6_INT_ISR, // ePWM6 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 4 PIE Vectors:
+ //
+ #if (G41PL != 0)
+ ECAP1_INT_ISR, // eCAP1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G42PL != 0)
+ ECAP2_INT_ISR, // eCAP2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G43PL != 0)
+ ECAP3_INT_ISR, // eCAP3 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G44PL != 0)
+ ECAP4_INT_ISR, // eCAP4 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G45PL != 0)
+ ECAP5_INT_ISR, // eCAP5 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G46PL != 0)
+ ECAP6_INT_ISR, // eCAP6 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 5 PIE Vectors:
+ //
+ #if (G51PL != 0)
+ EQEP1_INT_ISR, // eQEP1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G52PL != 0)
+ EQEP2_INT_ISR, // eQEP2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 6 PIE Vectors:
+ //
+ #if (G61PL != 0)
+ SPIRXINTA_ISR, // SPI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G62PL != 0)
+ SPITXINTA_ISR, // SPI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G63PL != 0)
+ MRINTB_ISR, // McBSP-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G64PL != 0)
+ MXINTB_ISR, // McBSP-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G65PL != 0)
+ MRINTA_ISR, // McBSP-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G66PL != 0)
+ MXINTA_ISR, // McBSP-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 7 PIE Vectors:
+ //
+ #if (G71PL != 0)
+ DINTCH1_ISR, // DMA-Channel 1 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G72PL != 0)
+ DINTCH2_ISR, // DMA-Channel 2 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G73PL != 0)
+ DINTCH3_ISR, // DMA-Channel 3 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G74PL != 0)
+ DINTCH4_ISR, // DMA-Channel 4 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G75PL != 0)
+ DINTCH5_ISR, // DMA-Channel 5 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G76PL != 0)
+ DINTCH6_ISR, // DMA-Channel 6 Interrupt
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 8 PIE Vectors:
+ //
+ #if (G81PL != 0)
+ I2CINT1A_ISR, // I2C-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G82PL != 0)
+ I2CINT2A_ISR, // I2C-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ #if (G85PL != 0)
+ SCIRXINTC_ISR, // SCI-C
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G86PL != 0)
+ SCITXINTC_ISR, // SCI-C
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 9 PIE Vectors:
+ //
+ #if (G91PL != 0)
+ SCIRXINTA_ISR, // SCI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G92PL != 0)
+ SCITXINTA_ISR, // SCI-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G93PL != 0)
+ SCIRXINTB_ISR, // SCI-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G94PL != 0)
+ SCITXINTB_ISR, // SCI-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G95PL != 0)
+ ECAN0INTA_ISR, // eCAN-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G96PL != 0)
+ ECAN1INTA_ISR, // eCAN-A
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G97PL != 0)
+ ECAN0INTB_ISR, // eCAN-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G98PL != 0)
+ ECAN1INTB_ISR, // eCAN-B
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ //
+ // Group 10 PIE Vectors
+ //
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 11 PIE Vectors
+ //
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+ rsvd_ISR,
+
+ //
+ // Group 12 PIE Vectors
+ //
+ #if (G121PL != 0)
+ XINT3_ISR, // External interrupt 3
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G122PL != 0)
+ XINT4_ISR, // External interrupt 4
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G123PL != 0)
+ XINT5_ISR, // External interrupt 5
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G124PL != 0)
+ XINT6_ISR, // External interrupt 6
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G125PL != 0)
+ XINT7_ISR, // External interrupt 7
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ rsvd_ISR,
+
+ #if (G127PL != 0)
+ LVF_ISR, // Latched overflow flag
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+
+ #if (G128PL != 0)
+ LUF_ISR, // Latched underflow flag
+ #else
+ INT_NOTUSED_ISR,
+ #endif
+};
+
+//
+// InitPieVectTable - This function initializes the PIE vector table to a known
+// state. This function must be executed after boot time.
+//
+void
+InitPieVectTable(void)
+{
+ int16 i;
+ Uint32 *Source = (void *) &PieVectTableInit;
+ Uint32 *Dest = (void *) &PieVectTable;
+
+ EALLOW;
+ for(i=0; i < 128; i++)
+ {
+ *Dest++ = *Source++;
+ }
+ EDIS;
+
+ //
+ // Enable the PIE Vector Table
+ //
+ PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+}
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_Sci.c b/bsp/source/DSP2833x_Sci.c
new file mode 100644
index 0000000..1c13ea2
--- /dev/null
+++ b/bsp/source/DSP2833x_Sci.c
@@ -0,0 +1,224 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 1, 2007 16:06:07 $
+//###########################################################################
+//
+// FILE: DSP2833x_Sci.c
+//
+// TITLE: DSP2833x SCI Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitSci - This function initializes the SCI(s) to a known state.
+//
+void
+InitSci(void)
+{
+ //
+ // Initialize SCI-A
+ //
+
+ //
+ // Initialize SCI-B
+ //
+
+ //
+ // Initialize SCI-C
+ //
+}
+
+//
+// InitSciGpio - This function initializes GPIO to function as SCI-A, SCI-B, or
+// SCI-C
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// Only one GPIO pin should be enabled for SCITXDA/B operation.
+// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation.
+// Comment out other unwanted lines.
+//
+void
+InitSciGpio()
+{
+ InitSciaGpio();
+#if DSP28_SCIB
+ InitScibGpio();
+#endif // if DSP28_SCIB
+
+#if DSP28_SCIC
+ InitScicGpio();
+#endif // if DSP28_SCIC
+}
+
+//
+// InitSciaGpio - This function initializes GPIO pins to function as SCI-A pins
+//
+void
+InitSciaGpio()
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled disabled by the user.
+ // This will enable the pullups for the specified pins.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // This will select asynch (no qualification) for the selected pins.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA)
+
+ //
+ // Configure SCI-A pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be SCI functional
+ // pins.
+ //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 to SCIRXDA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 to SCITXDA
+
+ EDIS;
+}
+
+#if DSP28_SCIB
+//
+// InitScibGpio - This function initializes GPIO pins to function as SCI-B pins
+//
+void
+InitScibGpio()
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ //GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; //Enable pull-up for GPIO9 (SCITXDB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; //Enable pull-up for GPIO14 (SCITXDB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up for GPIO18 (SCITXDB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; //Enable pull-up for GPIO22 (SCITXDB)
+
+ //GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; //Enable pull-up for GPIO11 (SCIRXDB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; //Enable pull-up for GPIO15 (SCIRXDB)
+ GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (SCIRXDB)
+ //GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; //Enable pull-up for GPIO23 (SCIRXDB)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB)
+ //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB)
+ //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB)
+
+ //
+ // Configure SCI-B pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be SCI functional
+ // pins.
+ // Comment out other unwanted lines.
+ //
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; //Configure GPIO9 to SCITXDB
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; //Configure GPIO14 to SCITXDB
+ GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; //Configure GPIO18 to SCITXDB
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; //Configure GPIO22 to SCITXDB
+
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; //Configure GPIO11 for SCIRXDB
+ //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; //Configure GPIO15 for SCIRXDB
+ GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; //Configure GPIO19 for SCIRXDB
+ //GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; //Configure GPIO23 for SCIRXDB
+
+ EDIS;
+}
+#endif // if DSP28_SCIB
+
+#if DSP28_SCIC
+//
+// InitScicGpio - This function initializes GPIO pins to function as SCI-C pins
+//
+void
+InitScicGpio()
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled disabled by the user.
+ // This will enable the pullups for the specified pins.
+ //
+ GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC)
+ GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // Inputs are synchronized to SYSCLKOUT by default.
+ // This will select asynch (no qualification) for the selected pins.
+ //
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC)
+
+ //
+ // Configure SCI-C pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be SCI functional
+ // pins.
+ //
+ GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 to SCIRXDC
+ GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 to SCITXDC
+
+ EDIS;
+}
+#endif // if DSP28_SCIC
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_Spi.c b/bsp/source/DSP2833x_Spi.c
new file mode 100644
index 0000000..aa6b259
--- /dev/null
+++ b/bsp/source/DSP2833x_Spi.c
@@ -0,0 +1,144 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006 13:46:44 $
+//###########################################################################
+//
+// FILE: DSP2833x_Spi.c
+//
+// TITLE: DSP2833x SPI Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitSPI - This function initializes the SPI(s) to a known state.
+//
+void
+InitSpi(void)
+{
+ //
+ // Initialize SPI-A/B/C/D
+ //
+}
+
+//
+// InitSpiGpio - This function initializes GPIO pins to function as SPI pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// For each SPI peripheral
+// Only one GPIO pin should be enabled for SPISOMO operation.
+// Only one GPIO pin should be enabled for SPISOMI operation.
+// Only one GPIO pin should be enabled for SPICLKA operation.
+// Only one GPIO pin should be enabled for SPISTEA operation.
+// Comment out other unwanted lines.
+//
+void
+InitSpiGpio()
+{
+ InitSpiaGpio();
+}
+
+//
+// InitSpiaGpio - This function initializes GPIO poins to function as SPI pins
+//
+void
+InitSpiaGpio()
+{
+ EALLOW;
+
+ //
+ // Enable internal pull-up for the selected pins
+ // Pull-ups can be enabled or disabled by the user.
+ // This will enable the pullups for the specified pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up on GPIO16 (SPISIMOA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; //Enable pull-up on GPIO17 (SPISOMIA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up on GPIO18 (SPICLKA)
+ GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up on GPIO19 (SPISTEA)
+
+ //GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; //Enable pull-up on GPIO54 (SPISIMOA)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; //Enable pull-up on GPIO55 (SPISOMIA)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; //Enable pull-up on GPIO56 (SPICLKA)
+ //GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; //Enable pull-up on GPIO57 (SPISTEA)
+
+ //
+ // Set qualification for selected pins to asynch only
+ // This will select asynch (no qualification) for the selected pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
+ GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
+
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA)
+ //GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)
+
+ //
+ // Configure SPI-A pins using GPIO regs
+ // This specifies which of the possible GPIO pins will be SPI
+ // functional pins.
+ // Comment out other unwanted lines.
+ //
+ GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
+ GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
+
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA
+ //GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
+
+ EDIS;
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_SysCtrl.c b/bsp/source/DSP2833x_SysCtrl.c
new file mode 100644
index 0000000..2e39878
--- /dev/null
+++ b/bsp/source/DSP2833x_SysCtrl.c
@@ -0,0 +1,453 @@
+// TI File $Revision: /main/8 $
+// Checkin $Date: April 15, 2009 09:54:05 $
+//###########################################################################
+//
+// FILE: DSP2833x_SysCtrl.c
+//
+// TITLE: DSP2833x Device System Control Initialization & Support Functions.
+//
+// DESCRIPTION: Example initialization of system resources.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // Headerfile Include File
+#include "DSP2833x_Examples.h" // Examples Include File
+
+//
+// Functions that will be run from RAM need to be assigned to
+// a different section. This section will then be mapped to a load and
+// run address using the linker cmd file.
+//
+#pragma CODE_SECTION(InitFlash, "ramfuncs");
+
+//
+// InitSysCtrl - This function initializes the System Control registers to a
+// known state.
+// - Disables the watchdog
+// - Set the PLLCR for proper SYSCLKOUT frequency
+// - Set the pre-scaler for the high and low frequency peripheral clocks
+// - Enable the clocks to the peripherals
+//
+void
+InitSysCtrl(void)
+{
+ //
+ // Disable the watchdog
+ //
+ DisableDog();
+
+ //
+ // Initialize the PLL control: PLLCR and DIVSEL
+ // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
+ //
+ InitPll(DSP28_PLLCR,DSP28_DIVSEL);
+
+ //
+ // Initialize the peripheral clocks
+ //
+ InitPeripheralClocks();
+}
+
+//
+// InitFlash - This function initializes the Flash Control registers
+// CAUTION
+// This function MUST be executed out of RAM. Executing it
+// out of OTP/Flash will yield unpredictable results
+//
+void
+InitFlash(void)
+{
+ EALLOW;
+
+ //
+ // Enable Flash Pipeline mode to improve performance
+ // of code executed from Flash.
+ //
+ FlashRegs.FOPT.bit.ENPIPE = 1;
+
+ //
+ // CAUTION
+ // Minimum waitstates required for the flash operating
+ // at a given CPU rate must be characterized by TI.
+ // Refer to the datasheet for the latest information.
+ //
+#if CPU_FRQ_150MHZ
+ //
+ // Set the Paged Waitstate for the Flash
+ //
+ FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
+
+ //
+ // Set the Random Waitstate for the Flash
+ //
+ FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
+
+ //
+ // Set the Waitstate for the OTP
+ //
+ FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
+#endif
+
+#if CPU_FRQ_100MHZ
+ //
+ // Set the Paged Waitstate for the Flash
+ //
+ FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
+
+ //
+ // Set the Random Waitstate for the Flash
+ //
+ FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
+
+ //
+ // Set the Waitstate for the OTP
+ //
+ FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
+#endif
+ //
+ // CAUTION
+ // ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
+ //
+ FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
+ FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
+ EDIS;
+
+ //
+ // Force a pipeline flush to ensure that the write to
+ // the last register configured occurs before returning.
+ //
+ asm(" RPT #7 || NOP");
+}
+
+//
+// ServiceDog - This function resets the watchdog timer.
+// Enable this function for using ServiceDog in the application
+//
+void
+ServiceDog(void)
+{
+ EALLOW;
+ SysCtrlRegs.WDKEY = 0x0055;
+ SysCtrlRegs.WDKEY = 0x00AA;
+ EDIS;
+}
+
+//
+// DisableDog - This function disables the watchdog timer.
+//
+void
+DisableDog(void)
+{
+ EALLOW;
+ SysCtrlRegs.WDCR= 0x0068;
+ EDIS;
+}
+
+//
+// InitPll - This function initializes the PLLCR register.
+//
+void
+InitPll(Uint16 val, Uint16 divsel)
+{
+ //
+ // Make sure the PLL is not running in limp mode
+ //
+ if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
+ {
+ //
+ // Missing external clock has been detected
+ // Replace this line with a call to an appropriate
+ // SystemShutdown(); function.
+ //
+ asm(" ESTOP0");
+ }
+
+ //
+ // DIVSEL MUST be 0 before PLLCR can be changed from
+ // 0x0000. It is set to 0 by an external reset XRSn
+ // This puts us in 1/4
+ //
+ if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
+ {
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
+ EDIS;
+ }
+
+ //
+ // Change the PLLCR
+ //
+ if (SysCtrlRegs.PLLCR.bit.DIV != val)
+ {
+ EALLOW;
+
+ //
+ // Before setting PLLCR turn off missing clock detect logic
+ //
+ SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
+ SysCtrlRegs.PLLCR.bit.DIV = val;
+ EDIS;
+
+ //
+ // Optional: Wait for PLL to lock.
+ // During this time the CPU will switch to OSCCLK/2 until
+ // the PLL is stable. Once the PLL is stable the CPU will
+ // switch to the new PLL value.
+ //
+ // This time-to-lock is monitored by a PLL lock counter.
+ //
+ // Code is not required to sit and wait for the PLL to lock.
+ // However, if the code does anything that is timing critical,
+ // and requires the correct clock be locked, then it is best to
+ // wait until this switching has completed.
+ //
+
+ //
+ // Wait for the PLL lock bit to be set.
+ //
+
+ //
+ // The watchdog should be disabled before this loop, or fed within
+ // the loop via ServiceDog().
+ //
+
+ //
+ // Uncomment to disable the watchdog
+ //
+ DisableDog();
+
+ while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
+ {
+ //
+ // Uncomment to service the watchdog
+ //
+ //ServiceDog();
+ }
+
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
+ EDIS;
+ }
+
+ //
+ // If switching to 1/2
+ //
+ if((divsel == 1)||(divsel == 2))
+ {
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
+ EDIS;
+ }
+
+ //
+ // NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF
+ // If switching to 1/1
+ // * First go to 1/2 and let the power settle
+ // The time required will depend on the system, this is only an example
+ // * Then switch to 1/1
+ //
+ if(divsel == 3)
+ {
+ EALLOW;
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
+ DELAY_US(50L);
+ SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
+ EDIS;
+ }
+}
+
+//
+// InitPeripheralClocks - This function initializes the clocks to the
+// peripheral modules. First the high and low clock prescalers are set
+// Second the clocks are enabled to each peripheral. To reduce power, leave
+// clocks to unused peripherals disabled
+//
+// Note: If a peripherals clock is not enabled then you cannot
+// read or write to the registers for that peripheral
+//
+void
+InitPeripheralClocks(void)
+{
+ EALLOW;
+
+ //
+ // HISPCP/LOSPCP prescale register settings, normally it will be set to
+ // default values
+ //
+ SysCtrlRegs.HISPCP.all = 0x0001;
+ SysCtrlRegs.LOSPCP.all = 0x0002;
+
+ //
+ // XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
+ // XTIMCLK = SYSCLKOUT/2
+ //
+ XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
+
+ //
+ // XCLKOUT = XTIMCLK/2
+ //
+ XintfRegs.XINTCNF2.bit.CLKMODE = 1;
+
+ //
+ // Enable XCLKOUT
+ //
+ XintfRegs.XINTCNF2.bit.CLKOFF = 0;
+
+ //
+ // Peripheral clock enables set for the selected peripherals.
+ // If you are not using a peripheral leave the clock off
+ // to save on power.
+ //
+ // Note: not all peripherals are available on all 2833x derivates.
+ // Refer to the datasheet for your particular device.
+ //
+ // This function is not written to be an example of efficient code.
+ //
+ SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
+
+ //
+ // *IMPORTANT*
+ // The ADC_cal function, which copies the ADC calibration values from TI
+ // reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs
+ // automatically in the Boot ROM. If the boot ROM code is bypassed during
+ // the debug process, the following function MUST be called for the ADC to
+ // function according to specification. The clocks to the ADC MUST be
+ // enabled before calling this function.
+ // See the device data manual and/or the ADC Reference
+ // Manual for more information.
+ //
+ ADC_cal();
+
+ SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
+ SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
+ SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
+ SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
+ SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
+ SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
+ SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
+ SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
+ SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
+
+ SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
+ SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
+ SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
+ SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
+ SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
+ SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
+ SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
+ SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
+
+ SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
+ SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
+ SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
+ SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
+ SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
+ SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
+ SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
+ SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
+
+ SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
+ SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
+ SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
+
+ SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
+ SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
+ SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
+
+ EDIS;
+}
+
+//
+// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with
+// current password for the DSP. Returns 1 if unlock is successful.
+//
+#define STATUS_FAIL 0
+#define STATUS_SUCCESS 1
+Uint16
+CsmUnlock()
+{
+ volatile Uint16 temp;
+
+ //
+ // Load the key registers with the current password. The 0xFFFF's are dummy
+ // passwords. User should replace them with the correct password for the
+ // DSP.
+ //
+ EALLOW;
+ CsmRegs.KEY0 = 0xFFFF;
+ CsmRegs.KEY1 = 0xFFFF;
+ CsmRegs.KEY2 = 0xFFFF;
+ CsmRegs.KEY3 = 0xFFFF;
+ CsmRegs.KEY4 = 0xFFFF;
+ CsmRegs.KEY5 = 0xFFFF;
+ CsmRegs.KEY6 = 0xFFFF;
+ CsmRegs.KEY7 = 0xFFFF;
+ EDIS;
+
+ //
+ // Perform a dummy read of the password locations if they match the key
+ // values, the CSM will unlock
+ //
+ temp = CsmPwl.PSWD0;
+ temp = CsmPwl.PSWD1;
+ temp = CsmPwl.PSWD2;
+ temp = CsmPwl.PSWD3;
+ temp = CsmPwl.PSWD4;
+ temp = CsmPwl.PSWD5;
+ temp = CsmPwl.PSWD6;
+ temp = CsmPwl.PSWD7;
+
+ //
+ // If the CSM unlocked, return succes, otherwise return failure.
+ //
+ if (CsmRegs.CSMSCR.bit.SECURE == 0)
+ {
+ return STATUS_SUCCESS;
+ }
+ else
+ {
+ return STATUS_FAIL;
+ }
+}
+
+//
+// End of file
+//
+
diff --git a/bsp/source/DSP2833x_Xintf.c b/bsp/source/DSP2833x_Xintf.c
new file mode 100644
index 0000000..2eebc8d
--- /dev/null
+++ b/bsp/source/DSP2833x_Xintf.c
@@ -0,0 +1,334 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: August 16, 2007 11:06:26 $
+//###########################################################################
+//
+// FILE: DSP2833x_Xintf.c
+//
+// TITLE: DSP2833x Device External Interface Init & Support Functions.
+//
+// DESCRIPTION:
+//
+// Example initialization function for the external interface (XINTF).
+// This example configures the XINTF to its default state. For an
+// example of how this function being used refer to the
+// examples/run_from_xintf project.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//
+// Included Files
+//
+#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
+
+//
+// InitXINTF - This function initializes the External Interface the default
+// reset state.
+//
+// Do not modify the timings of the XINTF while running from the XINTF. Doing
+// so can yield unpredictable results
+//
+void
+InitXintf(void)
+{
+ //
+ // This shows how to write to the XINTF registers. The
+ // values used here are the default state after reset.
+ // Different hardware will require a different configuration.
+ //
+
+ //
+ // For an example of an XINTF configuration used with the
+ // F28335 eZdsp, refer to the examples/run_from_xintf project.
+ //
+
+ //
+ // Any changes to XINTF timing should only be made by code
+ // running outside of the XINTF.
+ //
+
+ //
+ // All Zones
+ // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
+ //
+ EALLOW;
+ XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
+
+ //
+ // No write buffering
+ //
+ XintfRegs.XINTCNF2.bit.WRBUFF = 0;
+
+ //
+ // XCLKOUT is enabled
+ //
+ XintfRegs.XINTCNF2.bit.CLKOFF = 0;
+
+ //
+ // XCLKOUT = XTIMCLK/2
+ //
+ XintfRegs.XINTCNF2.bit.CLKMODE = 1;
+
+ //
+ // Zone 0
+ // When using ready, ACTIVE must be 1 or greater
+ // Lead must always be 1 or greater
+ // Zone write timing
+ //
+ XintfRegs.XTIMING0.bit.XWRLEAD = 3;
+ XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
+ XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
+
+ //
+ // Zone read timing
+ //
+ XintfRegs.XTIMING0.bit.XRDLEAD = 3;
+ XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
+ XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
+
+ //
+ // double all Zone read/write lead/active/trail timing
+ //
+ XintfRegs.XTIMING0.bit.X2TIMING = 1;
+
+ //
+ // Zone will sample XREADY signal
+ //
+ XintfRegs.XTIMING0.bit.USEREADY = 1;
+ XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
+
+ //
+ // Size must be either:
+ // 0,1 = x32 or
+ // 1,1 = x16 other values are reserved
+ //
+ XintfRegs.XTIMING0.bit.XSIZE = 3;
+
+ //
+ // Zone 6
+ // When using ready, ACTIVE must be 1 or greater
+ // Lead must always be 1 or greater
+ // Zone write timing
+ //
+ XintfRegs.XTIMING6.bit.XWRLEAD = 3;
+ XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
+ XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
+
+ //
+ // Zone read timing
+ //
+ XintfRegs.XTIMING6.bit.XRDLEAD = 3;
+ XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
+ XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
+
+ //
+ // double all Zone read/write lead/active/trail timing
+ //
+ XintfRegs.XTIMING6.bit.X2TIMING = 1;
+
+ //
+ // Zone will sample XREADY signal
+ //
+ XintfRegs.XTIMING6.bit.USEREADY = 1;
+ XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
+
+ //
+ // Size must be either:
+ // 0,1 = x32 or
+ // 1,1 = x16 other values are reserved
+ //
+ XintfRegs.XTIMING6.bit.XSIZE = 3;
+
+ //
+ // Zone 7
+ // When using ready, ACTIVE must be 1 or greater
+ // Lead must always be 1 or greater
+ // Zone write timing
+ //
+ XintfRegs.XTIMING7.bit.XWRLEAD = 3;
+ XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
+ XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
+
+ //
+ // Zone read timing
+ //
+ XintfRegs.XTIMING7.bit.XRDLEAD = 3;
+ XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
+ XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
+
+ //
+ // double all Zone read/write lead/active/trail timing
+ //
+ XintfRegs.XTIMING7.bit.X2TIMING = 1;
+
+ //
+ // Zone will sample XREADY signal
+ //
+ XintfRegs.XTIMING7.bit.USEREADY = 1;
+ XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
+
+ //
+ // Size must be either:
+ // 0,1 = x32 or
+ // 1,1 = x16 other values are reserved
+ //
+ XintfRegs.XTIMING7.bit.XSIZE = 3;
+
+ //
+ // Bank switching
+ // Assume Zone 7 is slow, so add additional BCYC cycles
+ // when ever switching from Zone 7 to another Zone.
+ // This will help avoid bus contention.
+ //
+ XintfRegs.XBANK.bit.BANK = 7;
+ XintfRegs.XBANK.bit.BCYC = 7;
+ EDIS;
+
+ //
+ // Force a pipeline flush to ensure that the write to the last register
+ // configured occurs before returning.
+ //
+ InitXintf16Gpio();
+ //InitXintf32Gpio();
+
+ asm(" RPT #7 || NOP");
+}
+
+//
+// InitXintf32Gpio -
+//
+void
+InitXintf32Gpio()
+{
+ EALLOW;
+ GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
+ GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
+ GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
+ GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
+ GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
+ GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
+ GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
+ GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
+ GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
+ GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
+ GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
+ GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
+ GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
+ GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
+ GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
+ GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
+
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
+ GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
+
+ InitXintf16Gpio();
+}
+
+//
+// InitXintf16Gpio -
+//
+void
+InitXintf16Gpio()
+{
+ EALLOW;
+ GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
+ GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
+ GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
+ GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
+ GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
+ GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
+ GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
+ GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
+ GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
+ GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
+ GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
+ GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
+ GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
+ GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
+ GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
+ GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
+ GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
+ GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
+ GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
+ GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
+ GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
+ GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
+ GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
+
+ GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
+ GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
+ GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
+ GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
+ GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
+ GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
+ GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
+ GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
+ GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
+ GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
+ GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
+ GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
+ GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
+ GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
+
+ GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
+ GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
+ GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
+ EDIS;
+}
+
+//
+// End of File
+//
+
diff --git a/bsp/source/DSP2833x_usDelay.asm b/bsp/source/DSP2833x_usDelay.asm
new file mode 100644
index 0000000..d09c7ed
--- /dev/null
+++ b/bsp/source/DSP2833x_usDelay.asm
@@ -0,0 +1,107 @@
+;// TI File $Revision: /main/4 $
+;// Checkin $Date: July 30, 2007 10:28:57 $
+;//###########################################################################
+;//
+;// FILE: DSP2833x_usDelay.asm
+;//
+;// TITLE: Simple delay function
+;//
+;// DESCRIPTION:
+;//
+;// This is a simple delay function that can be used to insert a specified
+;// delay into code.
+;//
+;// This function is only accurate if executed from internal zero-waitstate
+;// SARAM. If it is executed from waitstate memory then the delay will be
+;// longer then specified.
+;//
+;// To use this function:
+;//
+;// 1 - update the CPU clock speed in the DSP2833x_Examples.h
+;// file. For example:
+;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
+;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed
+;//
+;// 2 - Call this function by using the DELAY_US(A) macro
+;// that is defined in the DSP2833x_Examples.h file. This macro
+;// will convert the number of microseconds specified
+;// into a loop count for use with this function.
+;// This count will be based on the CPU frequency you specify.
+;//
+;// 3 - For the most accurate delay
+;// - Execute this function in 0 waitstate RAM.
+;// - Disable interrupts before calling the function
+;// If you do not disable interrupts, then think of
+;// this as an "at least" delay function as the actual
+;// delay may be longer.
+;//
+;// The C assembly call from the DELAY_US(time) macro will
+;// look as follows:
+;//
+;// extern void Delay(long LoopCount);
+;//
+;// MOV AL,#LowLoopCount
+;// MOV AH,#HighLoopCount
+;// LCR _Delay
+;//
+;// Or as follows (if count is less then 16-bits):
+;//
+;// MOV ACC,#LoopCount
+;// LCR _Delay
+;//
+;//
+;//###########################################################################
+;// $TI Release: F2833x Support Library v2.00.00.00 $
+;// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+;// $Copyright:
+;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+;//
+;// Redistribution and use in source and binary forms, with or without
+;// modification, are permitted provided that the following conditions
+;// are met:
+;//
+;// Redistributions of source code must retain the above copyright
+;// notice, this list of conditions and the following disclaimer.
+;//
+;// Redistributions in binary form must reproduce the above copyright
+;// notice, this list of conditions and the following disclaimer in the
+;// documentation and/or other materials provided with the
+;// distribution.
+;//
+;// Neither the name of Texas Instruments Incorporated nor the names of
+;// its contributors may be used to endorse or promote products derived
+;// from this software without specific prior written permission.
+;//
+;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;// $
+;//###########################################################################
+
+ .def _DSP28x_usDelay
+ .sect "ramfuncs"
+
+ .global __DSP28x_usDelay
+_DSP28x_usDelay:
+ SUB ACC,#1
+ BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0
+ LRETR
+
+;There is a 9/10 cycle overhead and each loop
+;takes five cycles. The LoopCount is given by
+;the following formula:
+; DELAY_CPU_CYCLES = 9 + 5*LoopCount
+; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
+; The macro DELAY_US(A) performs this calculation for you
+;
+;//===========================================================================
+;// End of file.
+;//===========================================================================
diff --git a/cmd/DSP2833x_Headers_nonBIOS.cmd b/cmd/DSP2833x_Headers_nonBIOS.cmd
new file mode 100644
index 0000000..e318c81
--- /dev/null
+++ b/cmd/DSP2833x_Headers_nonBIOS.cmd
@@ -0,0 +1,214 @@
+/*
+// TI File $Revision: /main/8 $
+// Checkin $Date: June 2, 2008 11:12:24 $
+//###########################################################################
+//
+// FILE: DSP2833x_Headers_nonBIOS.cmd
+//
+// TITLE: DSP2833x Peripheral registers linker command file
+//
+// DESCRIPTION:
+//
+// This file is for use in Non-BIOS applications.
+//
+// Linker command file to place the peripheral structures
+// used within the DSP2833x headerfiles into the correct memory
+// mapped locations.
+//
+// This version of the file includes the PieVectorTable structure.
+// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file
+// which does not include the PieVectorTable structure.
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+*/
+
+MEMORY
+{
+ PAGE 0: /* Program Memory */
+
+ PAGE 1: /* Data Memory */
+
+ DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
+ FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
+ CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
+
+ ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
+
+ XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
+
+ CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
+ CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
+ CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
+
+ PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
+ PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
+
+ DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
+
+ MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
+ MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
+
+ ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
+ ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
+ ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
+ ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
+ ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
+
+ ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
+ ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
+ ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
+ ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
+ ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
+
+ EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */
+ EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */
+ EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */
+ EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */
+ EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */
+ EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */
+
+ ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
+ ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
+ ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
+ ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
+ ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
+ ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
+
+ EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
+ EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
+
+ GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
+ GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
+ GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
+
+ SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
+ SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
+ SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
+ XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
+
+ ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
+
+ SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
+
+ SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
+
+ I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
+
+ CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
+
+ PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
+}
+
+
+SECTIONS
+{
+ PieVectTableFile : > PIE_VECT, PAGE = 1
+
+/*** Peripheral Frame 0 Register Structures ***/
+ DevEmuRegsFile : > DEV_EMU, PAGE = 1
+ FlashRegsFile : > FLASH_REGS, PAGE = 1
+ CsmRegsFile : > CSM, PAGE = 1
+ AdcMirrorFile : > ADC_MIRROR, PAGE = 1
+ XintfRegsFile : > XINTF, PAGE = 1
+ CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
+ CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
+ CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
+ PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
+ DmaRegsFile : > DMA, PAGE = 1
+
+/*** Peripheral Frame 3 Register Structures ***/
+ McbspaRegsFile : > MCBSPA, PAGE = 1
+ McbspbRegsFile : > MCBSPB, PAGE = 1
+
+/*** Peripheral Frame 1 Register Structures ***/
+ ECanaRegsFile : > ECANA, PAGE = 1
+ ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
+ ECanaMboxesFile : > ECANA_MBOX PAGE = 1
+ ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
+ ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
+
+ ECanbRegsFile : > ECANB, PAGE = 1
+ ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
+ ECanbMboxesFile : > ECANB_MBOX PAGE = 1
+ ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
+ ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
+
+ EPwm1RegsFile : > EPWM1 PAGE = 1
+ EPwm2RegsFile : > EPWM2 PAGE = 1
+ EPwm3RegsFile : > EPWM3 PAGE = 1
+ EPwm4RegsFile : > EPWM4 PAGE = 1
+ EPwm5RegsFile : > EPWM5 PAGE = 1
+ EPwm6RegsFile : > EPWM6 PAGE = 1
+
+ ECap1RegsFile : > ECAP1 PAGE = 1
+ ECap2RegsFile : > ECAP2 PAGE = 1
+ ECap3RegsFile : > ECAP3 PAGE = 1
+ ECap4RegsFile : > ECAP4 PAGE = 1
+ ECap5RegsFile : > ECAP5 PAGE = 1
+ ECap6RegsFile : > ECAP6 PAGE = 1
+
+ EQep1RegsFile : > EQEP1 PAGE = 1
+ EQep2RegsFile : > EQEP2 PAGE = 1
+
+ GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
+ GpioDataRegsFile : > GPIODAT PAGE = 1
+ GpioIntRegsFile : > GPIOINT PAGE = 1
+
+/*** Peripheral Frame 2 Register Structures ***/
+ SysCtrlRegsFile : > SYSTEM, PAGE = 1
+ SpiaRegsFile : > SPIA, PAGE = 1
+ SciaRegsFile : > SCIA, PAGE = 1
+ XIntruptRegsFile : > XINTRUPT, PAGE = 1
+ AdcRegsFile : > ADC, PAGE = 1
+ ScibRegsFile : > SCIB, PAGE = 1
+ ScicRegsFile : > SCIC, PAGE = 1
+ I2caRegsFile : > I2CA, PAGE = 1
+
+/*** Code Security Module Register Structures ***/
+ CsmPwlFile : > CSM_PWL, PAGE = 1
+
+/*** Device Part ID Register Structures ***/
+ PartIdRegsFile : > PARTID, PAGE = 1
+
+}
+
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
diff --git a/cmd/F28335.cmd b/cmd/F28335.cmd
new file mode 100644
index 0000000..cee4c10
--- /dev/null
+++ b/cmd/F28335.cmd
@@ -0,0 +1,235 @@
+/*
+// TI File $Revision: /main/10 $
+// Checkin $Date: July 9, 2008 13:43:56 $
+//###########################################################################
+//
+// FILE: F28335.cmd
+//
+// TITLE: Linker Command File For F28335 Device
+//
+//###########################################################################
+// $TI Release: F2833x Support Library v2.00.00.00 $
+// $Release Date: Mon May 27 06:46:54 CDT 2019 $
+// $Copyright:
+// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file,
+// add the header linker command file directly to the project.
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within
+// the memory map.
+//
+// The header linker files are found in \headers\cmd
+//
+// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper
+// locations within the memory map */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to \headers\cmd to the
+ library search path under project->build options, linker tab,
+ library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28335
+ PAGE 0 will be used to organize program sections
+ PAGE 1 will be used to organize data sections
+
+ Notes:
+ Memory blocks on F28335 are uniform (ie same
+ physical memory) in both PAGE 0 and PAGE 1.
+ That is the same memory region should not be
+ defined for both PAGE 0 and PAGE 1.
+ Doing so will result in corruption of program
+ and/or data.
+
+ L0/L1/L2 and L3 memory blocks are mirrored - that is
+ they can be accessed in high memory or low memory.
+ For simplicity only one instance is used in this
+ linker file.
+
+ Contiguous SARAM memory blocks can be combined
+ if required to create a larger memory block.
+ */
+
+
+MEMORY
+{
+PAGE 0: /* Program Memory */
+ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
+
+ ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
+ RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
+ RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
+ RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
+ RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
+ ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
+ ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
+ FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
+ FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
+ FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
+ FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
+ FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
+ FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
+ FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
+ CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
+ BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
+ CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
+ OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
+ ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
+
+ IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
+ IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
+ FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
+ ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
+ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
+ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
+
+PAGE 1 : /* Data Memory */
+ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
+ /* Registers remain on PAGE1 */
+
+ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
+ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
+ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
+ RAML45 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L1 */
+ //RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
+ RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
+ RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
+ ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
+ FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
+}
+
+/* Allocate sections to memory blocks.
+ Note:
+ codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
+ execution when booting to flash
+ ramfuncs user defined section to store functions that will be copied from Flash into RAM
+*/
+
+SECTIONS
+{
+
+ /* Allocate program areas: */
+ .cinit : > FLASHA PAGE = 0
+ .pinit : > FLASHA, PAGE = 0
+ .text : > FLASHA PAGE = 0
+ codestart : > BEGIN PAGE = 0
+ ramfuncs : LOAD = FLASHD,
+ RUN = RAML0,
+ LOAD_START(_RamfuncsLoadStart),
+ LOAD_END(_RamfuncsLoadEnd),
+ RUN_START(_RamfuncsRunStart),
+ LOAD_SIZE(_RamfuncsLoadSize),
+ PAGE = 0
+
+ csmpasswds : > CSM_PWL PAGE = 0
+ csm_rsvd : > CSM_RSVD PAGE = 0
+
+ /* Allocate uninitalized data sections: */
+ .stack : > RAMM1 PAGE = 1
+ .ebss : > RAML45 PAGE = 1
+ .esysmem : > RAMM1 PAGE = 1
+
+ /* Initalized sections go in Flash */
+ /* For SDFlash to program these, they must be allocated to page 0 */
+ .econst : > FLASHA PAGE = 0
+ .switch : > FLASHA PAGE = 0
+
+ /* Allocate IQ math areas: */
+ IQmath : > FLASHC PAGE = 0 /* Math Code */
+ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
+
+ /* Uncomment the section below if calling the IQNexp() or IQexp()
+ functions from the IQMath.lib library in order to utilize the
+ relevant IQ Math table in Boot ROM (This saves space and Boot ROM
+ is 1 wait-state). If this section is not uncommented, IQmathTables2
+ will be loaded into other memory (SARAM, Flash, etc.) and will take
+ up space, but 0 wait-state is possible.
+ */
+ /*
+ IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
+ {
+
+ IQmath.lib (IQmathTablesRam)
+
+ }
+ */
+
+ FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
+
+ /* Allocate DMA-accessible RAM sections: */
+ DMARAML4 : > RAML45, PAGE = 1
+ DMARAML5 : > RAML45, PAGE = 1
+ DMARAML6 : > RAML6, PAGE = 1
+ DMARAML7 : > RAML7, PAGE = 1
+
+ /* Allocate 0x400 of XINTF Zone 7 to storing data */
+ ZONE7DATA : > ZONE7B, PAGE = 1
+
+ /* .reset is a standard section used by the compiler. It contains the */
+ /* the address of the start of _c_int00 for C Code. /*
+ /* When using the boot ROM this section and the CPU vector */
+ /* table is not needed. Thus the default type is set here to */
+ /* DSECT */
+ .reset : > RESET, PAGE = 0, TYPE = DSECT
+ vectors : > VECTORS PAGE = 0, TYPE = DSECT
+
+ /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+ .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+
diff --git a/drivers/mcbsp.c b/drivers/mcbsp.c
new file mode 100644
index 0000000..26bfc16
--- /dev/null
+++ b/drivers/mcbsp.c
@@ -0,0 +1,144 @@
+#include "DSP28x_Project.h"
+#include "drivers/sx1255_tx.h"
+#include "drivers/sx1255_rx.h"
+
+void mcbspa_init(void)
+{
+ Uint16 i;
+ EALLOW;
+ McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
+ McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
+
+ McbspaRegs.SPCR1.bit.RJUST = 2; // left-justify word in DRR and zero-fill LSBs
+
+ McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
+
+ McbspaRegs.SPCR1.bit.RINTM = 0; // Configure McBSP interrupts
+ McbspaRegs.SPCR2.bit.XINTM = 0;
+
+ McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
+ McbspaRegs.RCR1.all=0x0;
+
+ McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
+ McbspaRegs.XCR1.all=0x0;
+
+ McbspaRegs.RCR2.bit.RWDLEN2 = 2; // 32-BIT OPERATION
+ McbspaRegs.RCR1.bit.RWDLEN1 = 2;
+ McbspaRegs.XCR2.bit.XWDLEN2 = 2;
+ McbspaRegs.XCR1.bit.XWDLEN1 = 2;
+
+ McbspaRegs.RCR2.bit.RPHASE = 1; // Dual-phase frame
+ McbspaRegs.RCR2.bit.RFRLEN2 = 0; // Recv frame length = 1 word in phase2
+ McbspaRegs.RCR1.bit.RFRLEN1 = 0; // Recv frame length = 1 word in phase1
+
+ McbspaRegs.XCR2.bit.XPHASE = 1; // Dual-phase frame
+ McbspaRegs.XCR2.bit.XFRLEN2 = 0; // Xmit frame length = 1 word in phase2
+ McbspaRegs.XCR1.bit.XFRLEN1 = 0; // Xmit frame length = 1 word in phase1
+
+ McbspaRegs.RCR2.bit.RDATDLY = 1; // n = n-bit data delay (max 2) CRITICAL PARAMETER !!!
+ McbspaRegs.XCR2.bit.XDATDLY = 1; // If LRP (AIC23) = 0, X/RDATDLY=0, if LRP=1, X/RDATDLY=1
+
+ McbspaRegs.SRGR2.bit.FPER = 0x0002; // Does not matter
+ McbspaRegs.SRGR1.all=0x0001; // Frame Width = 1 CLKG period, CLKGDV must be 1 as slave!!
+ // SRG clocked by LSPCLK - SRG clock MUST be at least 2x external data shift clk
+
+ McbspaRegs.PCR.all=0x0000; // Frame sync generated externally, CLKX/CLKR driven
+ McbspaRegs.PCR.bit.FSXM = 0; // FSX is always an i/p signal
+ McbspaRegs.PCR.bit.FSRM = 0; // FSR is always an i/p signal
+ McbspaRegs.PCR.bit.SCLKME = 0;
+
+ McbspaRegs.PCR.bit.FSRP = 1; // 1-FSRP is active low (L-channel first)
+ McbspaRegs.PCR.bit.FSXP = 1 ; // 1-FSXP is active low (L-channel first)
+ McbspaRegs.PCR.bit.CLKRP = 0; // 1-Rcvd data sampled on rising edge of CLKR
+ McbspaRegs.PCR.bit.CLKXP = 1; // 0- Tx data sampled on falling edge of CLKX
+ McbspaRegs.SRGR2.bit.CLKSM = 1; // LSPCLK is clock source for SRG
+
+ McbspaRegs.PCR.bit.CLKXM = 0; // 0-MCLKXA is an i/p driven by an external clock
+ McbspaRegs.PCR.bit.CLKRM = 0; // MCLKRA is an i/p signal
+
+ McbspaRegs.SPCR2.all |=0x00C0; // Frame sync & sample rate generators pulled out of reset
+
+ for (i = 0;i < 100;i++) {} //delay in McBsp init. must be at least 2 SRG cycles
+
+ McbspaRegs.SPCR2.bit.XRST=1; // Enable Transmitter
+ McbspaRegs.SPCR1.bit.RRST=1; // Enable Receiver
+
+ EDIS;
+
+ for (i = 0;i < 100;i++) {} //delay in McBsp init. must be at least 2 SRG cycles
+}
+
+void dma_init(void)
+{
+ EALLOW;
+ DmaRegs.DMACTRL.bit.HARDRESET = 1;
+ asm(" NOP");
+
+ DmaRegs.PRIORITYCTRL1.bit.CH1PRIORITY = 0;
+ /* DMA Channel 1 - McBSP-A Receive */
+ DmaRegs.CH1.BURST_SIZE.all = 0; // 2 16-bit words/burst (1 32-bit word per RRDY) - memory address bumped up by 1 internally
+ DmaRegs.CH1.SRC_BURST_STEP = 0; // DRR2 must be read first & then DRR1. Increment by 1. Hence a value of +1. (This is a 2's C #)
+ DmaRegs.CH1.DST_BURST_STEP = 0; // Copy DRR2 data to address N+1 and DRR1 data to N. Hence -1 (32-bit read= read addr N+1 as MSB, then N as LSB)
+ DmaRegs.CH1.TRANSFER_SIZE = 511; // Interrupt every 1024 (n+1) bursts. McBSP handles 16-bit data only (DRR2 and DRR1 are 16-bit registers)
+
+ DmaRegs.CH1.SRC_TRANSFER_STEP = 0; // Decrement source address by 1 (from DRR1 back to DRR2) after processing a burst of data
+ DmaRegs.CH1.DST_TRANSFER_STEP = 1; // After copying L-C data, move down to R-C data in a given buffer
+
+ DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // First read from DRR2
+ DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all;
+
+ DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // After LEFT(1) and then RIGHT(2), go back to LEFT buffer
+ DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Arbitary large value. We'll never hit this.....
+
+ DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clears peripheral interrupt, sync and sycn error flags
+ DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1;
+ DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;
+
+ DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt Enable
+ DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Generates Interrupt at beginning of transfer
+ DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral Interrupt Enable
+ DmaRegs.CH1.MODE.bit.PERINTSEL = 15; // McBSP MREVTA
+ DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Continuous mode
+
+ /* DMA Channel 2 - McBSP-A Transmit */
+ DmaRegs.CH2.BURST_SIZE.all = 0; // 2 16-bit words/burst (1 32-bit word per XRDY) - value bumped up by 1 internally
+ DmaRegs.CH2.SRC_BURST_STEP = 0; // Copy data at address N+1 to DXR2 first then data at N to DXR1. Hence -1
+ DmaRegs.CH2.DST_BURST_STEP = 0; // DXR2 must be written to first & then DXR1. Increment by 1. Hence a value of +1. (This is a 2's C #)
+ DmaRegs.CH2.TRANSFER_SIZE = 511; // Interrupt every 1024 (n+1) 16-bit words. McBSP still handles 16-bit data only in registers
+
+ DmaRegs.CH2.SRC_TRANSFER_STEP = 1; // After copying L-C data, move down to R-C data in a given buffer
+ DmaRegs.CH2.DST_TRANSFER_STEP = 0; // Decrement dest. address by 1 (DXR1 back to DXR2) after processing a burst of data
+
+ DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // First write to DXR2
+ DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all;
+
+ DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // After LEFT(1) and then RIGHT(2), go back to LEFT buffer
+ DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Arbitary large value. We'll never hit this.....
+
+ DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clears peripheral interrupt, sync and sync error flags
+ DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1;
+ DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;
+
+ DmaRegs.CH2.MODE.bit.CHINTE = 1; // Channel Interrupt Enable
+ DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Generates Interrupt at beginning of transfer
+ DmaRegs.CH2.MODE.bit.PERINTE = 1; // Peripheral Interrupt Enable
+ DmaRegs.CH2.MODE.bit.PERINTSEL = 14; // McBSP MXEVTA
+ DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Continuous mode
+ EDIS;
+
+ sx1255_tx_reset_state();
+ sx1255_rx_reset_state();
+
+ EALLOW;
+ PieVectTable.DINTCH1 = &SX1255_RX_DMA_ISR;
+ PieVectTable.DINTCH2 = &SX1255_TX_DMA_ISR;
+
+ PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable INTx.1 of INT7 (DMA CH1)
+ PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable INTx.2 of INT7 (DMA CH2)
+
+ DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start rx on Channel 1
+ DmaRegs.CH2.CONTROL.bit.RUN = 1; // Start rx on Channel 1
+ EDIS;
+
+ IER |= 0x0040; // Enable INT7
+}
diff --git a/drivers/mcbsp.h b/drivers/mcbsp.h
new file mode 100644
index 0000000..5c26b83
--- /dev/null
+++ b/drivers/mcbsp.h
@@ -0,0 +1,15 @@
+#ifndef DRIVERS_MCBSP_H_
+#define DRIVERS_MCBSP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void mcbspa_init(void);
+void dma_init(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* DRIVERS_MCBSP_H_ */
diff --git a/drivers/spi.c b/drivers/spi.c
new file mode 100644
index 0000000..b1f8e74
--- /dev/null
+++ b/drivers/spi.c
@@ -0,0 +1,34 @@
+#include "DSP28x_Project.h"
+
+int16 spia_xmit(int16 spiTxData)
+{
+ SpiaRegs.SPITXBUF = spiTxData;
+ while (SpiaRegs.SPISTS.bit.INT_FLAG != 1) {} // Wait until character has been transferred
+ return SpiaRegs.SPIRXBUF; // Clears INT_FLAG
+}
+
+void spia_init(void)
+{
+ SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Hold SPI in reset
+ SpiaRegs.SPIFFTX.bit.SPIRST = 0; // Hold both FIFOs in reset
+ SpiaRegs.SPIFFRX.bit.RXFIFORESET = 0; // Hold RX FIFO in reset
+
+ SpiaRegs.SPICCR.bit.SPICHAR = 15; // 16 bit char
+ SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; // Output on falling edge
+ SpiaRegs.SPICCR.bit.SPILBK = 0; // No Loopback
+ SpiaRegs.SPIBRR = 99; // Baud rate select
+
+ SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Master mode
+ SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // No Delay
+ SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0; // Disable
+ SpiaRegs.SPICTL.bit.TALK = 1; // Enable TX
+ SpiaRegs.SPICTL.bit.SPIINTENA = 1; // Enable Interrupt Request
+ SpiaRegs.SPIPRI.bit.FREE = 0; // Set so brkpts don't disturb xmission
+
+ SpiaRegs.SPIFFRX.bit.RXFFIL = 1; // Set flag after 3 bytes rcv'd
+ SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Clear any spurious Int Flag
+ SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Release RX FIFO from reset
+ SpiaRegs.SPIFFTX.bit.SPIRST = 1; // Release both FIFOs from reset
+ SpiaRegs.SPIFFTX.bit.SPIFFENA = 0; // Disable FIFOs feature
+ SpiaRegs.SPICCR.bit.SPISWRESET = 1; // Release SPI from reset
+}
diff --git a/drivers/spi.h b/drivers/spi.h
new file mode 100644
index 0000000..bf31d4d
--- /dev/null
+++ b/drivers/spi.h
@@ -0,0 +1,15 @@
+#ifndef DRIVERS_SPI_H_
+#define DRIVERS_SPI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int16 spia_xmit(int16 spiTxData);
+void spia_init(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* DRIVERS_SPI_H_ */
diff --git a/drivers/sx1255.c b/drivers/sx1255.c
new file mode 100644
index 0000000..4394302
--- /dev/null
+++ b/drivers/sx1255.c
@@ -0,0 +1,99 @@
+#include "DSP28x_Project.h"
+#include "drivers/spi.h"
+#include "drivers/mcbsp.h"
+
+#define SX1255_VERSION 0x11
+
+#define SX1255_REG_MODE 0x0
+#define SX1255_REG_FRFH_RX 0x1
+#define SX1255_REG_FRFM_RX 0x2
+#define SX1255_REG_FRFL_RX 0x3
+#define SX1255_REG_FRFH_TX 0x4
+#define SX1255_REG_FRFM_TX 0x5
+#define SX1255_REG_FRFL_TX 0x6
+#define SX1255_REG_VERSION 0x7
+#define SX1255_REG_TXFE1 0x8
+#define SX1255_REG_TXFE2 0x9
+#define SX1255_REG_TXFE3 0xA
+#define SX1255_REG_TXFE4 0xB
+#define SX1255_REG_RXFE1 0xC
+#define SX1255_REG_RXFE2 0xD
+#define SX1255_REG_RXFE3 0xE
+#define SX1255_REG_IO_MAP 0xF
+#define SX1255_REG_CK_SEL 0x10
+#define SX1255_REG_STAT 0x11
+#define SX1255_REG_IISM 0x12
+#define SX1255_REG_DIG_BRIDGE 0x13
+#define SX1255_REG_XOSC 0x28//This speciall reg was found in libloragw
+
+Uint16 sx1255_spi_read(Uint16 reg_name)
+{
+ int16 spi_value = 0;
+ reg_name &= 0x7F;
+ spi_value = reg_name << 8;
+ spi_value |= 0xFF;
+ return (spia_xmit(spi_value) & 0xFF);
+}
+
+void sx1255_spi_write(Uint16 reg_name,Uint16 value)
+{
+ Uint16 spi_value = 0;
+ reg_name &= 0x7F;
+ value &= 0xFF;
+ spi_value = reg_name << 8;
+ spi_value |= (value | 0x8000);
+ spia_xmit(spi_value);
+}
+
+void sx1255_reset(void)
+{
+ //reset SX1255
+ GpioDataRegs.GPASET.bit.GPIO8 = 1;
+ DELAY_US(1000);
+ GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
+ DELAY_US(50000);
+}
+
+void sx1255_init(void)
+{
+ Uint16 sx1255_hw_ver;
+
+ spia_init();
+ dma_init();
+ mcbspa_init();
+
+ sx1255_reset();
+
+ sx1255_hw_ver = sx1255_spi_read(SX1255_REG_VERSION);
+
+ if(sx1255_hw_ver == SX1255_VERSION)
+ {
+ sx1255_spi_write(SX1255_REG_XOSC,((0x00 << 4) | (0x0D)));
+
+ sx1255_spi_write(SX1255_REG_CK_SEL,0b0010);
+
+ sx1255_spi_write(SX1255_REG_TXFE1,((0x02 << 4) | (0x0E)));
+ sx1255_spi_write(SX1255_REG_TXFE2,((0x04 << 3) | (0x04)));
+ sx1255_spi_write(SX1255_REG_TXFE3,0x1F);
+ sx1255_spi_write(SX1255_REG_TXFE4,0x0);
+
+
+ sx1255_spi_write(SX1255_REG_RXFE1,((0x03 << 5) | (0x0F << 1) | (0x00)));
+ sx1255_spi_write(SX1255_REG_RXFE2,((0x01 << 5) | (0x05 << 2) | (0x01)));
+ sx1255_spi_write(SX1255_REG_RXFE3,0x0);
+
+ //set up i2s mode
+ sx1255_spi_write(SX1255_REG_IISM,((0x00 << 7) | (0x00 << 6) | (0x02 << 4) | (0x03)));
+ sx1255_spi_write(SX1255_REG_DIG_BRIDGE,((0x00 << 7) | (0x00 << 6) | (0x05 << 3) | (0x01 << 2)));
+
+ if((sx1255_spi_read(SX1255_REG_DIG_BRIDGE) & 0x2) == 0)
+ {
+ do{
+ //sx1255_spi_write(SX1255_REG_MODE,0xF);//enable RX/TX,PA
+ sx1255_spi_write(SX1255_REG_MODE,0xD);//enable TX,PA
+ //sx1255_spi_write(SX1255_REG_MODE,0x3);//enable RX
+ DELAY_US(50000);
+ } while((sx1255_spi_read(SX1255_REG_STAT) & 0x03) == 0);
+ }
+ }
+}
diff --git a/drivers/sx1255.h b/drivers/sx1255.h
new file mode 100644
index 0000000..017d3d9
--- /dev/null
+++ b/drivers/sx1255.h
@@ -0,0 +1,14 @@
+#ifndef DRIVERS_SX1255_H_
+#define DRIVERS_SX1255_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void sx1255_init(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* DRIVERS_SX1255_H_ */
diff --git a/drivers/sx1255_rx.c b/drivers/sx1255_rx.c
new file mode 100644
index 0000000..cefe771
--- /dev/null
+++ b/drivers/sx1255_rx.c
@@ -0,0 +1,40 @@
+#include "DSP28x_Project.h"
+#include "drivers/spi.h"
+#include "drivers/mcbsp.h"
+#include "libs/safepipe/safepipe.h"
+#include "libs/fsk/fsk_demod.h"
+
+int16 sx1255_rx_overrun = 0;
+
+void sx1255_rx_reset_state(void)
+{
+ Uint16 *new_buf;
+ fsk_demod_init();
+ new_buf = safepipe_get_current_write_buf(&fsk_demod_pipe);
+ EALLOW;
+ DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)new_buf;
+ DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)new_buf;
+ EDIS;
+}
+
+interrupt void SX1255_RX_DMA_ISR(void) // DMA Ch1 - McBSP-A Rx
+{
+ Uint16 *new_buf;
+ if(safepipe_writeable(&fsk_demod_pipe))
+ {
+ safepipe_write_update(&fsk_demod_pipe);
+ }
+ else
+ {
+ sx1255_rx_overrun = 1;
+ }
+
+ new_buf = safepipe_get_current_write_buf(&fsk_demod_pipe);
+ EALLOW;
+ DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)new_buf;
+ DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)new_buf;
+ EDIS;
+// To receive more interrupts from this PIE group, acknowledge this interrupt
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+ EDIS;
+}
diff --git a/drivers/sx1255_rx.h b/drivers/sx1255_rx.h
new file mode 100644
index 0000000..4345b29
--- /dev/null
+++ b/drivers/sx1255_rx.h
@@ -0,0 +1,15 @@
+#ifndef DRIVERS_SX1255_RX_H_
+#define DRIVERS_SX1255_RX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+interrupt void SX1255_RX_DMA_ISR(void);
+void sx1255_rx_reset_state(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* DRIVERS_SX1255_RX_H_ */
diff --git a/drivers/sx1255_tx.c b/drivers/sx1255_tx.c
new file mode 100644
index 0000000..fecc224
--- /dev/null
+++ b/drivers/sx1255_tx.c
@@ -0,0 +1,42 @@
+#include "DSP28x_Project.h"
+#include "drivers/spi.h"
+#include "drivers/mcbsp.h"
+#include "libs/safepipe/safepipe.h"
+#include "libs/fsk/fsk_mod.h"
+
+int16 sx1255_tx_overrun = 0;
+
+void sx1255_tx_reset_state(void)
+{
+ Uint16 *new_buf;
+ fsk_mod_init();
+ new_buf = safepipe_get_current_read_buf(&fsk_mod_pipe);
+ EALLOW;
+ DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)new_buf;
+ DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)new_buf;
+ EDIS;
+}
+
+// INT7.2
+interrupt void SX1255_TX_DMA_ISR(void) // DMA Ch2 - McBSP-A Tx
+{
+ Uint16 *new_buf;
+
+ if(safepipe_readable(&fsk_mod_pipe))
+ {
+ safepipe_read_update(&fsk_mod_pipe);
+ }
+ else
+ {
+ sx1255_tx_overrun = 1;
+ }
+
+ new_buf = safepipe_get_current_read_buf(&fsk_mod_pipe);
+
+ EALLOW;
+ DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)new_buf;
+ DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)new_buf;
+ EDIS;
+
+ PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt
+}
diff --git a/drivers/sx1255_tx.h b/drivers/sx1255_tx.h
new file mode 100644
index 0000000..708a0d6
--- /dev/null
+++ b/drivers/sx1255_tx.h
@@ -0,0 +1,16 @@
+#ifndef DRIVERS_SX1255_TX_H_
+#define DRIVERS_SX1255_TX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+interrupt void SX1255_TX_DMA_ISR(void);
+void sx1255_tx_reset_state(void);
+void sx1255_tx_bit(int16 bit);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* DRIVERS_SX1255_TX_H_ */
diff --git a/libs/complex/complex.h b/libs/complex/complex.h
new file mode 100644
index 0000000..c9b5cc2
--- /dev/null
+++ b/libs/complex/complex.h
@@ -0,0 +1,18 @@
+#ifndef LIBS_COMPLEX_COMPLEX_H_
+#define LIBS_COMPLEX_COMPLEX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+ int16 I;
+ int16 Q;
+}short_complex_t;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_COMPLEX_COMPLEX_H_ */
diff --git a/libs/crc/crc32.c b/libs/crc/crc32.c
new file mode 100644
index 0000000..59c107a
--- /dev/null
+++ b/libs/crc/crc32.c
@@ -0,0 +1,60 @@
+#include "DSP28x_Project.h"
+
+static Uint32 crc32_lut[256] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+ 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+ 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+ 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+ 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+ 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+ 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+ 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+ 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+ 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+ 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+ 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+ 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+ 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+ 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+
+Uint32 crc32(void *data, Uint32 len)
+{
+ Uint32 i;
+ Uint16 *bytes = (Uint16 *) data;
+ Uint32 crc = 0xffffffff;
+
+ for (i = 0; i < len; i++) {
+ crc = (crc >> 8) ^ crc32_lut[(crc ^ (bytes[i] & 0xFF)) & 0xff];
+ }
+
+ return ~crc;
+}
diff --git a/libs/crc/crc32.h b/libs/crc/crc32.h
new file mode 100644
index 0000000..961fe48
--- /dev/null
+++ b/libs/crc/crc32.h
@@ -0,0 +1,14 @@
+#ifndef LIBS_CRC_CRC32_H_
+#define LIBS_CRC_CRC32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+Uint32 crc32(void *data, Uint32 len);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_CRC_CRC32_H_ */
diff --git a/libs/fsk/fsk_ang.c b/libs/fsk/fsk_ang.c
new file mode 100644
index 0000000..380a255
--- /dev/null
+++ b/libs/fsk/fsk_ang.c
@@ -0,0 +1,37 @@
+#include "DSP28x_Project.h"
+#include "libs/complex/complex.h"
+#include "libs/fsk/fsk_table.h"
+
+#pragma CODE_SECTION(angle_unwrap,"ramfuncs");
+static int16 angle_unwrap(int16 angle_prev, int16 angle)
+{
+ int32 diff = (int32)angle - (int32)angle_prev;
+ if (diff > 18000){
+ return diff - 36000;
+ }else if (diff < -18000){
+ return diff + 36000;
+ }
+ return diff;
+}
+
+#pragma CODE_SECTION(fsk_angle,"ramfuncs");
+void fsk_angle(short_complex_t *buf_in, int16 *buf_out, Uint16 bufSize)
+{
+ int i,new_a;
+ static int16 old_a = 0;
+ for(i=0;i<256;i++)
+ {
+ new_a = atan2_table_16(buf_in[i].Q,buf_in[i].I);
+ buf_out[i] = angle_unwrap(old_a,new_a);
+ if(buf_out[i] > 5000)
+ {
+ buf_out[i] = 5000;
+ }
+ else if(buf_out[i] < -5000)
+ {
+ buf_out[i] = -5000;
+ }
+ old_a = new_a;
+ }
+}
+
diff --git a/libs/fsk/fsk_ang.h b/libs/fsk/fsk_ang.h
new file mode 100644
index 0000000..4e3bc36
--- /dev/null
+++ b/libs/fsk/fsk_ang.h
@@ -0,0 +1,14 @@
+#ifndef LIBS_FSK_FSK_ANG_H_
+#define LIBS_FSK_FSK_ANG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void fsk_angle(short_complex_t *buf_in, int16 *buf_out, Uint16 bufSize);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_ANG_H_ */
diff --git a/libs/fsk/fsk_corr.c b/libs/fsk/fsk_corr.c
new file mode 100644
index 0000000..5a3b332
--- /dev/null
+++ b/libs/fsk/fsk_corr.c
@@ -0,0 +1,79 @@
+#include "DSP28x_Project.h"
+#include "libs/fsk/fsk_corr.h"
+
+#define PREAMBLE_CODE 0xA5
+
+static inline int16 get_preamble_bit(Uint16 bit)
+{
+ return ((PREAMBLE_CODE >> bit) & 0x1);
+}
+
+#pragma CODE_SECTION(fsk_corr,"ramfuncs");
+int16 fsk_corr(int16 *buf, Uint16 bufSize, Uint16 *position)
+{
+ Uint16 window_end,i,j,k;
+ int32 corr_sum,corr_temp;
+ int16 corr_found_position = -1;
+
+ if(bufSize <= 256)
+ {
+ *position = 0;
+ return 0;
+ }
+ else
+ {
+ window_end = bufSize - 256;
+ for(i=0;(i -24000)
+ {
+ break;
+ }
+ else
+ {
+ corr_sum -= corr_temp;
+ }
+ }
+ else
+ {
+ if(corr_temp < 24000)
+ {
+ break;
+ }
+ else
+ {
+ corr_sum += corr_temp;
+ }
+ }
+ if(j==7)
+ {
+ if(corr_found_position < 0)
+ {
+ corr_found_position = i;
+ }
+ }
+ }
+ }
+
+ if(corr_found_position > 0)
+ {
+ *position = corr_found_position;
+ return 1;
+ }
+ else
+ {
+ *position = i;
+ return 0;
+ }
+ }
+}
diff --git a/libs/fsk/fsk_corr.h b/libs/fsk/fsk_corr.h
new file mode 100644
index 0000000..4e7c9da
--- /dev/null
+++ b/libs/fsk/fsk_corr.h
@@ -0,0 +1,15 @@
+#ifndef LIBS_FSK_FSK_CORR_H_
+#define LIBS_FSK_FSK_CORR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int16 fsk_corr(int16 *buf, Uint16 bufSize, Uint16 *position);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+
+#endif /* LIBS_FSK_FSK_CORR_H_ */
diff --git a/libs/fsk/fsk_dc.c b/libs/fsk/fsk_dc.c
new file mode 100644
index 0000000..7f257ed
--- /dev/null
+++ b/libs/fsk/fsk_dc.c
@@ -0,0 +1,65 @@
+#include "DSP28x_Project.h"
+#include "libs/complex/complex.h"
+
+int32 dc_sum_i = 0,dc_sum_q = 0;
+int16 dc_i = 0,dc_q = 0;
+
+#pragma CODE_SECTION(fsk_iq_dc,"ramfuncs");
+void fsk_iq_dc(short_complex_t *buf, Uint16 bufSize, int16 hold)
+{
+ Uint16 i;
+ if(!hold)
+ {
+ dc_sum_i = dc_sum_q = 0;
+ for(i=0;i
+
+short_complex_t sx1255_rx_buffer[4][256];
+
+safepipe_t fsk_demod_pipe;
+
+const void *fsk_demod_buf_p[4] = {sx1255_rx_buffer[0],sx1255_rx_buffer[1],sx1255_rx_buffer[2],sx1255_rx_buffer[3]};
+
+Uint16 demod_buf_position = 0;
+Uint16 demod_state = 0;
+int16 demod_raw_buf[512];
+Uint16 decode_raw_buff[38];
+//int16 sx1255_raw_i[256];
+//int16 sx1255_raw_q[256];
+//int16 filter_raw_i[256];
+//int16 filter_raw_q[256];
+//int16 norm_raw_i[256];
+//int16 norm_raw_q[256];
+
+static inline void shift_buf(int16 * buf, Uint16 shift_position)
+{
+ Uint16 i;
+ Uint16 shift_len = demod_buf_position - shift_position;
+ for(i=0;i= 4000)
+ {
+ return 1;
+ }
+ else
+ {
+ return -1;
+ }
+ }
+ else if((bit_earl == 1) && (bit_curr == 0) && (bit_late == 1))
+ {
+ delta = epl_sum(buf_earl) - epl_sum(buf_late);
+ abs_delta = (delta < 0) ? (0 - delta) : (delta);
+ if(abs_delta < 4000)
+ {
+ return 0;
+ }
+ else if(delta >= 4000)
+ {
+ return -1;
+ }
+ else
+ {
+ return 1;
+ }
+ }
+ else
+ {
+ return 0;
+ }
+}
diff --git a/libs/fsk/fsk_est.h b/libs/fsk/fsk_est.h
new file mode 100644
index 0000000..e1f3be0
--- /dev/null
+++ b/libs/fsk/fsk_est.h
@@ -0,0 +1,14 @@
+#ifndef LIBS_FSK_FSK_EST_H_
+#define LIBS_FSK_FSK_EST_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int16 fsk_est(int16 *buf,int16 bit_earl,int16 bit_curr,int16 bit_late);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_EST_H_ */
diff --git a/libs/fsk/fsk_filter.c b/libs/fsk/fsk_filter.c
new file mode 100644
index 0000000..8078da9
--- /dev/null
+++ b/libs/fsk/fsk_filter.c
@@ -0,0 +1,79 @@
+#include "DSP28x_Project.h"
+#include "libs/complex/complex.h"
+
+Uint16 rx_ins1 = 0;
+Uint16 rx_ins2 = 64;
+
+short_complex_t rx_filter_buf[128];
+
+#pragma CODE_SECTION(fsk_rx_filter,"ramfuncs");
+void fsk_rx_filter(short_complex_t *buf, const int16* filter_table, Uint16 count)
+{
+ Uint16 i,j,k;
+ int32 result_i,result_q;
+
+ for (i = 0; i < count; i ++)
+ {
+ result_i = 0;
+ result_q = 0;
+
+ rx_filter_buf[rx_ins1].I = rx_filter_buf[rx_ins2].I = buf[i].I;
+ rx_filter_buf[rx_ins1].Q = rx_filter_buf[rx_ins2].Q = buf[i].Q;
+
+ for (j = 0, k = rx_ins2; j < 64; j++, k--)
+ {
+ result_i += (int32)filter_table[j] * (int32)rx_filter_buf[k].I;
+ result_q += (int32)filter_table[j] * (int32)rx_filter_buf[k].Q;
+ }
+
+ buf[i].I = result_i >> 16;
+ buf[i].Q = result_q >> 16;
+
+ rx_ins2++;
+ if (rx_ins2 == 128) {
+ rx_ins1 = 0;
+ rx_ins2 = 64;
+ } else {
+ rx_ins1++;
+ }
+ }
+}
+
+Uint16 tx_ins1 = 0;
+Uint16 tx_ins2 = 64;
+
+short_complex_t tx_filter_buf[128];
+
+#pragma CODE_SECTION(fsk_tx_filter,"ramfuncs");
+void fsk_tx_filter(short_complex_t *buf, const int16* filter_table, Uint16 count)
+{
+ Uint16 i,j,k;
+ int32 result_i,result_q;
+
+ for (i = 0; i < count; i ++)
+ {
+ result_i = 0;
+ result_q = 0;
+
+ tx_filter_buf[tx_ins1].I = tx_filter_buf[tx_ins2].I = buf[i].I;
+ tx_filter_buf[tx_ins1].Q = tx_filter_buf[tx_ins2].Q = buf[i].Q;
+
+ for (j = 0, k = tx_ins2; j < 64; j++, k--)
+ {
+ result_i += (int32)filter_table[j] * (int32)tx_filter_buf[k].I;
+ result_q += (int32)filter_table[j] * (int32)tx_filter_buf[k].Q;
+ }
+
+ buf[i].I = result_i >> 16;
+ buf[i].Q = result_q >> 16;
+
+ tx_ins2++;
+ if (tx_ins2 == 128) {
+ tx_ins1 = 0;
+ tx_ins2 = 64;
+ } else {
+ tx_ins1++;
+ }
+ }
+}
+
diff --git a/libs/fsk/fsk_filter.h b/libs/fsk/fsk_filter.h
new file mode 100644
index 0000000..e965c83
--- /dev/null
+++ b/libs/fsk/fsk_filter.h
@@ -0,0 +1,15 @@
+#ifndef LIBS_FSK_FSK_FILTER_H_
+#define LIBS_FSK_FSK_FILTER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void fsk_rx_filter(short_complex_t *buf, const int16* filter_table, Uint16 count);
+void fsk_tx_filter(short_complex_t *buf, const int16* filter_table, Uint16 count);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_FILTER_H_ */
diff --git a/libs/fsk/fsk_frame.h b/libs/fsk/fsk_frame.h
new file mode 100644
index 0000000..4aa0150
--- /dev/null
+++ b/libs/fsk/fsk_frame.h
@@ -0,0 +1,19 @@
+#ifndef LIBS_FSK_FSK_FRAME_H_
+#define LIBS_FSK_FSK_FRAME_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+ int16 type;
+ int16 addr;
+ int16 data[30];
+}fsk_frame_t;
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_FRAME_H_ */
diff --git a/libs/fsk/fsk_gen.c b/libs/fsk/fsk_gen.c
new file mode 100644
index 0000000..1dca0b8
--- /dev/null
+++ b/libs/fsk/fsk_gen.c
@@ -0,0 +1,49 @@
+#include "DSP28x_Project.h"
+#include "libs/complex/complex.h"
+#include "libs/fsk/fsk_table.h"
+
+#include
+#include
+
+#define N_POINT 16
+
+#define MARKFREQ 1
+#define SPACEFREQ -1
+
+int32 GAIN_SPACE = 1; // SPACE Gain
+int32 GAIN_MARK = 1; // MARK Gain
+
+Uint16 phasePosition = 0;
+
+#pragma CODE_SECTION(fsk_gen,"ramfuncs");
+void fsk_gen(short_complex_t *buf,int16 txBit, Uint16 bufSize)
+{
+ int32 dacGain;
+ int16 phaseStep;
+ int16 x;
+ switch (txBit)
+ {
+ case SPACEFREQ:
+ dacGain = GAIN_SPACE;
+ phaseStep = 1;
+ break;
+ case MARKFREQ:
+ dacGain = GAIN_MARK;
+ phaseStep = -1;
+ break;
+ default:
+ dacGain = 0;
+ phaseStep = 0;
+ break;
+ }
+
+ for(x=0;x
+
+short_complex_t sx1255_tx_buffer[4][256];
+
+safepipe_t fsk_mod_pipe;
+Uint16 mod_state = 0;
+Uint16 send_position = 0;
+Uint16 send_raw_buff[38];
+
+//int16 raw_send_i[256];
+//int16 raw_send_q[256];
+
+const void *fsk_mod_buf_p[4] = {sx1255_tx_buffer[0],sx1255_tx_buffer[1],sx1255_tx_buffer[2],sx1255_tx_buffer[3]};
+
+void fsk_mod_init(void)
+{
+ memset(sx1255_tx_buffer,0,sizeof(sx1255_tx_buffer));
+ safepipe_init(&fsk_mod_pipe,4,(void **)fsk_mod_buf_p);
+}
+
+#pragma CODE_SECTION(fsk_mod_loop,"ramfuncs");
+void fsk_mod_loop(void)
+{
+ short_complex_t *write_buf;
+ fsk_frame_t raw_frame;
+ int16 i,txBit;
+ if(safepipe_writeable(&fsk_mod_pipe))
+ {
+ write_buf = safepipe_get_current_write_buf(&fsk_mod_pipe);
+
+ if(mod_state == 0)
+ {
+ if(link_tx_layer_send_cb(&raw_frame))
+ {
+ mod_state = 1;
+ fsk_pack(send_raw_buff,&raw_frame);
+ }
+ }
+
+ if(mod_state == 1)
+ {
+ for(i=0;i<8;i++)
+ {
+ txBit = (send_raw_buff[send_position] >> (7 - i)) & 0x1;
+ if(txBit)
+ {
+ fsk_gen(write_buf + (32 * i),1,32);
+ }
+ else
+ {
+ fsk_gen(write_buf + (32 * i),-1,32);
+ }
+ }
+ send_position++;
+ if(send_position == 38)
+ {
+ send_position = 0;
+ mod_state = 0;
+ }
+ }
+ else
+ {
+ fsk_gen(write_buf,0,256);
+ }
+
+ fsk_tx_filter(write_buf, filterTable, 256);
+ fsk_dac_dc(write_buf, 256);
+
+ //for(i=0;i<256;i++)
+ //{
+ // raw_send_i[i] = write_buf[i].I;
+ // raw_send_q[i] = write_buf[i].Q;
+ //}
+
+ safepipe_write_update(&fsk_mod_pipe);
+ }
+}
diff --git a/libs/fsk/fsk_mod.h b/libs/fsk/fsk_mod.h
new file mode 100644
index 0000000..f286618
--- /dev/null
+++ b/libs/fsk/fsk_mod.h
@@ -0,0 +1,16 @@
+#ifndef LIBS_FSK_FSK_MOD_H_
+#define LIBS_FSK_FSK_MOD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern safepipe_t fsk_mod_pipe;
+void fsk_mod_init(void);
+void fsk_mod_loop(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_MOD_H_ */
diff --git a/libs/fsk/fsk_norm.c b/libs/fsk/fsk_norm.c
new file mode 100644
index 0000000..cb35da5
--- /dev/null
+++ b/libs/fsk/fsk_norm.c
@@ -0,0 +1,39 @@
+#include "DSP28x_Project.h"
+#include "libs/complex/complex.h"
+
+int32 power2_sum = 0;
+int32 power2 = 0;
+
+#pragma CODE_SECTION(fsk_norm,"ramfuncs");
+void fsk_norm(short_complex_t *buf, Uint16 bufSize, int16 hold)
+{
+ Uint16 i;
+ int32 power;
+ Uint16 power_filter = 0;
+ if(!hold)
+ {
+ power2_sum = 0;
+ power2 = 0;
+
+ for(i=0;i 30000000)
+ {
+ //Blank impulse power
+ buf[i].I = buf[i].Q = 0;
+ }
+ else
+ {
+ power2_sum += power;
+ power_filter++;
+ }
+ power2 = power2_sum / power_filter;
+ }
+ }
+}
diff --git a/libs/fsk/fsk_norm.h b/libs/fsk/fsk_norm.h
new file mode 100644
index 0000000..e8bfe17
--- /dev/null
+++ b/libs/fsk/fsk_norm.h
@@ -0,0 +1,14 @@
+#ifndef LIBS_FSK_FSK_NORM_H_
+#define LIBS_FSK_FSK_NORM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void fsk_norm(short_complex_t *buf, Uint16 bufSize, int16 hold);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_NORM_H_ */
diff --git a/libs/fsk/fsk_pack.c b/libs/fsk/fsk_pack.c
new file mode 100644
index 0000000..9dcdd00
--- /dev/null
+++ b/libs/fsk/fsk_pack.c
@@ -0,0 +1,37 @@
+#include "DSP28x_Project.h"
+#include "libs/fsk/fsk_frame.h"
+#include "libs/complex/complex.h"
+#include "libs/fsk/fsk_table.h"
+#include "libs/crc/crc32.h"
+
+#include
+
+static inline void scramble_frame(Uint16 *frame, int16 frame_length,
+ const Uint16 *scrambling_sequence)
+{
+ int16 i;
+ for (i = 0; i < frame_length; i++){
+ //XOR byte with byte from scrambling sequence
+ frame[i] ^= scrambling_sequence[i];
+ }
+}
+
+#pragma CODE_SECTION(fsk_pack,"ramfuncs");
+void fsk_pack(Uint16 *buf,fsk_frame_t *frame)
+{
+ Uint32 crc32_value;
+ buf[0] = 0xA5;
+ buf[37] = 0x5A;
+
+ buf[1] = frame->addr;
+ buf[2] = frame->type;
+
+ memcpy(&buf[3],frame->data,30);
+ scramble_frame(&buf[3],30,scrambleTable);
+ crc32_value = crc32(&buf[3],30);
+
+ buf[33] = (crc32_value >> 24) & 0xFF;
+ buf[34] = (crc32_value >> 16) & 0xFF;
+ buf[35] = (crc32_value >> 8) & 0xFF;
+ buf[36] = (crc32_value) & 0xFF;
+}
diff --git a/libs/fsk/fsk_pack.h b/libs/fsk/fsk_pack.h
new file mode 100644
index 0000000..684dbe9
--- /dev/null
+++ b/libs/fsk/fsk_pack.h
@@ -0,0 +1,14 @@
+#ifndef LIBS_FSK_FSK_PACK_H_
+#define LIBS_FSK_FSK_PACK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void fsk_pack(Uint16 *buf,fsk_frame_t *frame);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_PACK_H_ */
diff --git a/libs/fsk/fsk_table.c b/libs/fsk/fsk_table.c
new file mode 100644
index 0000000..e1c4f2b
--- /dev/null
+++ b/libs/fsk/fsk_table.c
@@ -0,0 +1,214 @@
+#include "DSP28x_Project.h"
+#include "libs/complex/complex.h"
+
+const short_complex_t sampleTable[] = { { 0, 1024 },
+ { 391, 946 },
+ { 724, 724 },
+ { 946, 391 },
+ { 1024, 0 },
+ { 946, -392 },
+ { 724, -725 },
+ { 391, -947 },
+ { 0, -1024 },
+ { -392, -947 },
+ { -725, -725 },
+ { -947, -392 },
+ { -1024, -1 },
+ { -947, 391 },
+ { -725, 724 },
+ { -392, 946 }};
+
+const Uint16 scrambleTable[] = {
+ 97,125,253,153,201,27,207,78,
+ 197,205,208,148,135,45,5,27,
+ 51,238,145,223,113,191,183,
+ 121,161,6,25,63,73,193,179
+};
+
+const int16 filterTable[] = {
+
+-0x286,-0x1f6,-0x127,-0x54,0x44,0x74,0x30,-0x6E,0x126,0x1A3,
+-0x194,-0xBE,0xE7,0x328,0x598,0x7A6,0x8B5,0x849,0x622,0x25C,
+-0x290,-0x7D8,-0xC84,-0xF9F,-0x1066,-0xE7D,-0xA00,-0x38E,0x3D5,
+0xAED,0x107E,0x138D,0x138D,0x107E,0xAED,0x3D5,-0x38E,-0xA00,
+-0xE7D,-0x1066,-0xF9F,-0xC84,-0x7D8,-0x290,0x25C,0x622,0x849,
+0x8B5,0x7A6,0x598,0x328,0xE7,-0xBE,-0x194,0x1A3,0x126,-0x6E,
+0x30,0x74,0x44,-0x54,-0x127,-0x1f6,-0x286
+ /*
+ 0x2,-0x2F,-0x65,-0x9E,-0xDC,-0x11D,-0x161,-0x1A8,-0x1F2,-0x23E,-0x28B,
+ -0x2DA,-0x32,-0x379,-0x3C9,-0x418,-0x466,-0x4B2,-0x4FB,-0x542,-0x586,
+ -0x5C6,-0x601,-0x638,-0x66A,-0x696,-0x6BD,-0x6DE,-0x6F9,-0x70D,-0x71A,
+ 0x78DF,0x78DF,-0x71A,-0x70D,-0x6F9,-0x6DE,-0x6BD,-0x696,-0x66A,-0x638,
+ -0x601,-0x5C6,-0x586,-0x542,-0x4FB,-0x4B2,-0x466,-0x418,-0x3C9,
+ -0x379,-0x32,-0x2DA,-0x28B,-0x23E,-0x1F2,-0x1A8,-0x161,-0x11D,-0xDC,
+ -0x9E,-0x65,-0x2F,0x2
+ */};
+
+const int16 atan2Table[] = { 5, 11, 16, 22, 27, 33, 39, 44, 50, 55, 61, 67, 72,
+ 78, 83, 89, 95, 100, 106, 111, 117, 123, 128, 134,
+ 139, 145, 151, 156, 162, 167, 173, 179, 184, 190,
+ 195, 201, 207, 212, 218, 223, 229, 234, 240, 246,
+ 251, 257, 262, 268, 274, 279, 285, 290, 296, 301,
+ 307, 313, 318, 324, 329, 335, 341, 346, 352, 357,
+ 363, 368, 374, 380, 385, 391, 396, 402, 407, 413,
+ 419, 424, 430, 435, 441, 446, 452, 458, 463, 469,
+ 474, 480, 485, 491, 496, 502, 508, 513, 519, 524,
+ 530, 535, 541, 546, 552, 557, 563, 569, 574, 580,
+ 585, 591, 596, 602, 607, 613, 618, 624, 629, 635,
+ 641, 646, 652, 657, 663, 668, 674, 679, 685, 690,
+ 696, 701, 707, 712, 718, 723, 729, 734, 740, 745,
+ 751, 756, 762, 767, 773, 778, 784, 789, 795, 800,
+ 806, 811, 817, 822, 828, 833, 839, 844, 850, 855,
+ 861, 866, 872, 877, 882, 888, 893, 899, 904, 910,
+ 915, 921, 926, 932, 937, 943, 948, 953, 959, 964,
+ 970, 975, 981, 986, 991, 997, 1002, 1008, 1013,
+ 1019, 1024, 1029, 1035, 1040, 1046, 1051, 1057,
+ 1062, 1067, 1073, 1078, 1084, 1089, 1094, 1100,
+ 1105, 1111, 1116, 1121, 1127, 1132, 1137, 1143,
+ 1148, 1154, 1159, 1164, 1170, 1175, 1180, 1186,
+ 1191, 1196, 1202, 1207, 1213, 1218, 1223, 1229,
+ 1234, 1239, 1245, 1250, 1255, 1261, 1266, 1271,
+ 1277, 1282, 1287, 1293, 1298, 1303, 1309, 1314,
+ 1319, 1324, 1330, 1335, 1340, 1346, 1351, 1356,
+ 1361, 1367, 1372, 1377, 1383, 1388, 1393, 1398,
+ 1404, 1409, 1414, 1420, 1425, 1430, 1435, 1441,
+ 1446, 1451, 1456, 1462, 1467, 1472, 1477, 1482,
+ 1488, 1493, 1498, 1503, 1509, 1514, 1519, 1524,
+ 1529, 1535, 1540, 1545, 1550, 1555, 1561, 1566,
+ 1571, 1576, 1581, 1587, 1592, 1597, 1602, 1607,
+ 1612, 1618, 1623, 1628, 1633, 1638, 1643, 1649,
+ 1654, 1659, 1664, 1669, 1674, 1679, 1684, 1690,
+ 1695, 1700, 1705, 1710, 1715, 1720, 1725, 1731,
+ 1736, 1741, 1746, 1751, 1756, 1761, 1766, 1771,
+ 1776, 1781, 1786, 1792, 1797, 1802, 1807, 1812,
+ 1817, 1822, 1827, 1832, 1837, 1842, 1847, 1852,
+ 1857, 1862, 1867, 1872, 1877, 1882, 1887, 1892,
+ 1897, 1902, 1907, 1912, 1917, 1922, 1927, 1932,
+ 1937, 1942, 1947, 1952, 1957, 1962, 1967, 1972,
+ 1977, 1982, 1987, 1992, 1997, 2002, 2007, 2012,
+ 2017, 2022, 2026, 2031, 2036, 2041, 2046, 2051,
+ 2056, 2061, 2066, 2071, 2076, 2080, 2085, 2090,
+ 2095, 2100, 2105, 2110, 2115, 2120, 2124, 2129,
+ 2134, 2139, 2144, 2149, 2153, 2158, 2163, 2168,
+ 2173, 2178, 2182, 2187, 2192, 2197, 2202, 2207,
+ 2211, 2216, 2221, 2226, 2231, 2235, 2240, 2245,
+ 2250, 2254, 2259, 2264, 2269, 2274, 2278, 2283,
+ 2288, 2293, 2297, 2302, 2307, 2312, 2316, 2321,
+ 2326, 2330, 2335, 2340, 2345, 2349, 2354, 2359,
+ 2363, 2368, 2373, 2378, 2382, 2387, 2392, 2396,
+ 2401, 2406, 2410, 2415, 2420, 2424, 2429, 2434,
+ 2438, 2443, 2447, 2452, 2457, 2461, 2466, 2471,
+ 2475, 2480, 2484, 2489, 2494, 2498, 2503, 2507,
+ 2512, 2517, 2521, 2526, 2530, 2535, 2540, 2544,
+ 2549, 2553, 2558, 2562, 2567, 2571, 2576, 2580,
+ 2585, 2590, 2594, 2599, 2603, 2608, 2612, 2617,
+ 2621, 2626, 2630, 2635, 2639, 2644, 2648, 2653,
+ 2657, 2662, 2666, 2671, 2675, 2679, 2684, 2688,
+ 2693, 2697, 2702, 2706, 2711, 2715, 2719, 2724,
+ 2728, 2733, 2737, 2742, 2746, 2750, 2755, 2759,
+ 2764, 2768, 2772, 2777, 2781, 2786, 2790, 2794,
+ 2799, 2803, 2807, 2812, 2816, 2820, 2825, 2829,
+ 2833, 2838, 2842, 2846, 2851, 2855, 2859, 2864,
+ 2868, 2872, 2877, 2881, 2885, 2890, 2894, 2898,
+ 2902, 2907, 2911, 2915, 2919, 2924, 2928, 2932,
+ 2937, 2941, 2945, 2949, 2953, 2958, 2962, 2966,
+ 2970, 2975, 2979, 2983, 2987, 2991, 2996, 3000,
+ 3004, 3008, 3012, 3017, 3021, 3025, 3029, 3033,
+ 3038, 3042, 3046, 3050, 3054, 3058, 3062, 3067,
+ 3071, 3075, 3079, 3083, 3087, 3091, 3096, 3100,
+ 3104, 3108, 3112, 3116, 3120, 3124, 3128, 3132,
+ 3137, 3141, 3145, 3149, 3153, 3157, 3161, 3165,
+ 3169, 3173, 3177, 3181, 3185, 3189, 3193, 3197,
+ 3201, 3205, 3209, 3213, 3217, 3221, 3225, 3229,
+ 3233, 3237, 3241, 3245, 3249, 3253, 3257, 3261,
+ 3265, 3269, 3273, 3277, 3281, 3285, 3289, 3293,
+ 3297, 3301, 3305, 3309, 3313, 3317, 3321, 3324,
+ 3328, 3332, 3336, 3340, 3344, 3348, 3352, 3356,
+ 3360, 3363, 3367, 3371, 3375, 3379, 3383, 3387,
+ 3391, 3394, 3398, 3402, 3406, 3410, 3414, 3417,
+ 3421, 3425, 3429, 3433, 3437, 3440, 3444, 3448,
+ 3452, 3456, 3459, 3463, 3467, 3471, 3475, 3478,
+ 3482, 3486, 3490, 3493, 3497, 3501, 3505, 3508,
+ 3512, 3516, 3520, 3523, 3527, 3531, 3535, 3538,
+ 3542, 3546, 3549, 3553, 3557, 3561, 3564, 3568,
+ 3572, 3575, 3579, 3583, 3586, 3590, 3594, 3597,
+ 3601, 3605, 3608, 3612, 3616, 3619, 3623, 3627,
+ 3630, 3634, 3638, 3641, 3645, 3648, 3652, 3656,
+ 3659, 3663, 3666, 3670, 3674, 3677, 3681, 3684,
+ 3688, 3692, 3695, 3699, 3702, 3706, 3709, 3713,
+ 3717, 3720, 3724, 3727, 3731, 3734, 3738, 3741,
+ 3745, 3748, 3752, 3756, 3759, 3763, 3766, 3770,
+ 3773, 3777, 3780, 3784, 3787, 3791, 3794, 3798,
+ 3801, 3804, 3808, 3811, 3815, 3818, 3822, 3825,
+ 3829, 3832, 3836, 3839, 3842, 3846, 3849, 3853,
+ 3856, 3860, 3863, 3866, 3870, 3873, 3877, 3880,
+ 3883, 3887, 3890, 3894, 3897, 3900, 3904, 3907,
+ 3911, 3914, 3917, 3921, 3924, 3927, 3931, 3934,
+ 3937, 3941, 3944, 3947, 3951, 3954, 3957, 3961,
+ 3964, 3967, 3971, 3974, 3977, 3981, 3984, 3987,
+ 3991, 3994, 3997, 4000, 4004, 4007, 4010, 4014,
+ 4017, 4020, 4023, 4027, 4030, 4033, 4036, 4040,
+ 4043, 4046, 4049, 4053, 4056, 4059, 4062, 4065,
+ 4069, 4072, 4075, 4078, 4082, 4085, 4088, 4091,
+ 4094, 4098, 4101, 4104, 4107, 4110, 4113, 4117,
+ 4120, 4123, 4126, 4129, 4132, 4136, 4139, 4142,
+ 4145, 4148, 4151, 4155, 4158, 4161, 4164, 4167,
+ 4170, 4173, 4176, 4180, 4183, 4186, 4189, 4192,
+ 4195, 4198, 4201, 4204, 4207, 4210, 4214, 4217,
+ 4220, 4223, 4226, 4229, 4232, 4235, 4238, 4241,
+ 4244, 4247, 4250, 4253, 4256, 4259, 4262, 4265,
+ 4269, 4272, 4275, 4278, 4281, 4284, 4287, 4290,
+ 4293, 4296, 4299, 4302, 4305, 4308, 4311, 4314,
+ 4317, 4320, 4323, 4325, 4328, 4331, 4334, 4337,
+ 4340, 4343, 4346, 4349, 4352, 4355, 4358, 4361,
+ 4364, 4367, 4370, 4373, 4376, 4378, 4381, 4384,
+ 4387, 4390, 4393, 4396, 4399, 4402, 4405, 4408,
+ 4410, 4413, 4416, 4419, 4422, 4425, 4428, 4431,
+ 4433, 4436, 4439, 4442, 4445, 4448, 4451, 4453,
+ 4456, 4459, 4462, 4465, 4468, 4470, 4473, 4476,
+ 4479, 4482, 4485, 4487, 4490, 4493, 4496, 4499,
+ 4501 };
+
+#pragma CODE_SECTION(atan2_table_16,"ramfuncs");
+int16 atan2_table_16(int16 x, int16 y)
+{
+ int16 result;
+ Uint32 z;
+ int16 abs_x = (x < 0) ? (0 - x) : (x);
+ int16 abs_y = (y < 0) ? (0 - y) : (y);
+
+ if ((x == 0) && (y == 0))
+ {
+ return 0;
+ }
+
+ if (abs_y < abs_x)
+ {
+ z = (abs_y) * 65536u / (abs_x);
+ z = z >> 6;
+ result = atan2Table[z];
+ }
+ else
+ {
+ z = (abs_x) * 65536u / (abs_y);
+ z = z >> 6;
+ result = 9000 - atan2Table[z];
+ }
+
+ if ((x >= 0) && (y < 0))
+ {
+ return -result;
+ }
+ else if ((x < 0) && (y >= 0))
+ {
+ return 18000 - result;
+ }
+ else if ((x < 0) && (y < 0))
+ {
+ return result - 18000;
+ }
+ else
+ {
+ return result;
+ }
+}
diff --git a/libs/fsk/fsk_table.h b/libs/fsk/fsk_table.h
new file mode 100644
index 0000000..fed5b9d
--- /dev/null
+++ b/libs/fsk/fsk_table.h
@@ -0,0 +1,19 @@
+#ifndef LIBS_FSK_FSK_TABLE_H_
+#define LIBS_FSK_FSK_TABLE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const short_complex_t sampleTable[];
+extern const int32 atan2buf[];
+extern const Uint16 scrambleTable[];
+extern const int16 filterTable[];
+
+int16 atan2_table_16(int16 x,int16 y);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_TABLE_H_ */
diff --git a/libs/fsk/fsk_unpack.c b/libs/fsk/fsk_unpack.c
new file mode 100644
index 0000000..8d80be5
--- /dev/null
+++ b/libs/fsk/fsk_unpack.c
@@ -0,0 +1,46 @@
+#include "DSP28x_Project.h"
+#include "libs/fsk/fsk_frame.h"
+#include "libs/complex/complex.h"
+#include "libs/fsk/fsk_table.h"
+#include "libs/crc/crc32.h"
+
+#include
+
+static inline void unscramble_frame(Uint16 *frame, int16 frame_length,
+ const Uint16 *scrambling_sequence)
+{
+ int16 i;
+ for (i = 0; i < frame_length; i++){
+ //XOR byte with byte from scrambling sequence
+ frame[i] ^= scrambling_sequence[i];
+ }
+}
+
+#pragma CODE_SECTION(fsk_unpack,"ramfuncs");
+int16 fsk_unpack(Uint16 *buf,fsk_frame_t *frame)
+{
+ Uint32 crc32_value,crc32_received;
+ if((buf[0] == 0xA5) && (buf[37] == 0x5A))
+ {
+ crc32_received = (Uint32)buf[33] << 24;
+ crc32_received |= (Uint32)buf[34] << 16;
+ crc32_received |= (Uint32)buf[35] << 8;
+ crc32_received |= (Uint32)buf[36];
+
+ crc32_value = crc32(&buf[3],30);
+ if(crc32_value != crc32_received)
+ {
+ return 0;
+ }
+
+ frame->addr = buf[1];
+ frame->type = buf[2];
+ unscramble_frame(&buf[3],30,scrambleTable);
+ memcpy(frame->data,&buf[3],30);
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
diff --git a/libs/fsk/fsk_unpack.h b/libs/fsk/fsk_unpack.h
new file mode 100644
index 0000000..8af1106
--- /dev/null
+++ b/libs/fsk/fsk_unpack.h
@@ -0,0 +1,14 @@
+#ifndef LIBS_FSK_FSK_UNPACK_H_
+#define LIBS_FSK_FSK_UNPACK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int16 fsk_unpack(Uint16 *buf,fsk_frame_t *frame);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_FSK_FSK_UNPACK_H_ */
diff --git a/libs/link/link_rx.c b/libs/link/link_rx.c
new file mode 100644
index 0000000..ab2f2ba
--- /dev/null
+++ b/libs/link/link_rx.c
@@ -0,0 +1,44 @@
+#include "DSP28x_Project.h"
+#include "libs/safepipe/safepipe.h"
+#include "libs/fsk/fsk_frame.h"
+
+#include
+
+fsk_frame_t link_rx_buffer[4];
+
+safepipe_t link_rx_pipe;
+
+const void *link_rx_buf_p[4] = {&link_rx_buffer[0],&link_rx_buffer[1],&link_rx_buffer[2],&link_rx_buffer[3]};
+
+void link_rx_layer_init(void)
+{
+ memset(link_rx_buffer,0,sizeof(link_rx_buffer));
+ safepipe_init(&link_rx_pipe,4,(void **)link_rx_buf_p);
+}
+
+#pragma CODE_SECTION(link_rx_layer_recv_cb,"ramfuncs");
+int16 link_rx_layer_recv_cb(fsk_frame_t * recv_frame)
+{
+ fsk_frame_t *new_frame;
+ if(safepipe_writeable(&link_rx_pipe))
+ {
+ new_frame = safepipe_get_current_write_buf(&link_rx_pipe);
+
+ memcpy(new_frame,recv_frame,sizeof(fsk_frame_t));
+
+ safepipe_write_update(&link_rx_pipe);
+ return 1;
+ }
+ return 0;
+}
+
+#pragma CODE_SECTION(link_rx_loop,"ramfuncs");
+void link_rx_loop(void)
+{
+ fsk_frame_t *new_frame;
+ if(safepipe_readable(&link_rx_pipe))
+ {
+ safepipe_read_update(&link_rx_pipe);
+ new_frame = safepipe_get_current_read_buf(&link_rx_pipe);
+ }
+}
diff --git a/libs/link/link_rx.h b/libs/link/link_rx.h
new file mode 100644
index 0000000..faca769
--- /dev/null
+++ b/libs/link/link_rx.h
@@ -0,0 +1,16 @@
+#ifndef LIBS_LINK_LINK_RX_H_
+#define LIBS_LINK_LINK_RX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void link_rx_layer_init(void);
+int16 link_rx_layer_recv_cb(fsk_frame_t * recv_frame);
+void link_rx_loop(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_LINK_LINK_RX_H_ */
diff --git a/libs/link/link_tx.c b/libs/link/link_tx.c
new file mode 100644
index 0000000..06e879e
--- /dev/null
+++ b/libs/link/link_tx.c
@@ -0,0 +1,74 @@
+#include "DSP28x_Project.h"
+#include "libs/safepipe/safepipe.h"
+#include "libs/fsk/fsk_frame.h"
+
+#include
+#include
+
+fsk_frame_t link_tx_buffer[4];
+
+safepipe_t link_tx_pipe;
+
+const void *link_tx_buf_p[4] = {&link_tx_buffer[0],&link_tx_buffer[1],&link_tx_buffer[2],&link_tx_buffer[3]};
+
+void link_tx_layer_init(void)
+{
+ memset(link_tx_buffer,0,sizeof(link_tx_buffer));
+ safepipe_init(&link_tx_pipe,4,(void **)link_tx_buf_p);
+}
+
+#pragma CODE_SECTION(link_tx_layer_send_cb,"ramfuncs");
+int16 link_tx_layer_send_cb(fsk_frame_t * send_frame)
+{
+ fsk_frame_t *new_frame;
+ if(safepipe_readable(&link_tx_pipe))
+ {
+ safepipe_read_update(&link_tx_pipe);
+ new_frame = safepipe_get_current_read_buf(&link_tx_pipe);
+ memcpy(send_frame,new_frame,sizeof(fsk_frame_t));
+ return 1;
+ }
+ return 0;
+}
+
+Uint16 test_send = 0;
+Uint16 test_count = 0;
+
+#pragma CODE_SECTION(link_tx_loop,"ramfuncs");
+void link_tx_loop(void)
+{
+ fsk_frame_t *new_frame;
+ int i;
+
+ if(test_send == 1)
+ {
+ test_count++;
+ if(test_count < 10)
+ {
+ return;
+ }
+ else
+ {
+ test_count = 0;
+ }
+ }
+ else
+ {
+ return;
+ }
+
+ if(safepipe_writeable(&link_tx_pipe))
+ {
+ new_frame = safepipe_get_current_write_buf(&link_tx_pipe);
+
+ //send here
+ new_frame->addr = 0x33;
+ new_frame->type = 0x44;
+ for(i=0;i<30;i++)
+ {
+ new_frame->data[i] = (rand() & 0xFF);
+ }
+
+ safepipe_write_update(&link_tx_pipe);
+ }
+}
diff --git a/libs/link/link_tx.h b/libs/link/link_tx.h
new file mode 100644
index 0000000..f5923b7
--- /dev/null
+++ b/libs/link/link_tx.h
@@ -0,0 +1,16 @@
+#ifndef LIBS_LINK_LINK_TX_H_
+#define LIBS_LINK_LINK_TX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void link_tx_layer_init(void);
+int16 link_tx_layer_send_cb(fsk_frame_t * send_frame);
+void link_tx_loop(void);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_LINK_LINK_TX_H_ */
diff --git a/libs/safepipe/safepipe.c b/libs/safepipe/safepipe.c
new file mode 100644
index 0000000..424c94c
--- /dev/null
+++ b/libs/safepipe/safepipe.c
@@ -0,0 +1,77 @@
+#include "DSP28x_Project.h"
+#include "libs/safepipe/safepipe.h"
+
+/*
+ Although we call this safepipe, it is not safe at all!!!
+ Callers must obey the rules, otherwise bad things will happen!!!
+ For readers, safepipe_readable----->safepipe_read_update----->safepipe_get_current_read_buf
+ For writers, safepipe_writeable----->safepipe_get_current_write_buf----->safepipe_write_update
+ For writers(int), safepipe_writeable----->safepipe_write_update----->safepipe_get_current_write_buf
+*/
+
+void safepipe_init(safepipe_t *pipe_p,int size,void **buf_p)
+{
+ //check the size, at least 4 as one for write guard, one for read guard, two for use
+ if(size < 4)
+ {
+ return;
+ }
+ pipe_p->size = size;
+ pipe_p->read_count = 0;
+ pipe_p->write_count = 1;
+ pipe_p->buf_p = buf_p;
+}
+
+Uint16 safepipe_writeable(safepipe_t *pipe_p)
+{
+ Uint16 new_write_count;
+ new_write_count = (pipe_p->write_count + 1) % pipe_p->size;
+
+ if(new_write_count != pipe_p->read_count)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+void safepipe_write_update(safepipe_t *pipe_p)
+{
+ Uint16 new_write_count;
+ new_write_count = (pipe_p->write_count + 1) % pipe_p->size;
+ pipe_p->write_count = new_write_count;
+}
+
+void *safepipe_get_current_write_buf(safepipe_t *pipe_p)
+{
+ return pipe_p->buf_p[pipe_p->write_count];
+}
+
+Uint16 safepipe_readable(safepipe_t *pipe_p)
+{
+ Uint16 new_read_count;
+ new_read_count = (pipe_p->read_count + 1) % pipe_p->size;
+
+ if(new_read_count != pipe_p->write_count)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+void safepipe_read_update(safepipe_t *pipe_p)
+{
+ Uint16 new_read_count;
+ new_read_count = (pipe_p->read_count + 1) % pipe_p->size;
+ pipe_p->read_count = new_read_count;
+}
+
+void *safepipe_get_current_read_buf(safepipe_t *pipe_p)
+{
+ return pipe_p->buf_p[pipe_p->read_count];
+}
diff --git a/libs/safepipe/safepipe.h b/libs/safepipe/safepipe.h
new file mode 100644
index 0000000..2ad36ae
--- /dev/null
+++ b/libs/safepipe/safepipe.h
@@ -0,0 +1,38 @@
+#ifndef LIBS_SAFEPIPE_SAFEPIPE_H_
+#define LIBS_SAFEPIPE_SAFEPIPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+ Uint16 read_count;
+ Uint16 write_count;
+ Uint16 size;
+ void **buf_p;
+}safepipe_t;
+
+void safepipe_init(safepipe_t *pipe_p,int size,void **buf_p);
+
+/*
+ Although we call this safepipe, it is not safe at all!!!
+ Callers must obey the rules, otherwise bad things will happen!!!
+ For readers, safepipe_readable----->safepipe_read_update----->safepipe_get_current_read_buf
+ For writers, safepipe_writeable----->safepipe_get_current_write_buf----->safepipe_write_update
+ For writers(int), safepipe_writeable----->safepipe_write_update----->safepipe_get_current_write_buf
+*/
+
+Uint16 safepipe_writeable(safepipe_t *pipe_p);
+void safepipe_write_update(safepipe_t *pipe_p);
+void *safepipe_get_current_write_buf(safepipe_t *pipe_p);
+
+Uint16 safepipe_readable(safepipe_t *pipe_p);
+void safepipe_read_update(safepipe_t *pipe_p);
+void *safepipe_get_current_read_buf(safepipe_t *pipe_p);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* LIBS_SAFEPIPE_SAFEPIPE_H_ */