Merge pull request #88 from chetan-rathore/main

BSA 1.0.3 release changes

README.md

@@ -16,7 +16,7 @@ A few tests are executed by running the BSA ACS Linux application which in turn
 
 
 ## Release details
- - Code quality: v1.0.2
+ - Code quality: v1.0.3
  - The tests are written for version 1.0 of the BSA specification.
  - The compliance suite is not a substitute for design verification.
  - To review the BSA ACS logs, Arm licensees can contact Arm directly through their partner managers.
@@ -243,4 +243,4 @@ BSA ACS is distributed under Apache v2.0 License.
 
 --------------
 
-*Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.*

linux_app/bsa-acs-app/include/bsa_app.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,7 +22,7 @@
 
 #define BSA_APP_VERSION_MAJOR     1
 #define BSA_APP_VERSION_MINOR     0
-#define BSA_APP_VERSION_SUBMINOR  2
+#define BSA_APP_VERSION_SUBMINOR  3
 
 #define G_SW_OS            0
 #define G_SW_HYP           1

platform/pal_uefi_acpi/src/pal_pe.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -157,7 +157,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
       Ptr->pe_num     = PeTable->header.num_of_pe;
       Ptr->pmu_gsiv   = Entry->PerformanceInterruptGsiv;
       Ptr->gmain_gsiv = Entry->VGICMaintenanceInterrupt;
-      bsa_print(ACS_PRINT_DEBUG, L"  MPIDR %x PE num %x \n", Ptr->mpidr, Ptr->pe_num);
+      bsa_print(ACS_PRINT_DEBUG, L"  MPIDR %llx PE num %x \n", Ptr->mpidr, Ptr->pe_num);
       pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE);
       Ptr++;
       PeTable->header.num_of_pe++;

platform/pal_uefi_dt/src/pal_dt_debug.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2021 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2021, 2023 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -42,7 +42,7 @@ dt_dump_pe_table(PE_INFO_TABLE *PeTable)
 
   while (Index < PeTable->header.num_of_pe) {
     bsa_print(ACS_PRINT_DEBUG, L" PE NUM      :%x\n", PeTable->pe_info[Index].pe_num);
-    bsa_print(ACS_PRINT_DEBUG, L" MPIDR       :%x\n", PeTable->pe_info[Index].mpidr);
+    bsa_print(ACS_PRINT_DEBUG, L" MPIDR       :%llx\n", PeTable->pe_info[Index].mpidr);
 //    bsa_print(ACS_PRINT_DEBUG, L"    ATTR     :%x\n", PeTable->pe_info[Index].attr);
     bsa_print(ACS_PRINT_DEBUG, L" PMU GSIV    :%x\n", PeTable->pe_info[Index].pmu_gsiv);
     Index++;

test_pool/memory_map/operating_system/test_os_m002.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2021 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2021, 2023 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -28,7 +28,7 @@
 
 #define LOOP_VAR   3          /* Number of Addresses to check */
 
-static void *branch_to_test;
+static uint64_t branch_to_test;
 uint32_t loop_var = LOOP_VAR;
 uint32_t instance = 0;
 uint32_t timeout;
@@ -42,7 +42,7 @@ void
 esr(uint64_t interrupt_type, void *context)
 {
   /* Update the ELR to point to next instrcution */
-  val_pe_update_elr(context, (uint64_t)branch_to_test);
+  val_pe_update_elr(context, branch_to_test);
 
   val_print(ACS_PRINT_DEBUG, "\n       Received DAbort Exception ", 0);
 }
@@ -60,7 +60,7 @@ payload()
   val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr);
   val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
 
-  branch_to_test = &&exception_taken_d;
+  branch_to_test = (uint64_t)&&exception_taken_d;
   while (loop_var) {
       timeout = TIMEOUT_SMALL;
       /* Get the address of device memory region */
@@ -86,7 +86,7 @@ payload()
 normal_mem_test:
   loop_var = LOOP_VAR;
   instance = 0;
-  branch_to_test = &&exception_taken_n;
+  branch_to_test = (uint64_t)&&exception_taken_n;
   while (loop_var) {
       timeout = TIMEOUT_SMALL;
       /* Get the address of normal memory region */

uefi_app/BsaAcs.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,7 +22,7 @@
 
   #define BSA_ACS_MAJOR_VER      1
   #define BSA_ACS_MINOR_VER      0
-  #define BSA_ACS_SUBMINOR_VER   2
+  #define BSA_ACS_SUBMINOR_VER   3
 
   #define G_PRINT_LEVEL ACS_PRINT_TEST
 

val/include/bsa_acs_exerciser.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2020,2021 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2021, 2023 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -97,7 +97,7 @@ typedef enum {
     INVALID_CFG = 0x19
 } EXERCISER_ERROR_CODE;
 
-void val_exerciser_create_info_table(void);
+uint32_t val_exerciser_create_info_table(void);
 uint32_t val_exerciser_init(uint32_t instance);
 uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance);
 uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance);

val/src/acs_exerciser.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,44 +30,89 @@ extern uint32_t pcie_bdf_table_list_flag;
   @param   exerciser_info_table - Table pointer to be filled by this API
   @return  exerciser_info_table - Contains info to communicate with stimulus generation hardware
 **/
-void val_exerciser_create_info_table(void)
+uint32_t val_exerciser_create_info_table(void)
 {
-  uint32_t Bdf;
+  uint32_t num_ecam;
+  uint32_t seg_num;
+  uint32_t start_bus;
+  uint32_t end_bus;
+  uint32_t bus_index;
+  uint32_t dev_index;
+  uint32_t func_index;
+  uint32_t ecam_index;
+  uint32_t bdf;
   uint32_t reg_value;
-  uint32_t num_bdf;
-  pcie_device_bdf_table *bdf_table;
+  uint32_t cid_offset;
+  uint32_t p_cap;
 
-  bdf_table = val_pcie_bdf_table_ptr();
-  /* if no bdf table ptr return error */
-  if (bdf_table->num_entries == 0)
+  num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
+  if (num_ecam == 0)
   {
-      val_print(ACS_PRINT_DEBUG, "\n       No BDFs discovered            ", 0);
-      return;
+      val_print(ACS_PRINT_ERR,
+        "       No ECAMs discovered             \n ", 0);
+      return 1;
   }
 
-  num_bdf = bdf_table->num_entries;
-  while (num_bdf-- != 0)
+  for (ecam_index = 0; ecam_index < num_ecam; ecam_index++)
   {
+      /* Derive ecam specific information */
+      seg_num = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index);
+      start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, ecam_index);
+      end_bus = val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index);
 
-      Bdf = bdf_table->device[num_bdf].bdf;
-      /* Probe pcie device Function with this bdf */
-      if (val_pcie_read_cfg(Bdf, TYPE01_VIDR, &reg_value) == PCIE_NO_MAPPING)
+      /* Iterate over all buses, devices and functions in this ecam */
+      for (bus_index = start_bus; bus_index <= end_bus; bus_index++)
       {
-          /* Return if there is a bdf mapping issue */
-          val_print(ACS_PRINT_ERR, "\n       BDF 0x%x mapping issue", Bdf);
-          return;
-      }
-
-      /* Store the Function's BDF if there was a valid response */
-      if (pal_is_bdf_exerciser(Bdf))
-      {
-          g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser].bdf = Bdf;
-          g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser++].initialized = 0;
-          val_print(ACS_PRINT_INFO, "\n       exerciser Bdf %x", Bdf);
+          for (dev_index = 0; dev_index < PCIE_MAX_DEV; dev_index++)
+          {
+              for (func_index = 0; func_index < PCIE_MAX_FUNC; func_index++)
+              {
+                  /* Form bdf using seg, bus, device, function numbers */
+                  bdf = PCIE_CREATE_BDF(seg_num, bus_index, dev_index, func_index);
+
+                  /* Probe pcie device Function with this bdf */
+                  if (val_pcie_read_cfg(bdf, TYPE01_VIDR, &reg_value) == PCIE_NO_MAPPING)
+                  {
+                      /* Return if there is a bdf mapping issue */
+                      val_print(ACS_PRINT_ERR, "\n       BDF 0x%x mapping issue", bdf);
+                      return 1;
+                  }
+
+                  /* Store the Function's BDF if there was a valid response */
+                  if (reg_value != PCIE_UNKNOWN_RESPONSE)
+                  {
+                      /* Skip if the device is a host bridge */
+                      if (val_pcie_is_host_bridge(bdf))
+                          continue;
+
+                      /* Skip if the device is a PCI legacy device */
+                      p_cap = val_pcie_find_capability(
+                        bdf,
+                        PCIE_CAP,
+                        CID_PCIECS,
+                        &cid_offset);
+
+                      if (p_cap != PCIE_SUCCESS)
+                          continue;
+
+                      /* Store the Function's BDF if there was a valid response */
+                      if (pal_is_bdf_exerciser(bdf))
+                      {
+                          g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser].bdf
+                                                                                          = bdf;
+                          g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser++]
+                                                                               .initialized = 0;
+                          val_print(ACS_PRINT_INFO, "\n       exerciser Bdf %x", bdf);
+                      }
+                  }
+              }
+          }
       }
   }
+
   val_print(ACS_PRINT_INFO, "\n       exerciser cards in the system %x \n",
             g_exercier_info_table.num_exerciser);
+  return 0;
 }
 
 uint32_t val_get_exerciser_err_info(EXERCISER_ERROR_CODE type)
@@ -305,18 +350,11 @@ val_exerciser_execute_tests(uint32_t *g_sw_view)
   }
 
   /* Create the list of valid Pcie Device Functions */
-  if (val_pcie_create_device_bdf_table()) {
+  if (val_exerciser_create_info_table()) {
       val_print(ACS_PRINT_WARN, "\n     Create BDF Table Failed, Skipping Exerciser tests...\n", 0);
       return ACS_STATUS_SKIP;
   }
 
-   if (pcie_bdf_table_list_flag == 1) {
-    val_print(ACS_PRINT_WARN, "\n     *** Created device list with valid bdf doesn't match \
-                with the platform pcie device hierarchy, Skipping exerciser tests *** \n", 0);
-    return ACS_STATUS_SKIP;
-  }
-
-  val_exerciser_create_info_table();
   num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
   if (num_instances == 0) {

val/src/acs_pcie.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -75,8 +75,7 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data)
   }
 
   if (ecam_base == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Read PCIe_CFG: ECAM Base is zero   "
-                                                        "   ", 0);
+      val_print(ACS_PRINT_ERR, "\n       Read PCIe_CFG: ECAM Base is zero %x", bdf);
       return PCIE_NO_MAPPING;
   }
 
@@ -152,7 +151,7 @@ val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data)
   }
 
   if (ecam_base == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Read PCIe_CFG: ECAM Base is zero ", 0);
+      val_print(ACS_PRINT_ERR, "\n       Write PCIe_CFG: ECAM Base is zero %x", bdf);
       return;
   }
 
@@ -223,7 +222,7 @@ uint64_t val_pcie_get_bdf_config_addr(uint32_t bdf)
   }
 
   if (ecam_base == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Read PCIe_CFG: ECAM Base is zero ", 0);
+      val_print(ACS_PRINT_ERR, "\n       BDF config Read PCIe_CFG: ECAM Base is zero %x", bdf);
       return 0;
   }
 
@@ -502,7 +501,7 @@ val_pcie_create_info_table(uint64_t *pcie_info_table)
 
   /* Create the list of valid Pcie Device Functions */
   if (val_pcie_create_device_bdf_table()) {
-      val_print(ACS_PRINT_ERR, " Create Bdf table failed.\n", 0);
+      val_print(ACS_PRINT_ERR, "   Create Bdf table failed.\n", 0);
       return;
   }
 
@@ -660,16 +659,19 @@ val_pcie_create_device_bdf_table()
       }
   }
 
-  val_print(ACS_PRINT_INFO,
-    "  Number of valid BDFs is %x\n", g_pcie_bdf_table->num_entries);
-
   /* Sanity Check : Confirm all EP (normal, integrated) have a rootport */
   if (val_pcie_populate_device_rootport())
   {
       /* Discard the bdf table */
       g_pcie_bdf_table->num_entries = 0;
+      val_print(ACS_PRINT_TEST,
+        " PCIE_INFO: Number of BDFs found      :    %x\n", g_pcie_bdf_table->num_entries);
+
       return 1;
   }
+  val_print(ACS_PRINT_TEST,
+    " PCIE_INFO: Number of BDFs found      :    %x\n", g_pcie_bdf_table->num_entries);
+
   return 0;
 }
 
@@ -2105,7 +2107,7 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf)
   }
 
   /* Return failure */
-  val_print(ACS_PRINT_ERR, "\n  PCIe Hierarchy fail: RP of bdf 0x%x not found", bdf);
+  val_print(ACS_PRINT_DEBUG, "   PCIe Hierarchy fail: RP of bdf 0x%x not found\n", bdf);
   *rp_bdf = 0;
   return 1;