Computer Architecture | Experiment to determine the optimal configuration of cache to reduce the cost
Cache Design choices effect the performance of a microprocessor. Define the cost function and optimal configuration of a microprocessor.
- Cache Levels
- Size
- Associativity
- Block Size Fine tune the cache hierarchy on X86 architecture based on the gem5 simulator
- 401.bzip2
- 429.mcf
Automation files used to simulate the performance of different configurations: perl script files
- L1 miss penalty = 6
- L2 miss penalty = 50
Optimizing CPI for both benchmarks, by experimentation with different configuration of L1, L2 caches, cache line size and cache associativity
- CACHE LINE COST
- 16 KB cache line = 16 units
- 32 KB cache line = 32 units
- 64 KB cache line = 64 units Cost doubles as cache line size doubles
- MAIN CACHE COST
- D L1 Cost = 8 units
- I L1 cost = 8 units
- L2 cost = 6 units
L2 cache is cheaper than L1 cache as it is slower
- ASSOCIATIVITY COST
- L1 associativity cost = 4 units
- L2 associativity cost = 2 units
TOTAL COST = CACAHE LINE COST + MAIN CACHE COST + ASSOCIATIVITY COST
- L1 Associativity keeping Data cache associativity constant, and L1 Instruction cache associativity doesn't affect the CPI . Thus keeping the least possible L1 Associativity is better (complexity and area of implementation) increasing data associativity, increases the CPI and cost as well.
- Increase in L2 associativity decreases the CPI and the cost as well.
- Cache-line size =64 KB, L1_D cache size = 128KB, L1_I cache size = 128KB, L2 cache size = 1024 KB with L1_D associativity = 2 and L1_I associativity = 2, L2 associativity = 1 is optimum for 401.bzip2 benchmark.
- Cache line size =64 KB, L1_D cache size = 128KB, L1_I cache size = 128KB, L2 cache size = 1024 KB with L1_D associativity = 16 and L1_I associativity = 4, L2 associativity = 1 is optimum for 429.mcf benchmark.