Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[WIP] Further memory optimization of SPHINX series models #118

Draft
wants to merge 3 commits into
base: main
Choose a base branch
from

Conversation

linziyi96
Copy link
Contributor

This PR currently introduces 3 changes to fit SPHINX-13B FP16 on 4*16GB GPUs:

  1. Support resharding the checkpoints to higher degree of tensor parallelism to support 4 GPUs (our checkpoints are released with a tensor parallel size of 2).
  2. Move the visual backbone creation to CPU. As the visual backbones have to be created with FP32 and with some unused language parameters, directly creating on GPUs, as is currently implemented, causes a memory spike and the consequent OOM on 16GB GPUs.
  3. In the multi_turn_mm_box demo, gives an option to disable SAM. This is a work-around to save a few GBs of memory on GPU 0 as they cannot be sharded easily now.

nvidia-smi with the model running on 4*V100-16GB after this PR:
image

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant