chore: disable prefetch, for testing purposes only

EdgeTX · Jul 8, 2024 · 2b9d0be · 2b9d0be
1 parent 4a9e943
commit 2b9d0be
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Showing 4 changed files with 2 additions and 7 deletions.
diff --git a/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c b/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c
@@ -299,7 +299,7 @@ static void SetSysClock(void)
     }
 
     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-    FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
+    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
 
     /* Select the main PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

diff --git a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c
@@ -427,7 +427,7 @@ static void SetSysClock(void)
     }
 
     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
+    FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
 
     /* Select the main PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

diff --git a/radio/src/targets/horus/board.cpp b/radio/src/targets/horus/board.cpp
@@ -70,10 +70,6 @@ void boardInit()
   board_set_bor_level();
 #endif
 
-#if defined(RADIO_TX16S)
-  FLASH_PrefetchBufferCmd(DISABLE);
-#endif
-
   pwrInit();
 
 #if defined(FUNCTION_SWITCHES) && !defined(DEBUG_SEGGER_RTT)

diff --git a/radio/src/targets/taranis/board.cpp b/radio/src/targets/taranis/board.cpp
@@ -79,7 +79,6 @@ void boardInit()
 #if defined(MANUFACTURER_RADIOMASTER) && defined(STM32F407xx)
   void board_set_bor_level();
   board_set_bor_level();
-  FLASH_PrefetchBufferCmd(DISABLE);
 #endif
 
   board_trainer_init();