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| Original file line number | Diff line number | Diff line change |
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| 3.1.0 | ||
| 4.0.0 |
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| / _____) _ | | | ||
| ( (____ _____ ____ _| |_ _____ ____| |__ | ||
| \____ \| ___ | (_ _) ___ |/ ___) _ \ | ||
| _____) ) ____| | | || |_| ____( (___| | | | | ||
| (______/|_____)_|_|_| \__)_____)\____)_| |_| | ||
| (C)2013 Semtech-Cycleo | ||
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| FPGA images for LoRa Gateway SX1301AP2-PCB_E336 | ||
| =============================================== | ||
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| 1. Content | ||
| ---------- | ||
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| This directory contains the FPGA images to be programmed in the Semtech's | ||
| Reference Design board (SX1301AP2-PCB_E336) flash memory. | ||
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| The different images contain the following features: | ||
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| * SX1301_FPGA_125K_NOTCH_LBT_bitmap_v27.bin: | ||
| - 125K Notch filter for TX | ||
| - Listen-Before-Talk | ||
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| * SX1301_FPGA_125K_NOTCH_SPECTRAL_SCAN_bitmap_v27.bin: | ||
| - 125K Notch filter for TX | ||
| - Background Spectral Scan | ||
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| 2. Usage | ||
| -------- | ||
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| The following parameters have to be set when using the Lattice Diamond | ||
| Programmer software: | ||
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| Device Family -> iCE40 | ||
| Device -> iCE40LP1K | ||
| Operation -> SPI Flash Programming | ||
| -> Programming file: select one of the provided bin image | ||
| -> SPI Vendor: Micron | ||
| -> SPI Device: SPI-M25P10-A | ||
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| 3. Legal notice | ||
| ---------------- | ||
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| The information presented in this project documentation does not form part of | ||
| any quotation or contract, is believed to be accurate and reliable and may be | ||
| changed without notice. No liability will be accepted by the publisher for any | ||
| consequence of its use. Publication thereof does not convey nor imply any | ||
| license under patent or other industrial or intellectual property rights. | ||
| Semtech assumes no responsibility or liability whatsoever for any failure or | ||
| unexpected operation resulting from misuse, neglect improper installation, | ||
| repair or improper handling or unusual physical or electrical stress | ||
| including, but not limited to, exposure to parameters beyond the specified | ||
| maximum ratings or operation outside the specified range. | ||
|
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| SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE | ||
| SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER | ||
| CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS | ||
| UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a | ||
| customer purchase or use Semtech products for any such unauthorized | ||
| application, the customer shall indemnify and hold Semtech and its officers, | ||
| employees, subsidiaries, affiliates, and distributors harmless against all | ||
| claims, costs damages and attorney fees which could arise. | ||
|
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| *EOF* |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,105 @@ | ||
| /* | ||
| / _____) _ | | | ||
| ( (____ _____ ____ _| |_ _____ ____| |__ | ||
| \____ \| ___ | (_ _) ___ |/ ___) _ \ | ||
| _____) ) ____| | | || |_| ____( (___| | | | | ||
| (______/|_____)_|_|_| \__)_____)\____)_| |_| | ||
| (C)2013 Semtech-Cycleo | ||
| Description: | ||
| Functions used to handle FPGA register access for LoRa concentrator. | ||
| Registers are addressed by name. | ||
| Multi-bytes registers are handled automatically. | ||
| Read-modify-write is handled automatically. | ||
| License: Revised BSD License, see LICENSE.TXT file include in the project | ||
| Maintainer: Michael Coracin | ||
| */ | ||
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| #ifndef _LORAGW_FPGA_REG_H | ||
| #define _LORAGW_FPGA_REG_H | ||
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| /* -------------------------------------------------------------------------- */ | ||
| /* --- DEPENDANCIES --------------------------------------------------------- */ | ||
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| #include <stdint.h> /* C99 types */ | ||
| #include <stdbool.h> /* bool type */ | ||
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| /* -------------------------------------------------------------------------- */ | ||
| /* --- PUBLIC CONSTANTS ----------------------------------------------------- */ | ||
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| #define LGW_REG_SUCCESS 0 | ||
| #define LGW_REG_ERROR -1 | ||
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| /* | ||
| auto generated register mapping for C code | ||
| this file contains autogenerated C struct used to access the FPGA registers | ||
| this file is autogenerated from registers description | ||
| */ | ||
| #define LGW_FPGA_SOFT_RESET 0 | ||
| #define LGW_FPGA_FPGA_FEATURE 1 | ||
| #define LGW_FPGA_VERSION 2 | ||
| #define LGW_FPGA_FPGA_STATUS 3 | ||
| #define LGW_FPGA_CTRL_FEATURE_START 4 | ||
| #define LGW_FPGA_CTRL_RADIO_RESET 5 | ||
| #define LGW_FPGA_CTRL_INPUT_SYNC_I 6 | ||
| #define LGW_FPGA_CTRL_INPUT_SYNC_Q 7 | ||
| #define LGW_FPGA_CTRL_OUTPUT_SYNC 8 | ||
| #define LGW_FPGA_CTRL_INVERT_IQ 9 | ||
| #define LGW_FPGA_HISTO_RAM_ADDR 10 | ||
| #define LGW_FPGA_HISTO_RAM_DATA 11 | ||
| #define LGW_FPGA_HISTO_TEMPO 12 | ||
| #define LGW_FPGA_HISTO_NB_READ 13 | ||
| #define LGW_FPGA_TIMESTAMP 14 | ||
| #define LGW_FPGA_LBT_TIMESTAMP_CH 15 | ||
| #define LGW_FPGA_LBT_TIMESTAMP_SELECT_CH 16 | ||
| #define LGW_FPGA_LBT_TIMESTAMP_NB_CH 17 | ||
| #define LGW_FPGA_SPI_MASTER_SPEED_DIVIDER 18 | ||
| #define LGW_FPGA_NB_READ_RSSI 19 | ||
| #define LGW_FPGA_PLL_LOCK_TIME 20 | ||
| #define LGW_FPGA_RSSI_TARGET 21 | ||
| #define LGW_FPGA_LSB_START_FREQ 22 | ||
| #define LGW_FPGA_SPI_MUX_CTRL 23 | ||
| #define LGW_FPGA_TOTALREGS 24 | ||
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| /* -------------------------------------------------------------------------- */ | ||
| /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ | ||
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| int lgw_fpga_configure(void); | ||
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| /** | ||
| @brief LoRa concentrator FPGA register write | ||
| @param register_id register number in the data structure describing registers | ||
| @param reg_value signed value to write to the register (for u32, use cast) | ||
| @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) | ||
| */ | ||
| int lgw_fpga_reg_w(uint16_t register_id, int32_t reg_value); | ||
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| /** | ||
| @brief LoRa concentrator FPGA register read | ||
| @param register_id register number in the data structure describing registers | ||
| @param reg_value pointer to a variable where to write register read value | ||
| @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) | ||
| */ | ||
| int lgw_fpga_reg_r(uint16_t register_id, int32_t *reg_value); | ||
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| /** | ||
| @brief LoRa concentrator FPGA register burst write | ||
| @param register_id register number in the data structure describing registers | ||
| @param data pointer to byte array that will be sent to the LoRa concentrator | ||
| @param size size of the transfer, in byte(s) | ||
| @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) | ||
| */ | ||
| int lgw_fpga_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size); | ||
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| /** | ||
| @brief LoRa concentrator FPGA register burst read | ||
| @param register_id register number in the data structure describing registers | ||
| @param data pointer to byte array that will be written from the LoRa concentrator | ||
| @param size size of the transfer, in byte(s) | ||
| @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) | ||
| */ | ||
| int lgw_fpga_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size); | ||
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| #endif | ||
| /* --- EOF ------------------------------------------------------------------ */ |
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