Merge pull request #1532 from IntelPython/fix-test-sycl-device-interf…

…ace-for-future-dpcpp Added work-around for breaking change in 2024.1 compiler
IntelPython · Feb 7, 2024 · 71b1640 · 71b1640
2 parents e2d9640 + fbd68b8
commit 71b1640
Showing 1 changed file with 7 additions and 6 deletions.
diff --git a/libsyclinterface/tests/test_sycl_device_interface.cpp b/libsyclinterface/tests/test_sycl_device_interface.cpp
@@ -297,9 +297,7 @@ TEST_P(TestDPCTLSyclDeviceInterface, ChkGetPreferredVectorWidthDouble)
         EXPECT_TRUE(vector_width_double != 0);
     }
     else {
-        // FIXME: DPC++ 2023 RT must have a bug, since it returns 1 for
-        // devices without aspect::fp64
-        // EXPECT_TRUE(vector_width_double == 0);
+        EXPECT_TRUE(vector_width_double == 0);
     }
 }
 
@@ -311,7 +309,9 @@ TEST_P(TestDPCTLSyclDeviceInterface, ChkGetPreferredVectorWidthHalf)
     if (DPCTLDevice_HasAspect(DRef, DPCTL_SyclAspectToDPCTLAspectType(
                                         DPCTL_StrToAspectType("fp16"))))
     {
-        EXPECT_TRUE(vector_width_half != 0);
+        // FIXME: zero value incorrectly returned for CPU in 2024.1,
+        // even though aspect::fp16 is true
+        EXPECT_TRUE(vector_width_half != 0 || DPCTLDevice_IsCPU(DRef));
     }
     else {
         EXPECT_TRUE(vector_width_half == 0);
@@ -384,13 +384,14 @@ TEST_P(TestDPCTLSyclDeviceInterface, ChkGetNativeVectorWidthHalf)
     if (DPCTLDevice_HasAspect(DRef, DPCTL_SyclAspectToDPCTLAspectType(
                                         DPCTL_StrToAspectType("fp16"))))
     {
-        EXPECT_TRUE(vector_width_half != 0);
+        // FIXME: zero value incorrectly returned for CPU in 2024.1,
+        // even though aspect::fp16 is true
+        EXPECT_TRUE(vector_width_half != 0 || DPCTLDevice_IsCPU(DRef));
     }
     else {
         EXPECT_TRUE(vector_width_half == 0);
     }
 }
-//
 
 TEST_P(TestDPCTLSyclDeviceInterface, ChkGetMaxReadImageArgs)
 {