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Re-organize CVA6 and APU (openhwgroup#725)
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* Initial repository re-organization (openhwgroup#662)

Initial attempt to split core from APU.

Signed-off-by: MikeOpenHWGroup <[email protected]>
Co-authored-by: Jean-Roch Coulon <[email protected]>

Compile `corev_apu` (openhwgroup#667)

* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu

Signed-off-by: Mike Thompson <[email protected]>

Add extended verification support (openhwgroup#685)

* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6

according to variant variable

Signed-off-by: Jean-Roch Coulon <[email protected]>

* add RVFI tracer and debug support

New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv

- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation

Co-authored-by: Florian Zaruba <[email protected]>
Signed-off-by: Jean-Roch Coulon <[email protected]>

* Move example_tb from cva6 to core-v-verif project

Signed-off-by: Jean-Roch Coulon <[email protected]>

* Makefile: remove useless rule for vsim

Signed-off-by: André Sintzoff <[email protected]>

* Makefile: add timescale definition when vsim is used

Signed-off-by: André Sintzoff <[email protected]>

* Makefile: add vcs support (fix openhwgroup#570)

Signed-off-by: André Sintzoff <[email protected]>

* rvfi_tracer.sv: fix compilation error raised by vcs

Signed-off-by: André Sintzoff <[email protected]>

* Makefile: use only 2 threads for verilator

when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration

Signed-off-by: André Sintzoff <[email protected]>

* Flist.cva6: cleanup for synthesis workflow

Thales synthesis workflow does not manage comments at end of lines

Signed-off-by: André Sintzoff <[email protected]>

* Support FPGA generation

- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths

Signed-off-by: André Sintzoff <[email protected]>

* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)

Signed-off-by: André Sintzoff <[email protected]>

* Create cva6_config_pkg to setup 32- or 64-bit configuration

According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv

Signed-off-by: Jean-Roch Coulon <[email protected]>

* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures

needed for dc_shell

Signed-off-by: Jean-Roch Coulon <[email protected]>

* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams

Signed-off-by: Jean-Roch Coulon <[email protected]>

* riscv_pkg.sv: clean-up the cva6_config_pkg import

Signed-off-by: Jean-Roch Coulon <[email protected]>

* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane

Signed-off-by: Jean-Roch Coulon <[email protected]>

Co-authored-by: Jean-Roch Coulon <[email protected]>
Co-authored-by: Florian Zaruba <[email protected]>

* Add lfsr.sv to manifest

Signed-off-by: Mike Thompson <[email protected]>

* Directory re-organzation

* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (openhwgroup#726)

into the new file organisation

Signed-off-by: André Sintzoff <[email protected]>

* move mmu_sv32 and mmu_sv39, move bootrom, update path (openhwgroup#729)

Signed-off-by: sjthales <[email protected]>

Co-authored-by: Mike Thompson <[email protected]>
Co-authored-by: Jean-Roch Coulon <[email protected]>
Co-authored-by: Florian Zaruba <[email protected]>
Co-authored-by: sébastien jacq <[email protected]>
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@ASintzoff @MikeOpenHWGroup
@JeanRochCoulon @zarubaf @sjthales
5 people authored Sep 24, 2021
1 parent f5cbaa9 commit 3ddf797
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2 changes: 1 addition & 1 deletion .gitignore
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Expand Up @@ -26,7 +26,7 @@ build/
*.o
uart
work-ver/*
fpga/work-fpga
corev_apu/fpga/work-fpga
stdout/
work-dpi/
tb/riscv-isa-sim/
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80 changes: 40 additions & 40 deletions .gitmodules
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@@ -1,57 +1,57 @@
[submodule "src/axi_mem_if"]
path = src/axi_mem_if
[submodule "corev_apu/axi_mem_if"]
path = corev_apu/axi_mem_if
url = https://github.com/pulp-platform/axi_mem_if.git
[submodule "src/axi_node"]
path = src/axi_node
[submodule "corev_apu/axi_node"]
path = corev_apu/axi_node
url = https://github.com/pulp-platform/axi_node.git
[submodule "src/fpga-support"]
path = src/fpga-support
[submodule "corev_apu/fpga-support"]
path = corev_apu/fpga-support
url = https://github.com/pulp-platform/fpga-support.git
[submodule "src/common_cells"]
path = src/common_cells
[submodule "common/submodules/common_cells"]
path = common/submodules/common_cells
url = https://github.com/pulp-platform/common_cells.git
[submodule "src/axi"]
path = src/axi
[submodule "corev_apu/axi"]
path = corev_apu/axi
url = https://github.com/pulp-platform/axi.git
[submodule "src/register_interface"]
path = src/register_interface
[submodule "corev_apu/register_interface"]
path = corev_apu/register_interface
url = https://github.com/pulp-platform/register_interface.git
[submodule "fpga/src/apb_uart"]
path = fpga/src/apb_uart
[submodule "corev_apu/fpga/src/apb_uart"]
path = corev_apu/fpga/src/apb_uart
url = https://github.com/pulp-platform/apb_uart.git
[submodule "fpga/src/apb_node"]
path = fpga/src/apb_node
[submodule "corev_apu/fpga/src/apb_node"]
path = corev_apu/fpga/src/apb_node
url = https://github.com/pulp-platform/apb_node.git
[submodule "fpga/src/axi2apb"]
path = fpga/src/axi2apb
url = https://github.com/pulp-platform/axi2apb.git
[submodule "fpga/src/axi_slice"]
path = fpga/src/axi_slice
url = https://github.com/pulp-platform/axi_slice.git
[submodule "src/tech_cells_generic"]
path = src/tech_cells_generic
[submodule "corev_apu/fpga/src/axi2apb"]
path = corev_apu/fpga/src/axi2apb
url = https://github.com/pulp-platform/axi2apb.git
[submodule "corev_apu/fpga/src/axi_slice"]
path = corev_apu/fpga/src/axi_slice
url = https://github.com/pulp-platform/axi_slice.git
[submodule "corev_apu/src/tech_cells_generic"]
path = corev_apu/src/tech_cells_generic
url = https://github.com/pulp-platform/tech_cells_generic.git
[submodule "src/fpu"]
path = src/fpu
[submodule "core/fpu"]
path = core/fpu
url = https://github.com/pulp-platform/fpnew.git
[submodule "fpga/src/ariane-ethernet"]
path = fpga/src/ariane-ethernet
[submodule "corev_apu/fpga/src/ariane-ethernet"]
path = corev_apu/fpga/src/ariane-ethernet
url = https://github.com/lowRISC/ariane-ethernet.git
[submodule "src/axi_riscv_atomics"]
path = src/axi_riscv_atomics
[submodule "corev_apu/src/axi_riscv_atomics"]
path = corev_apu/src/axi_riscv_atomics
url = https://github.com/pulp-platform/axi_riscv_atomics.git
[submodule "src/riscv-dbg"]
path = src/riscv-dbg
[submodule "corev_apu/riscv-dbg"]
path = corev_apu/riscv-dbg
url = https://github.com/pulp-platform/riscv-dbg.git
[submodule "src/rv_plic"]
path = src/rv_plic
[submodule "corev_apu/rv_plic"]
path = corev_apu/rv_plic
url = https://github.com/pulp-platform/rv_plic.git
[submodule "fpga/src/apb_timer"]
path = fpga/src/apb_timer
[submodule "corev_apu/fpga/src/apb_timer"]
path = corev_apu/fpga/src/apb_timer
url = https://github.com/pulp-platform/apb_timer.git
[submodule "tb/dromajo"]
path = tb/dromajo
[submodule "corev_apu/tb/dromajo"]
path = corev_apu/tb/dromajo
url = https://github.com/kabylkas/dromajo.git
[submodule "tb/common_verification"]
path = tb/common_verification
[submodule "corev_apu/tb/common_verification"]
path = corev_apu/tb/common_verification
url = https://github.com/pulp-platform/common_verification.git
91 changes: 91 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -12,6 +12,97 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.

- Fix non-setable MEIE bit in MIE CSR
- Bump `fpnew` to `v0.6.2`
- Restructured directories to separate CVA6 core from CVA6-APU (FPGA emulation platform for the core). See the [README](README.md#new-directory-structure) for details.

#### Moved Package files
```
include/riscv_pkg.sv ==> core/include/riscv_pkg.sv
src/riscv-dbg/src/dm_pkg.sv ==> corev_apu/riscv-dbg/src/dm_pkg.sv
include/ariane_pkg.sv ==> core/include/ariane_pkg.sv
include/std_cache_pkg.sv ==> core/include/std_cache_pkg.sv
include/wt_cache_pkg.sv ==> core/include/wt_cache_pkg.sv
src/axi/src/axi_pkg.sv ==> corev_apu/axi/src/axi_pkg.sv
src/register_interface/src/reg_intf.sv ==> corev_apu/register_interface/src/reg_intf.sv
src/register_interface/src/reg_intf_pkg.sv ==> corev_apu/register_interface/src/reg_intf_pkg.sv
include/axi_intf.sv ==> core/include/axi_intf.sv
tb/ariane_soc_pkg.sv ==> corev_apu/tb/ariane_soc_pkg.sv
tb/ariane_axi_soc_pkg.sv ==> corev_apu/tb/ariane_axi_soc_pkg.sv
include/ariane_axi_pkg.sv ==> core/include/ariane_axi_pkg.sv
src/fpu/src/fpnew_pkg.sv ==> core/fpu/src/fpnew_pkg.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
```

#### Moved standalone components
```
src/frontend/*.sv ==> core/frontend/*.sv
src/cache_subsystem/*.sv ==> core/cache_subsystem/*.sv (excluding std_no_dcache.sv)
bootrom/*.sv ==> corev_apu/bootrom/*.sv
src/clint/*.sv ==> corev_apu/clint/*.sv
fpga/src/axi2apb/src/*.sv ==> corev_apu/fpga/src/axi2apb/src/*.sv
fpga/src/apb_timer/*.sv ==> corev_apu/fpga/src/apb_timer/*.sv
fpga/src/axi_slice/src/*.sv ==> corev_apu/fpga/src/axi_slice/src/*.sv
src/axi_node/src/*.sv ==> corev_apu/axi_node/src/*.sv
src/axi_riscv_atomics/src/*.sv ==> corev_apu/src/axi_riscv_atomics/src/*.sv
src/axi_mem_if/src/*.sv ==> corev_apu/axi_mem_if/src/*.sv
src/pmp/src/*.sv ==> core/pmp/src/*.sv
src/rv_plic/rtl/rv_plic_target.sv ==> corev_apu/rv_plic/rtl/rv_plic_target.sv
src/rv_plic/rtl/rv_plic_gateway.sv ==> corev_apu/rv_plic/rtl/rv_plic_gateway.sv
src/rv_plic/rtl/plic_regmap.sv ==> corev_apu/rv_plic/rtl/plic_regmap.sv
src/rv_plic/rtl/plic_top.sv ==> corev_apu/rv_plic/rtl/plic_top.sv
src/riscv-dbg/src/dmi_cdc.sv ==> corev_apu/riscv-dbg/src/dmi_cdc.sv
src/riscv-dbg/src/dmi_jtag.sv ==> corev_apu/riscv-dbg/src/dmi_jtag.sv
src/riscv-dbg/src/dmi_jtag_tap.sv ==> corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
src/riscv-dbg/src/dm_csrs.sv ==> corev_apu/riscv-dbg/src/dm_csrs.sv
src/riscv-dbg/src/dm_mem.sv ==> corev_apu/riscv-dbg/src/dm_mem.sv
src/riscv-dbg/src/dm_sba.sv ==> corev_apu/riscv-dbg/src/dm_sba.sv
src/riscv-dbg/src/dm_top.sv ==> corev_apu/riscv-dbg/src/dm_top.sv
src/riscv-dbg/debug_rom/debug_rom.sv ==> corev_apu/riscv-dbg/debug_rom/debug_rom.sv
src/register_interface/src/apb_to_reg.sv ==> corev_apu/register_interface/src/apb_to_reg.sv
src/axi/src/axi_multicut.sv ==> corev_apu/axi/src/axi_multicut.sv
src/common_cells/src/deprecated/generic_fifo.sv ==> common/submodules/common_cells/src/deprecated/generic_fifo.sv
src/common_cells/src/deprecated/pulp_sync.sv ==> common/submodules/common_cells/src/deprecated/pulp_sync.sv
src/common_cells/src/deprecated/find_first_one.sv ==> common/submodules/common_cells/src/deprecated/find_first_one.sv
src/common_cells/src/rstgen_bypass.sv ==> common/submodules/common_cells/src/rstgen_bypass.sv
src/common_cells/src/rstgen.sv ==> common/submodules/common_cells/src/rstgen.sv
src/common_cells/src/stream_mux.sv ==> common/submodules/common_cells/src/stream_mux.sv
src/common_cells/src/stream_demux.sv ==> common/submodules/common_cells/src/stream_demux.sv
src/common_cells/src/exp_backoff.sv ==> common/submodules/common_cells/src/exp_backoff.sv
src/util/axi_master_connect.sv ==> common/local/util/axi_master_connect.sv
src/util/axi_slave_connect.sv ==> common/local/util/axi_slave_connect.sv
src/util/axi_master_connect_rev.sv ==> common/local/util/axi_master_connect_rev.sv
src/util/axi_slave_connect_rev.sv ==> common/local/util/axi_slave_connect_rev.sv
src/axi/src/axi_cut.sv ==> corev_apu/axi/src/axi_cut.sv
src/axi/src/axi_join.sv ==> corev_apu/axi/src/axi_join.sv
src/axi/src/axi_delayer.sv ==> corev_apu/axi/src/axi_delayer.sv
src/axi/src/axi_to_axi_lite.sv ==> corev_apu/axi/src/axi_to_axi_lite.sv
src/common_cells/src/unread.sv ==> common/submodules/common_cells/src/unread.sv
src/common_cells/src/sync.sv ==> common/submodules/common_cells/src/sync.sv
src/common_cells/src/cdc_2phase.sv ==> common/submodules/common_cells/src/cdc_2phase.sv
src/common_cells/src/spill_register.sv ==> common/submodules/common_cells/src/spill_register.sv
src/common_cells/src/sync_wedge.sv ==> common/submodules/common_cells/src/sync_wedge.sv
src/common_cells/src/edge_detect.sv ==> common/submodules/common_cells/src/edge_detect.sv
src/common_cells/src/stream_arbiter.sv ==> common/submodules/common_cells/src/stream_arbiter.sv
src/common_cells/src/stream_arbiter_flushable.sv ==> common/submodules/common_cells/src/stream_arbiter_flushable.sv
src/common_cells/src/deprecated/fifo_v1.sv ==> common/submodules/common_cells/src/deprecated/fifo_v1.sv
src/common_cells/src/deprecated/fifo_v2.sv ==> common/submodules/common_cells/src/deprecated/fifo_v2.sv
src/common_cells/src/fifo_v3.sv ==> common/submodules/common_cells/src/fifo_v3.sv
src/common_cells/src/rr_arb_tree.sv ==> common/submodules/common_cells/src/rr_arb_tree.sv
src/common_cells/src/deprecated/rrarbiter.sv ==> common/submodules/common_cells/src/deprecated/rrarbiter.sv
src/common_cells/src/stream_delay.sv ==> common/submodules/common_cells/src/stream_delay.sv
src/common_cells/src/lfsr_8bit.sv ==> common/submodules/common_cells/src/lfsr_8bit.sv
src/common_cells/src/lfsr_16bit.sv ==> common/submodules/common_cells/src/lfsr_16bit.sv
src/common_cells/src/delta_counter.sv ==> common/submodules/common_cells/src/delta_counter.sv
src/common_cells/src/counter.sv ==> common/submodules/common_cells/src/counter.sv
src/common_cells/src/shift_reg.sv ==> common/submodules/common_cells/src/shift_reg.sv
src/tech_cells_generic/src/pulp_clock_gating.sv ==> corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv
src/tech_cells_generic/src/cluster_clock_inverter.sv ==> corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv
src/tech_cells_generic/src/pulp_clock_mux2.sv ==> corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
tb/ariane_testharness.sv ==> corev_apu/tb/ariane_testharness.sv
tb/ariane_peripherals.sv ==> corev_apu/tb/ariane_peripherals.sv
tb/common/uart.sv ==> corev_apu/tb/common/uart.sv
tb/common/SimDTM.sv ==> corev_apu/tb/common/SimDTM.sv
tb/common/SimJTAG.sv ==> corev_apu/tb/common/SimJTAG.sv
```

### 4.2.0 - 2019-06-04

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