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riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug (openhwgroup…
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@ASintzoff
ASintzoff authored Oct 1, 2021
1 parent 5380030 commit 43677af
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion corev_apu/riscv-dbg
Submodule riscv-dbg updated 67 files
+85 −0 .travis.yml
+16 −0 Bender.yml
+59 −0 CHANGELOG.md
+4 −3 README.md
+12 −0 ci/download-pulp-gcc.sh
+40 −0 ci/get-openocd.sh
+28 −0 ci/install-verilator.sh
+5 −0 ci/make-tmp.sh
+62 −0 ci/openocd-to-junit.py
+47 −0 ci/run-openocd-compliance.sh
+33 −0 ci/veri-run-openocd-compliance.sh
+3 −3 debug_rom/Makefile
+33 −5 debug_rom/debug_rom.S
+3 −3 debug_rom/debug_rom.h
+42 −34 debug_rom/debug_rom.sv
+32 −0 debug_rom/debug_rom_one_scratch.h
+60 −0 debug_rom/debug_rom_one_scratch.sv
+24 −17 debug_rom/gen_rom.py
+453 −0 doc/debug-system.md
+679 −0 doc/debugsys_schematic.svg
+13 −0 doc/dmi_protocol.json
+4 −0 doc/dmi_protocol.svg
+591 −556 src/dm_csrs.sv
+500 −447 src/dm_mem.sv
+187 −0 src/dm_obi_top.sv
+417 −367 src/dm_pkg.sv
+161 −164 src/dm_sba.sv
+212 −216 src/dm_top.sv
+38 −37 src/dmi_cdc.sv
+250 −241 src/dmi_jtag.sv
+313 −307 src/dmi_jtag_tap.sv
+2 −0 src_files.yml
+55 −0 sva/dm_csrs_sva.sv
+50 −0 sva/dm_sba_sva.sv
+65 −0 sva/dm_top_sva.sv
+35 −0 tb/.clang-format
+26 −0 tb/.gitignore
+24 −0 tb/LICENSE.Berkeley
+202 −0 tb/LICENSE.SiFive
+325 −0 tb/Makefile
+51 −0 tb/README.md
+85 −0 tb/SimJTAG.sv
+40 −0 tb/boot_rom.sv
+31 −0 tb/dm_compliance_test.cfg
+32 −0 tb/dm_debug.cfg
+58 −0 tb/dm_tb_pkg.sv
+84 −0 tb/dp_ram.sv
+571 −0 tb/mm_ram.sv
+66 −0 tb/prog/crt0.S
+385 −0 tb/prog/link.ld
+270 −0 tb/prog/syscalls.c
+6 −0 tb/prog/test.c
+152 −0 tb/prog/vectors.S
+3 −0 tb/remote_bitbang/.gitignore
+124 −0 tb/remote_bitbang/Makefile
+34 −0 tb/remote_bitbang/rbs_test.c
+275 −0 tb/remote_bitbang/remote_bitbang.c
+52 −0 tb/remote_bitbang/remote_bitbang.h
+29 −0 tb/remote_bitbang/sim_jtag.c
+351 −0 tb/tb_test_env.sv
+137 −0 tb/tb_top.sv
+105 −0 tb/tb_top_verilator.cpp
+319 −0 tb/tb_top_verilator.sv
+81 −0 tb/unused/SimDTM.sv
+15 −0 tb/vsim_batch.tcl
+16 −0 tb/vsim_gui.tcl
+106 −0 tb/waves.tcl

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