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axi and common_cells upgrade (openhwgroup#791)
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* Change questa version reference format

* bump common_cells to v1.23

* Bump axi to v0.31.0, replace axi_node with axi_xbar

* Bump register_interface for axi compatibility

* add prot signals to axi_lite for compatibility
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@micprog
micprog authored Jan 15, 2022
1 parent 44a89b9 commit 4bdfa69
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Showing 12 changed files with 185 additions and 262 deletions.
3 changes: 0 additions & 3 deletions .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,9 +1,6 @@
[submodule "corev_apu/axi_mem_if"]
path = corev_apu/axi_mem_if
url = https://github.com/pulp-platform/axi_mem_if.git
[submodule "corev_apu/axi_node"]
path = corev_apu/axi_node
url = https://github.com/pulp-platform/axi_node.git
[submodule "corev_apu/fpga-support"]
path = corev_apu/fpga-support
url = https://github.com/pulp-platform/fpga-support.git
Expand Down
30 changes: 11 additions & 19 deletions Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ package:

export_include_dirs:
- common/submodules/common_cells/include/
- corev_apu/axi/include/

sources:
- defines:
Expand Down Expand Up @@ -120,25 +121,6 @@ sources:
- corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv
- corev_apu/fpga/src/apb_timer/apb_timer.sv
- corev_apu/fpga/src/apb_timer/timer.sv
- corev_apu/axi_node/src/axi_regs_top.sv
- corev_apu/axi_node/src/axi_BR_allocator.sv
- corev_apu/axi_node/src/axi_BW_allocator.sv
- corev_apu/axi_node/src/axi_address_decoder_BR.sv
- corev_apu/axi_node/src/axi_DW_allocator.sv
- corev_apu/axi_node/src/axi_address_decoder_BW.sv
- corev_apu/axi_node/src/axi_address_decoder_DW.sv
- corev_apu/axi_node/src/axi_node_arbiter.sv
- corev_apu/axi_node/src/axi_response_block.sv
- corev_apu/axi_node/src/axi_request_block.sv
- corev_apu/axi_node/src/axi_AR_allocator.sv
- corev_apu/axi_node/src/axi_AW_allocator.sv
- corev_apu/axi_node/src/axi_address_decoder_AR.sv
- corev_apu/axi_node/src/axi_address_decoder_AW.sv
- corev_apu/axi_node/src/apb_regs_top.sv
- corev_apu/axi_node/src/axi_node_intf_wrap.sv
- corev_apu/axi_node/src/axi_node.sv
- corev_apu/axi_node/src/axi_node_wrap_with_slices.sv
- corev_apu/axi_node/src/axi_multiplexer.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv
- corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv
Expand All @@ -161,6 +143,7 @@ sources:
- corev_apu/riscv-dbg/debug_rom/debug_rom.sv
- corev_apu/register_interface/src/apb_to_reg.sv
- corev_apu/axi/src/axi_multicut.sv
- common/submodules/common_cells/src/cf_math_pkg.sv
- common/submodules/common_cells/src/deprecated/generic_fifo.sv
- common/submodules/common_cells/src/deprecated/pulp_sync.sv
- common/submodules/common_cells/src/deprecated/find_first_one.sv
Expand All @@ -178,11 +161,18 @@ sources:
- corev_apu/axi/src/axi_join.sv
- corev_apu/axi/src/axi_delayer.sv
- corev_apu/axi/src/axi_to_axi_lite.sv
- corev_apu/axi/src/axi_id_prepend.sv
- corev_apu/axi/src/axi_atop_filter.sv
- corev_apu/axi/src/axi_err_slv.sv
- corev_apu/axi/src/axi_mux.sv
- corev_apu/axi/src/axi_demux.sv
- corev_apu/axi/src/axi_xbar.sv
- corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
- common/submodules/common_cells/src/sync.sv
- common/submodules/common_cells/src/popcount.sv
- common/submodules/common_cells/src/unread.sv
- common/submodules/common_cells/src/cdc_2phase.sv
- common/submodules/common_cells/src/spill_register_flushable.sv
- common/submodules/common_cells/src/spill_register.sv
- common/submodules/common_cells/src/edge_detect.sv
- common/submodules/common_cells/src/fifo_v3.sv
Expand All @@ -198,6 +188,8 @@ sources:
- common/submodules/common_cells/src/counter.sv
- common/submodules/common_cells/src/shift_reg.sv
- common/submodules/common_cells/src/exp_backoff.sv
- common/submodules/common_cells/src/addr_decode.sv
- common/submodules/common_cells/src/stream_register.sv
- corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv
- corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
- target: not(cv32a6)
Expand Down
3 changes: 3 additions & 0 deletions CHANGELOG.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Fix non-setable MEIE bit in MIE CSR
- Bump `fpnew` to `v0.6.2`
- Restructured directories to separate CVA6 core from CVA6-APU (FPGA emulation platform for the core). See the [README](README.md#new-directory-structure) for details.
- Bump `common_cells` to `v1.23.0`
- Bump `axi` to `v0.31.0`
- Remove `axi_node` dependency, replace with `axi_xbar` from `axi` repository

#### Moved Package files
```
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53 changes: 34 additions & 19 deletions Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,12 @@ max_cycles ?= 10000000
test_case ?= core_test
# QuestaSim Version
questa_version ?= ${QUESTASIM_VERSION}
VLOG ?= vlog$(questa_version)
VSIM ?= vsim$(questa_version)
VOPT ?= vopt$(questa_version)
VCOM ?= vcom$(questa_version)
VLIB ?= vlib$(questa_version)
VMAP ?= vmap$(questa_version)
# verilator version
verilator ?= verilator
# traget option
Expand Down Expand Up @@ -162,7 +168,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
$(wildcard corev_apu/fpga/src/apb_timer/*.sv) \
$(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \
$(wildcard corev_apu/axi_node/src/*.sv) \
$(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \
$(wildcard corev_apu/axi_mem_if/src/*.sv) \
$(wildcard core/pmp/src/*.sv) \
Expand All @@ -180,6 +185,7 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
corev_apu/register_interface/src/apb_to_reg.sv \
corev_apu/axi/src/axi_multicut.sv \
common/submodules/common_cells/src/cf_math_pkg.sv \
common/submodules/common_cells/src/deprecated/generic_fifo.sv \
common/submodules/common_cells/src/deprecated/pulp_sync.sv \
common/submodules/common_cells/src/deprecated/find_first_one.sv \
Expand All @@ -188,6 +194,8 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
common/submodules/common_cells/src/stream_mux.sv \
common/submodules/common_cells/src/stream_demux.sv \
common/submodules/common_cells/src/exp_backoff.sv \
common/submodules/common_cells/src/addr_decode.sv \
common/submodules/common_cells/src/stream_register.sv \
common/local/util/axi_master_connect.sv \
common/local/util/axi_slave_connect.sv \
common/local/util/axi_master_connect_rev.sv \
Expand All @@ -196,10 +204,17 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
corev_apu/axi/src/axi_join.sv \
corev_apu/axi/src/axi_delayer.sv \
corev_apu/axi/src/axi_to_axi_lite.sv \
corev_apu/axi/src/axi_id_prepend.sv \
corev_apu/axi/src/axi_atop_filter.sv \
corev_apu/axi/src/axi_err_slv.sv \
corev_apu/axi/src/axi_mux.sv \
corev_apu/axi/src/axi_demux.sv \
corev_apu/axi/src/axi_xbar.sv \
corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv \
common/submodules/common_cells/src/unread.sv \
common/submodules/common_cells/src/sync.sv \
common/submodules/common_cells/src/cdc_2phase.sv \
common/submodules/common_cells/src/spill_register_flushable.sv \
common/submodules/common_cells/src/spill_register.sv \
common/submodules/common_cells/src/sync_wedge.sv \
common/submodules/common_cells/src/edge_detect.sv \
Expand Down Expand Up @@ -268,7 +283,7 @@ riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)

# Search here for include files (e.g.: non-standalone components)
incdir := common/submodules/common_cells/include/
incdir := common/submodules/common_cells/include/ corev_apu/axi/include/

# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
Expand Down Expand Up @@ -329,27 +344,27 @@ vcs: vcs_build
# Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
# Optimize top level
vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis
$(VOPT) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis

# src files
$(library)/.build-srcs: $(util) $(library)
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
$(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
# $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
$(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
# $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
touch $(library)/.build-srcs

# build TBs
$(library)/.build-tb: $(dpi)
# Compile top level
vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library)
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library) $(list_incdir)
touch $(library)/.build-tb

$(library):
vlib${questa_version} $(library)
$(VLIB) $(library)

# compile DPIs
$(dpi-library)/%.o: corev_apu/tb/dpi/%.cc $(dpi_hdr)
Expand All @@ -370,32 +385,32 @@ generate-trace-vsim:
make generate-trace

sim: build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log

$(riscv-asm-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log

$(riscv-amo-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log

$(riscv-mul-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log

$(riscv-fp-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log

$(riscv-benchmarks): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log

Expand Down Expand Up @@ -732,12 +747,12 @@ torture-rtest-verilator: verilate
$(MAKE) check-torture

run-torture: build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)

run-torture-log: build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf
Expand Down
2 changes: 1 addition & 1 deletion common/submodules/common_cells
Submodule common_cells updated 87 files
+16 −0 .github/verible-lint-matcher.json
+32 −0 .github/workflows/ci.yml
+3 −0 .gitignore
+64 −0 .travis.yml
+34 −9 Bender.yml
+89 −2 CHANGELOG.md
+9 −0 Makefile
+127 −68 README.md
+24 −0 ci/install-verilator.sh
+99 −0 common_cells.core
+201 −0 include/common_cells/assertions.svh
+57 −60 include/common_cells/registers.svh
+2 −0 ips_list.yml
+6 −0 lint/common_cells.style.waiver
+65 −44 src/addr_decode.sv
+22 −0 src/binary_to_gray.sv
+4 −16 src/cb_filter.sv
+26 −0 src/cb_filter_pkg.sv
+50 −0 src/cc_onehot.sv
+8 −8 src/cdc_fifo_2phase.sv
+19 −18 src/cdc_fifo_gray.sv
+26 −14 src/cf_math_pkg.sv
+1 −1 src/clk_div.sv
+0 −0 src/deprecated/sram.sv
+128 −0 src/ecc_decode.sv
+78 −0 src/ecc_encode.sv
+31 −0 src/ecc_pkg.sv
+1 −1 src/edge_detect.sv
+11 −7 src/exp_backoff.sv
+9 −8 src/fifo_v3.sv
+0 −10 src/gray_to_binary.sv
+223 −81 src/id_queue.sv
+81 −0 src/isochronous_4phase_handshake.sv
+111 −0 src/isochronous_spill_register.sv
+103 −98 src/lfsr.sv
+4 −3 src/lfsr_16bit.sv
+32 −39 src/lfsr_8bit.sv
+41 −33 src/lzc.sv
+1 −1 src/mv_filter.sv
+8 −8 src/plru_tree.sv
+9 −9 src/popcount.sv
+172 −76 src/rr_arb_tree.sv
+5 −2 src/rstgen_bypass.sv
+1 −1 src/serial_deglitch.sv
+3 −3 src/shift_reg.sv
+17 −66 src/spill_register.sv
+105 −0 src/spill_register_flushable.sv
+2 −0 src/stream_arbiter_flushable.sv
+7 −7 src/stream_delay.sv
+9 −10 src/stream_demux.sv
+66 −0 src/stream_fifo.sv
+1 −1 src/stream_fork.sv
+95 −0 src/stream_fork_dynamic.sv
+49 −0 src/stream_intf.sv
+43 −0 src/stream_join.sv
+1 −1 src/stream_mux.sv
+301 −0 src/stream_omega_net.sv
+1 −1 src/stream_register.sv
+134 −0 src/stream_to_mem.sv
+198 −0 src/stream_xbar.sv
+6 −6 src/sub_per_hash.sv
+3 −2 src/sync.sv
+22 −7 src_files.yml
+6 −0 test/.gitignore
+0 −2 test/addr_decode_tb.sv
+2 −2 test/cb_filter_tb.sv
+0 −2 test/cdc_2phase_tb.sv
+0 −2 test/cdc_fifo_tb.sv
+103 −0 test/ecc/ecc.cpp
+9 −0 test/ecc/ecc.h
+112 −0 test/ecc/ecc_decode.cpp
+76 −0 test/ecc/ecc_encode.cpp
+27 −0 test/ecc_synth.sv
+1 −7 test/fifo_tb.sv
+0 −2 test/graycode_tb.sv
+14 −17 test/id_queue_tb.sv
+186 −0 test/isochronous_crossing_tb.sv
+0 −2 test/popcount_tb.sv
+265 −0 test/rr_arb_tree_tb.sv
+33 −2 test/simulate.sh
+171 −0 test/stream_omega_net_tb.sv
+74 −0 test/stream_test.sv
+153 −0 test/stream_to_mem_tb.sv
+168 −0 test/stream_xbar_tb.sv
+2 −2 test/sub_per_hash_tb.sv
+1 −0 test/synth.sh
+2 −0 test/synth_bench.sv
10 changes: 6 additions & 4 deletions core/include/axi_intf.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -201,6 +201,7 @@ interface AXI_LITE #(

// AW channel
addr_t aw_addr;
prot_t aw_prot;
logic aw_valid;
logic aw_ready;

Expand All @@ -214,6 +215,7 @@ interface AXI_LITE #(
logic b_ready;

addr_t ar_addr;
prot_t ar_prot;
logic ar_valid;
logic ar_ready;

Expand All @@ -223,18 +225,18 @@ interface AXI_LITE #(
logic r_ready;

modport Master (
output aw_addr, aw_valid, input aw_ready,
output aw_addr, aw_prot, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_valid, input ar_ready,
output ar_addr, ar_prot, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);

modport Slave (
input aw_addr, aw_valid, output aw_ready,
input aw_addr, aw_prot, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_valid, output ar_ready,
input ar_addr, ar_prot, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);

Expand Down
2 changes: 1 addition & 1 deletion corev_apu/axi
Submodule axi updated 116 files
1 change: 0 additions & 1 deletion corev_apu/axi_node
Submodule axi_node deleted from a29a69
2 changes: 1 addition & 1 deletion corev_apu/fpga/scripts/run.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ read_ip { \
}
# read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci

set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" } [current_fileset]
set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" "../axi/include"} [current_fileset]

source scripts/add_sources.tcl

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