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ECE2300.eda.rpt
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EDA Netlist Writer report for ECE2300
Fri Nov 30 15:57:19 2018
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Fri Nov 30 15:57:19 2018 ;
; Revision Name ; ECE2300 ;
; Top-level Entity Name ; lab4_top ;
; Family ; Cyclone V ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+---------------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------------+
; C:/Users/jly72/Desktop/Cornell/lab 4 part c/lab4/simulation/modelsim/ECE2300.vo ;
+---------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
Info: Processing started: Fri Nov 30 15:57:17 2018
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off lab4 -c ECE2300
Warning (10905): Generated the EDA functional simulation files although EDA timing simulation option is chosen.
Info (204019): Generated file ECE2300.vo in folder "C:/Users/jly72/Desktop/Cornell/lab 4 part c/lab4/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4843 megabytes
Info: Processing ended: Fri Nov 30 15:57:19 2018
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:03