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JohnLy57/Single-Cycle-Microprocessor-with-Heart-Rate-Monitor-Simulation

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db
db
 
 
incremental_db
incremental_db
 
 
simulation/modelsim
simulation/modelsim
 
 
ECE2300.asm.rpt
ECE2300.asm.rpt
 
 
ECE2300.cdf
ECE2300.cdf
 
 
ECE2300.done
ECE2300.done
 
 
ECE2300.eda.rpt
ECE2300.eda.rpt
 
 
ECE2300.fit.rpt
ECE2300.fit.rpt
 
 
ECE2300.fit.smsg
ECE2300.fit.smsg
 
 
ECE2300.fit.summary
ECE2300.fit.summary
 
 
ECE2300.flow.rpt
ECE2300.flow.rpt
 
 
ECE2300.jdi
ECE2300.jdi
 
 
ECE2300.map.rpt
ECE2300.map.rpt
 
 
ECE2300.map.smsg
ECE2300.map.smsg
 
 
ECE2300.map.summary
ECE2300.map.summary
 
 
ECE2300.pin
ECE2300.pin
 
 
ECE2300.qsf
ECE2300.qsf
 
 
ECE2300.qws
ECE2300.qws
 
 
ECE2300.sdc
ECE2300.sdc
 
 
ECE2300.sld
ECE2300.sld
 
 
ECE2300.sof
ECE2300.sof
 
 
ECE2300.sta.rpt
ECE2300.sta.rpt
 
 
ECE2300.sta.summary
ECE2300.sta.summary
 
 
ECE2300_assignment_defaults.qdf
ECE2300_assignment_defaults.qdf
 
 
ECE2300_nativelink_simulation.rpt
ECE2300_nativelink_simulation.rpt
 
 
Haltlogic.v
Haltlogic.v
 
 
README.md
README.md
 
 
_DS_Store
_DS_Store
 
 
adder.v
adder.v
 
 
alu.v
alu.v
 
 
bitadd.v
bitadd.v
 
 
c5_pin_model_dump.txt
c5_pin_model_dump.txt
 
 
control.v
control.v
 
 
cpu.v
cpu.v
 
 
cpu_muxMB.v
cpu_muxMB.v
 
 
cpu_muxMD.v
cpu_muxMD.v
 
 
cpu_muxPC.v
cpu_muxPC.v
 
 
decoder.qpf
decoder.qpf
 
 
decoder.qsf
decoder.qsf
 
 
decoder.v
decoder.v
 
 
decoder.v.bak
decoder.v.bak
 
 
decoder_test.v
decoder_test.v
 
 
dual_reg_in.v
dual_reg_in.v
 
 
hex_to_seven_seg.v
hex_to_seven_seg.v
 
 
lab4.qpf
lab4.qpf
 
 
lab4.v
lab4.v
 
 
lab4.v.bak
lab4.v.bak
 
 
lab4_test.v
lab4_test.v
 
 
lab4_top.v
lab4_top.v
 
 
lab4dram.v
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lab4iram.v
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lab4iramHRM.v
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lab4iramHRMmod.v
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lab4iramHRMmod.v.bak
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lab4iramHRMmod2.v
lab4iramHRMmod2.v
 
 
lab4iramHRMmod2.v.bak
lab4iramHRMmod2.v.bak
 
 
lab4iramHalt.v
lab4iramHalt.v
 
 
logical.v
logical.v
 
 
muxB.v
muxB.v
 
 
muxCI.v
muxCI.v
 
 
muxMP.v
muxMP.v
 
 
muxNextPC.v
muxNextPC.v
 
 
muxY.v
muxY.v
 
 
opsel.v
opsel.v
 
 
programcounter.v
programcounter.v
 
 
registerfile.v
registerfile.v
 
 
shifter.v
shifter.v
 
 
sign_extend.v
sign_extend.v
 
 
sign_xshift.v
sign_xshift.v
 
 
var_clk.v
var_clk.v
 
 

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Designed on a Cyclone IV FPGA in Verilog for Cornell ECE 2300

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Completed as a part of my Digital Logic and Computer Organization class

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