Home

There are many open source tools as a replacement for the proprietary tools used in communication and electronic systems but we identified that there are a very few contributions in the VLSI stream using open source. Hence, our area of work revolves around contributing in the VLSI stream.

Our area of work involves developing open cores. Open cores is the open source product similar to IP cores. IP block is a reusable unit of logic, cell, or integrated circuit (commonly called a "chip") layout design. An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array which is licensed. In place of intellectual property cores we will use open cores which is an open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. Open Cores hopes to eliminate redundant design work and slash development costs.

The open source tools identified to implement Open Cores are Iverilog and GTKWaveform. Iverilog is an open source verilog simulator which is used to design the digital circuits. The results of iverilog are seen as values but it cannot be used show the graphical analysis like in timing diagrams.So for this we are using a tool called GTKWave which supports Iverilog for graphical analysis.By modifying the test bench we can create a file called *.vcd which is used to see timing diagrams as in Xilinx or Vivado tool.

The concept we are trying to implement is Partial Reconfiguration. Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems. This methodology is to be implemented using Open Cores.