Add SPV_EXT_arithmetic_fence (#450)

* Add SPV_EXT_arithmetic_fence Spec: https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_arithmetic_fence.html Signed-off-by: Sidorov, Dmitry <[email protected]> * Also add INTEL extension for tooling Signed-off-by: Sidorov, Dmitry <[email protected]> * Revert "Also add INTEL extension for tooling" This reverts commit ce256a3. --------- Signed-off-by: Sidorov, Dmitry <[email protected]>
KhronosGroup · Oct 2, 2024 · a62b032 · a62b032
1 parent ec59c77
commit a62b032
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diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
@@ -1264,6 +1264,7 @@ namespace Spv
             DebugInfoModuleINTEL = 6114,
             BFloat16ConversionINTEL = 6115,
             SplitBarrierINTEL = 6141,
+            ArithmeticFenceEXT = 6144,
             FPGAClusterAttributesV2INTEL = 6150,
             FPGAKernelAttributesv2INTEL = 6161,
             FPMaxErrorINTEL = 6169,
@@ -2228,6 +2229,7 @@ namespace Spv
             OpConvertBF16ToFINTEL = 6117,
             OpControlBarrierArriveINTEL = 6142,
             OpControlBarrierWaitINTEL = 6143,
+            OpArithmeticFenceEXT = 6145,
             OpSubgroupBlockPrefetchINTEL = 6221,
             OpGroupIMulKHR = 6401,
             OpGroupFMulKHR = 6402,

diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
@@ -9920,6 +9920,18 @@
       "capabilities" : [ "SplitBarrierINTEL" ],
       "version" : "None"
     },
+    {
+      "opname" : "OpArithmeticFenceEXT",
+      "class"  : "Miscellaneous",
+      "opcode" : 6145,
+      "operands" : [
+        { "kind" : "IdResultType" },
+        { "kind" : "IdResult" },
+        { "kind" : "IdRef",          "name" : "'Target '" }
+      ],
+      "capabilities" : [ "ArithmeticFenceEXT" ],
+      "version" : "None"
+    },
     {
       "opname" : "OpSubgroupBlockPrefetchINTEL",
       "class"  : "Group",
@@ -16753,6 +16765,12 @@
           "extensions" : [ "SPV_INTEL_split_barrier" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "ArithmeticFenceEXT",
+          "value" : 6144,
+          "extensions" : [ "SPV_EXT_arithmetic_fence" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "FPGAClusterAttributesV2INTEL",
           "value" : 6150,

diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
@@ -1263,6 +1263,7 @@ public enum Capability
             DebugInfoModuleINTEL = 6114,
             BFloat16ConversionINTEL = 6115,
             SplitBarrierINTEL = 6141,
+            ArithmeticFenceEXT = 6144,
             FPGAClusterAttributesV2INTEL = 6150,
             FPGAKernelAttributesv2INTEL = 6161,
             FPMaxErrorINTEL = 6169,
@@ -2227,6 +2228,7 @@ public enum Op
             OpConvertBF16ToFINTEL = 6117,
             OpControlBarrierArriveINTEL = 6142,
             OpControlBarrierWaitINTEL = 6143,
+            OpArithmeticFenceEXT = 6145,
             OpSubgroupBlockPrefetchINTEL = 6221,
             OpGroupIMulKHR = 6401,
             OpGroupFMulKHR = 6402,

diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
@@ -1234,6 +1234,7 @@ typedef enum SpvCapability_ {
     SpvCapabilityDebugInfoModuleINTEL = 6114,
     SpvCapabilityBFloat16ConversionINTEL = 6115,
     SpvCapabilitySplitBarrierINTEL = 6141,
+    SpvCapabilityArithmeticFenceEXT = 6144,
     SpvCapabilityFPGAClusterAttributesV2INTEL = 6150,
     SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
     SpvCapabilityFPMaxErrorINTEL = 6169,
@@ -2173,6 +2174,7 @@ typedef enum SpvOp_ {
     SpvOpConvertBF16ToFINTEL = 6117,
     SpvOpControlBarrierArriveINTEL = 6142,
     SpvOpControlBarrierWaitINTEL = 6143,
+    SpvOpArithmeticFenceEXT = 6145,
     SpvOpSubgroupBlockPrefetchINTEL = 6221,
     SpvOpGroupIMulKHR = 6401,
     SpvOpGroupFMulKHR = 6402,
@@ -2919,6 +2921,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
     case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
     case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+    case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
     case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
     case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
@@ -3831,6 +3834,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
     case SpvCapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
     case SpvCapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
     case SpvCapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
+    case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
     case SpvCapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
     case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
     case SpvCapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
@@ -4716,6 +4720,7 @@ inline const char* SpvOpToString(SpvOp value) {
     case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
     case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
     case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
+    case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
     case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
     case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
     case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";

diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
@@ -1230,6 +1230,7 @@ enum Capability {
     CapabilityDebugInfoModuleINTEL = 6114,
     CapabilityBFloat16ConversionINTEL = 6115,
     CapabilitySplitBarrierINTEL = 6141,
+    CapabilityArithmeticFenceEXT = 6144,
     CapabilityFPGAClusterAttributesV2INTEL = 6150,
     CapabilityFPGAKernelAttributesv2INTEL = 6161,
     CapabilityFPMaxErrorINTEL = 6169,
@@ -2169,6 +2170,7 @@ enum Op {
     OpConvertBF16ToFINTEL = 6117,
     OpControlBarrierArriveINTEL = 6142,
     OpControlBarrierWaitINTEL = 6143,
+    OpArithmeticFenceEXT = 6145,
     OpSubgroupBlockPrefetchINTEL = 6221,
     OpGroupIMulKHR = 6401,
     OpGroupFMulKHR = 6402,
@@ -2915,6 +2917,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
     case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
     case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
     case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+    case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
     case OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
     case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
     case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
@@ -3827,6 +3830,7 @@ inline const char* CapabilityToString(Capability value) {
     case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
     case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
     case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
+    case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
     case CapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
     case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
     case CapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
@@ -4712,6 +4716,7 @@ inline const char* OpToString(Op value) {
     case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
     case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
     case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
+    case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
     case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
     case OpGroupIMulKHR: return "OpGroupIMulKHR";
     case OpGroupFMulKHR: return "OpGroupFMulKHR";

diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
@@ -1230,6 +1230,7 @@ enum class Capability : unsigned {
     DebugInfoModuleINTEL = 6114,
     BFloat16ConversionINTEL = 6115,
     SplitBarrierINTEL = 6141,
+    ArithmeticFenceEXT = 6144,
     FPGAClusterAttributesV2INTEL = 6150,
     FPGAKernelAttributesv2INTEL = 6161,
     FPMaxErrorINTEL = 6169,
@@ -2169,6 +2170,7 @@ enum class Op : unsigned {
     OpConvertBF16ToFINTEL = 6117,
     OpControlBarrierArriveINTEL = 6142,
     OpControlBarrierWaitINTEL = 6143,
+    OpArithmeticFenceEXT = 6145,
     OpSubgroupBlockPrefetchINTEL = 6221,
     OpGroupIMulKHR = 6401,
     OpGroupFMulKHR = 6402,
@@ -2915,6 +2917,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
     case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
     case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+    case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
     case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
     case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
     case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
@@ -3827,6 +3830,7 @@ inline const char* CapabilityToString(Capability value) {
     case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
     case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
     case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
+    case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
     case CapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
     case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
     case CapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
@@ -4712,6 +4716,7 @@ inline const char* OpToString(Op value) {
     case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
     case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
     case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
+    case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
     case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
     case OpGroupIMulKHR: return "OpGroupIMulKHR";
     case OpGroupFMulKHR: return "OpGroupFMulKHR";

diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
@@ -1206,6 +1206,7 @@
                     "DebugInfoModuleINTEL": 6114,
                     "BFloat16ConversionINTEL": 6115,
                     "SplitBarrierINTEL": 6141,
+                    "ArithmeticFenceEXT": 6144,
                     "FPGAClusterAttributesV2INTEL": 6150,
                     "FPGAKernelAttributesv2INTEL": 6161,
                     "FPMaxErrorINTEL": 6169,
@@ -2170,6 +2171,7 @@
                     "OpConvertBF16ToFINTEL": 6117,
                     "OpControlBarrierArriveINTEL": 6142,
                     "OpControlBarrierWaitINTEL": 6143,
+                    "OpArithmeticFenceEXT": 6145,
                     "OpSubgroupBlockPrefetchINTEL": 6221,
                     "OpGroupIMulKHR": 6401,
                     "OpGroupFMulKHR": 6402,

diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
@@ -1221,6 +1221,7 @@ spv = {
         DebugInfoModuleINTEL = 6114,
         BFloat16ConversionINTEL = 6115,
         SplitBarrierINTEL = 6141,
+        ArithmeticFenceEXT = 6144,
         FPGAClusterAttributesV2INTEL = 6150,
         FPGAKernelAttributesv2INTEL = 6161,
         FPMaxErrorINTEL = 6169,
@@ -2160,6 +2161,7 @@ spv = {
         OpConvertBF16ToFINTEL = 6117,
         OpControlBarrierArriveINTEL = 6142,
         OpControlBarrierWaitINTEL = 6143,
+        OpArithmeticFenceEXT = 6145,
         OpSubgroupBlockPrefetchINTEL = 6221,
         OpGroupIMulKHR = 6401,
         OpGroupFMulKHR = 6402,

diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
@@ -1192,6 +1192,7 @@
         'DebugInfoModuleINTEL' : 6114,
         'BFloat16ConversionINTEL' : 6115,
         'SplitBarrierINTEL' : 6141,
+        'ArithmeticFenceEXT' : 6144,
         'FPGAClusterAttributesV2INTEL' : 6150,
         'FPGAKernelAttributesv2INTEL' : 6161,
         'FPMaxErrorINTEL' : 6169,
@@ -2110,6 +2111,7 @@
         'OpConvertBF16ToFINTEL' : 6117,
         'OpControlBarrierArriveINTEL' : 6142,
         'OpControlBarrierWaitINTEL' : 6143,
+        'OpArithmeticFenceEXT' : 6145,
         'OpSubgroupBlockPrefetchINTEL' : 6221,
         'OpGroupIMulKHR' : 6401,
         'OpGroupFMulKHR' : 6402,

diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
@@ -1266,6 +1266,7 @@ enum Capability : uint
     DebugInfoModuleINTEL = 6114,
     BFloat16ConversionINTEL = 6115,
     SplitBarrierINTEL = 6141,
+    ArithmeticFenceEXT = 6144,
     FPGAClusterAttributesV2INTEL = 6150,
     FPGAKernelAttributesv2INTEL = 6161,
     FPMaxErrorINTEL = 6169,
@@ -2230,6 +2231,7 @@ enum Op : uint
     OpConvertBF16ToFINTEL = 6117,
     OpControlBarrierArriveINTEL = 6142,
     OpControlBarrierWaitINTEL = 6143,
+    OpArithmeticFenceEXT = 6145,
     OpSubgroupBlockPrefetchINTEL = 6221,
     OpGroupIMulKHR = 6401,
     OpGroupFMulKHR = 6402,