Headers support for two Intel extensions (#356)

* Add SPV_INTEL_global_variable_fpga_decorations Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_global_variable_fpga_decorations.asciidoc * Add SPV_INTEL_global_variable_host_access Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_global_variable_host_access.asciidoc * Update headers generator * update headers after generating script
KhronosGroup · Aug 16, 2023 · b8b9eb8 · b8b9eb8
1 parent 45fc02a
commit b8b9eb8
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diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
@@ -599,6 +599,9 @@ namespace Spv
             SingleElementVectorINTEL = 6085,
             VectorComputeCallableFunctionINTEL = 6087,
             MediaBlockIOINTEL = 6140,
+            InitModeINTEL = 6147,
+            ImplementInRegisterMapINTEL = 6148,
+            HostAccessINTEL = 6168,
             FPMaxErrorDecorationINTEL = 6170,
             LatencyControlLabelINTEL = 6172,
             LatencyControlConstraintINTEL = 6173,
@@ -1188,7 +1191,9 @@ namespace Spv
             DebugInfoModuleINTEL = 6114,
             BFloat16ConversionINTEL = 6115,
             SplitBarrierINTEL = 6141,
+            GlobalVariableFPGADecorationsINTEL = 6146,
             FPGAKernelAttributesv2INTEL = 6161,
+            GlobalVariableHostAccessINTEL = 6167,
             FPMaxErrorINTEL = 6169,
             FPGALatencyControlINTEL = 6171,
             FPGAArgumentInterfacesINTEL = 6174,
@@ -1332,6 +1337,20 @@ namespace Spv
             MatrixAccumulatorKHR = 2,
         }
 
+        [AllowDuplicates, CRepr] public enum InitializationModeQualifier
+        {
+            InitOnDeviceReprogramINTEL = 0,
+            InitOnDeviceResetINTEL = 1,
+        }
+
+        [AllowDuplicates, CRepr] public enum HostAccessQualifier
+        {
+            NoneINTEL = 0,
+            ReadINTEL = 1,
+            WriteINTEL = 2,
+            ReadWriteINTEL = 3,
+        }
+
         [AllowDuplicates, CRepr] public enum Op
         {
             OpNop = 0,

diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
@@ -11981,6 +11981,32 @@
         }
       ]
     },
+    {
+      "category" : "ValueEnum",
+      "kind" : "HostAccessQualifier",
+      "enumerants" : [
+        {
+          "enumerant" : "NoneINTEL",
+          "value" : 0,
+          "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+        },
+        {
+          "enumerant" : "ReadINTEL",
+          "value" : 1,
+          "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+        },
+        {
+          "enumerant" : "WriteINTEL",
+          "value" : 2,
+          "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+        },
+        {
+          "enumerant" : "ReadWriteINTEL",
+          "value" : 3,
+          "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+        }
+      ]
+    },
     {
       "category" : "ValueEnum",
       "kind" : "FunctionParameterAttribute",
@@ -12926,6 +12952,34 @@
           "capabilities" : [ "VectorComputeINTEL" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "InitModeINTEL",
+          "value" : 6147,
+          "parameters": [
+            { "kind" : "InitializationModeQualifier", "name" : "'Trigger'" }
+          ],
+          "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "ImplementInRegisterMapINTEL",
+          "value" : 6148,
+          "parameters": [
+            { "kind" : "LiteralInteger", "name" : "Value" }
+          ],
+          "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "HostAccessINTEL",
+          "value" : 6168,
+          "parameters": [
+            { "kind" : "HostAccessQualifier", "name" : "'Access'" },
+            { "kind" : "LiteralString", "name" : "'Name'" }
+          ],
+          "capabilities" : [ "GlobalVariableHostAccessINTEL" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "FPMaxErrorDecorationINTEL",
           "value" : 6170,
@@ -15418,13 +15472,25 @@
           "extensions" : [ "SPV_INTEL_split_barrier" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "GlobalVariableFPGADecorationsINTEL",
+          "value" : 6146,
+          "extensions": [ "SPV_INTEL_global_variable_fpga_decorations" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "FPGAKernelAttributesv2INTEL",
           "value" : 6161,
           "capabilities" : [ "FPGAKernelAttributesINTEL" ],
           "extensions" : [ "SPV_INTEL_kernel_attributes" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "GlobalVariableHostAccessINTEL",
+          "value" : 6167,
+          "extensions": [ "SPV_INTEL_global_variable_host_access" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "FPMaxErrorINTEL",
           "value" : 6169,
@@ -15601,6 +15667,24 @@
         }
       ]
     },
+    {
+      "category" : "ValueEnum",
+      "kind" : "InitializationModeQualifier",
+      "enumerants" : [
+        {
+          "enumerant" : "InitOnDeviceReprogramINTEL",
+          "value" : 0,
+          "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "InitOnDeviceResetINTEL",
+          "value" : 1,
+          "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+          "version" : "None"
+        }
+      ]
+    },
     {
       "category" : "Id",
       "kind" : "IdResultType",

diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
@@ -598,6 +598,9 @@ public enum Decoration
             SingleElementVectorINTEL = 6085,
             VectorComputeCallableFunctionINTEL = 6087,
             MediaBlockIOINTEL = 6140,
+            InitModeINTEL = 6147,
+            ImplementInRegisterMapINTEL = 6148,
+            HostAccessINTEL = 6168,
             FPMaxErrorDecorationINTEL = 6170,
             LatencyControlLabelINTEL = 6172,
             LatencyControlConstraintINTEL = 6173,
@@ -1187,7 +1190,9 @@ public enum Capability
             DebugInfoModuleINTEL = 6114,
             BFloat16ConversionINTEL = 6115,
             SplitBarrierINTEL = 6141,
+            GlobalVariableFPGADecorationsINTEL = 6146,
             FPGAKernelAttributesv2INTEL = 6161,
+            GlobalVariableHostAccessINTEL = 6167,
             FPMaxErrorINTEL = 6169,
             FPGALatencyControlINTEL = 6171,
             FPGAArgumentInterfacesINTEL = 6174,
@@ -1331,6 +1336,20 @@ public enum CooperativeMatrixUse
             MatrixAccumulatorKHR = 2,
         }
 
+        public enum InitializationModeQualifier
+        {
+            InitOnDeviceReprogramINTEL = 0,
+            InitOnDeviceResetINTEL = 1,
+        }
+
+        public enum HostAccessQualifier
+        {
+            NoneINTEL = 0,
+            ReadINTEL = 1,
+            WriteINTEL = 2,
+            ReadWriteINTEL = 3,
+        }
+
         public enum Op
         {
             OpNop = 0,

diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
@@ -604,6 +604,9 @@ typedef enum SpvDecoration_ {
     SpvDecorationSingleElementVectorINTEL = 6085,
     SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
     SpvDecorationMediaBlockIOINTEL = 6140,
+    SpvDecorationInitModeINTEL = 6147,
+    SpvDecorationImplementInRegisterMapINTEL = 6148,
+    SpvDecorationHostAccessINTEL = 6168,
     SpvDecorationFPMaxErrorDecorationINTEL = 6170,
     SpvDecorationLatencyControlLabelINTEL = 6172,
     SpvDecorationLatencyControlConstraintINTEL = 6173,
@@ -1187,7 +1190,9 @@ typedef enum SpvCapability_ {
     SpvCapabilityDebugInfoModuleINTEL = 6114,
     SpvCapabilityBFloat16ConversionINTEL = 6115,
     SpvCapabilitySplitBarrierINTEL = 6141,
+    SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6146,
     SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
+    SpvCapabilityGlobalVariableHostAccessINTEL = 6167,
     SpvCapabilityFPMaxErrorINTEL = 6169,
     SpvCapabilityFPGALatencyControlINTEL = 6171,
     SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
@@ -1329,6 +1334,20 @@ typedef enum SpvCooperativeMatrixUse_ {
     SpvCooperativeMatrixUseMax = 0x7fffffff,
 } SpvCooperativeMatrixUse;
 
+typedef enum SpvInitializationModeQualifier_ {
+    SpvInitializationModeQualifierInitOnDeviceReprogramINTEL = 0,
+    SpvInitializationModeQualifierInitOnDeviceResetINTEL = 1,
+    SpvInitializationModeQualifierMax = 0x7fffffff,
+} SpvInitializationModeQualifier;
+
+typedef enum SpvHostAccessQualifier_ {
+    SpvHostAccessQualifierNoneINTEL = 0,
+    SpvHostAccessQualifierReadINTEL = 1,
+    SpvHostAccessQualifierWriteINTEL = 2,
+    SpvHostAccessQualifierReadWriteINTEL = 3,
+    SpvHostAccessQualifierMax = 0x7fffffff,
+} SpvHostAccessQualifier;
+
 typedef enum SpvOp_ {
     SpvOpNop = 0,
     SpvOpUndef = 1,

diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
@@ -600,6 +600,9 @@ enum Decoration {
     DecorationSingleElementVectorINTEL = 6085,
     DecorationVectorComputeCallableFunctionINTEL = 6087,
     DecorationMediaBlockIOINTEL = 6140,
+    DecorationInitModeINTEL = 6147,
+    DecorationImplementInRegisterMapINTEL = 6148,
+    DecorationHostAccessINTEL = 6168,
     DecorationFPMaxErrorDecorationINTEL = 6170,
     DecorationLatencyControlLabelINTEL = 6172,
     DecorationLatencyControlConstraintINTEL = 6173,
@@ -1183,7 +1186,9 @@ enum Capability {
     CapabilityDebugInfoModuleINTEL = 6114,
     CapabilityBFloat16ConversionINTEL = 6115,
     CapabilitySplitBarrierINTEL = 6141,
+    CapabilityGlobalVariableFPGADecorationsINTEL = 6146,
     CapabilityFPGAKernelAttributesv2INTEL = 6161,
+    CapabilityGlobalVariableHostAccessINTEL = 6167,
     CapabilityFPMaxErrorINTEL = 6169,
     CapabilityFPGALatencyControlINTEL = 6171,
     CapabilityFPGAArgumentInterfacesINTEL = 6174,
@@ -1325,6 +1330,20 @@ enum CooperativeMatrixUse {
     CooperativeMatrixUseMax = 0x7fffffff,
 };
 
+enum InitializationModeQualifier {
+    InitializationModeQualifierInitOnDeviceReprogramINTEL = 0,
+    InitializationModeQualifierInitOnDeviceResetINTEL = 1,
+    InitializationModeQualifierMax = 0x7fffffff,
+};
+
+enum HostAccessQualifier {
+    HostAccessQualifierNoneINTEL = 0,
+    HostAccessQualifierReadINTEL = 1,
+    HostAccessQualifierWriteINTEL = 2,
+    HostAccessQualifierReadWriteINTEL = 3,
+    HostAccessQualifierMax = 0x7fffffff,
+};
+
 enum Op {
     OpNop = 0,
     OpUndef = 1,

diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
@@ -600,6 +600,9 @@ enum class Decoration : unsigned {
     SingleElementVectorINTEL = 6085,
     VectorComputeCallableFunctionINTEL = 6087,
     MediaBlockIOINTEL = 6140,
+    InitModeINTEL = 6147,
+    ImplementInRegisterMapINTEL = 6148,
+    HostAccessINTEL = 6168,
     FPMaxErrorDecorationINTEL = 6170,
     LatencyControlLabelINTEL = 6172,
     LatencyControlConstraintINTEL = 6173,
@@ -1183,7 +1186,9 @@ enum class Capability : unsigned {
     DebugInfoModuleINTEL = 6114,
     BFloat16ConversionINTEL = 6115,
     SplitBarrierINTEL = 6141,
+    GlobalVariableFPGADecorationsINTEL = 6146,
     FPGAKernelAttributesv2INTEL = 6161,
+    GlobalVariableHostAccessINTEL = 6167,
     FPMaxErrorINTEL = 6169,
     FPGALatencyControlINTEL = 6171,
     FPGAArgumentInterfacesINTEL = 6174,
@@ -1325,6 +1330,20 @@ enum class CooperativeMatrixUse : unsigned {
     Max = 0x7fffffff,
 };
 
+enum class InitializationModeQualifier : unsigned {
+    InitOnDeviceReprogramINTEL = 0,
+    InitOnDeviceResetINTEL = 1,
+    Max = 0x7fffffff,
+};
+
+enum class HostAccessQualifier : unsigned {
+    NoneINTEL = 0,
+    ReadINTEL = 1,
+    WriteINTEL = 2,
+    ReadWriteINTEL = 3,
+    Max = 0x7fffffff,
+};
+
 enum class Op : unsigned {
     OpNop = 0,
     OpUndef = 1,

diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
@@ -626,6 +626,9 @@
                     "SingleElementVectorINTEL": 6085,
                     "VectorComputeCallableFunctionINTEL": 6087,
                     "MediaBlockIOINTEL": 6140,
+                    "InitModeINTEL": 6147,
+                    "ImplementInRegisterMapINTEL": 6148,
+                    "HostAccessINTEL": 6168,
                     "FPMaxErrorDecorationINTEL": 6170,
                     "LatencyControlLabelINTEL": 6172,
                     "LatencyControlConstraintINTEL": 6173,
@@ -1163,7 +1166,9 @@
                     "DebugInfoModuleINTEL": 6114,
                     "BFloat16ConversionINTEL": 6115,
                     "SplitBarrierINTEL": 6141,
+                    "GlobalVariableFPGADecorationsINTEL": 6146,
                     "FPGAKernelAttributesv2INTEL": 6161,
+                    "GlobalVariableHostAccessINTEL": 6167,
                     "FPMaxErrorINTEL": 6169,
                     "FPGALatencyControlINTEL": 6171,
                     "FPGAArgumentInterfacesINTEL": 6174,
@@ -1311,6 +1316,26 @@
                     "MatrixAccumulatorKHR": 2
                 }
             },
+            {
+                "Name": "InitializationModeQualifier",
+                "Type": "Value",
+                "Values":
+                {
+                    "InitOnDeviceReprogramINTEL": 0,
+                    "InitOnDeviceResetINTEL": 1
+                }
+            },
+            {
+                "Name": "HostAccessQualifier",
+                "Type": "Value",
+                "Values":
+                {
+                    "NoneINTEL": 0,
+                    "ReadINTEL": 1,
+                    "WriteINTEL": 2,
+                    "ReadWriteINTEL": 3
+                }
+            },
             {
                 "Name": "Op",
                 "Type": "Value",