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refactor(FTQ): prune the least significant bit of PC
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@Yan-Muzi
Yan-Muzi committed Nov 27, 2024
1 parent 225a94c commit bbc16e6
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Showing 2 changed files with 39 additions and 40 deletions.
37 changes: 18 additions & 19 deletions src/main/scala/xiangshan/frontend/FTB.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,10 +55,10 @@ class FtbSlot(val offsetLen: Int, val subOffsetLen: Option[Int] = None)(implicit
val lower = UInt(offsetLen.W)
val tarStat = UInt(TAR_STAT_SZ.W)

def setLowerStatByTarget(pc: UInt, target: UInt, isShare: Boolean) = {
def setLowerStatByTarget(pc: Pc, target: Pc, isShare: Boolean): Unit = {
def getTargetStatByHigher(pc_higher: UInt, target_higher: UInt) =
Mux(target_higher > pc_higher, TAR_OVF, Mux(target_higher < pc_higher, TAR_UDF, TAR_FIT))
def getLowerByTarget(target: UInt, offsetLen: Int) = target(offsetLen, 1)
def getLowerByTarget(target: Pc, offsetLen: Int) = target(offsetLen, 1)
val offLen = if (isShare) this.subOffsetLen.get else this.offsetLen
val pc_higher = pc(VAddrBits - 1, offLen + 1)
val target_higher = target(VAddrBits - 1, offLen + 1)
Expand All @@ -69,8 +69,8 @@ class FtbSlot(val offsetLen: Int, val subOffsetLen: Option[Int] = None)(implicit
this.sharing := isShare.B
}

def getTarget(pc: UInt, last_stage: Option[Tuple2[UInt, Bool]] = None) = {
def getTarget(offLen: Int)(pc: UInt, lower: UInt, stat: UInt, last_stage: Option[Tuple2[UInt, Bool]] = None) = {
def getTarget(pc: Pc, last_stage: Option[(UInt, Bool)] = None): Pc = {
def getTarget(offLen: Int)(pc: Pc, lower: UInt, stat: UInt, last_stage: Option[(UInt, Bool)] = None): Pc = {
val h = pc(VAddrBits - 1, offLen + 1)
val higher = Wire(UInt((VAddrBits - offLen - 1).W))
val higher_plus_one = Wire(UInt((VAddrBits - offLen - 1).W))
Expand All @@ -90,28 +90,27 @@ class FtbSlot(val offsetLen: Int, val subOffsetLen: Option[Int] = None)(implicit
higher_plus_one := h + 1.U
higher_minus_one := h - 1.U
}
val target =
Cat(
Mux1H(Seq(
(stat === TAR_OVF, higher_plus_one),
(stat === TAR_UDF, higher_minus_one),
(stat === TAR_FIT, higher)
)),
lower(offLen - 1, 0),
0.U(1.W)
)
require(target.getWidth == VAddrBits)
val target = Pc(Cat(
Mux1H(Seq(
(stat === TAR_OVF, higher_plus_one),
(stat === TAR_UDF, higher_minus_one),
(stat === TAR_FIT, higher)
)),
lower(offLen - 1, 0),
0.U(1.W)
))
require(offLen != 0)
target
}
if (subOffsetLen.isDefined)
if (subOffsetLen.isDefined) {
Mux(
sharing,
getTarget(subOffsetLen.get)(pc, lower, tarStat, last_stage),
getTarget(offsetLen)(pc, lower, tarStat, last_stage)
)
else
} else {
getTarget(offsetLen)(pc, lower, tarStat, last_stage)
}
}
def fromAnotherSlot(that: FtbSlot) = {
require(
Expand Down Expand Up @@ -200,11 +199,11 @@ class FTBEntry(implicit p: Parameters) extends FTBEntry_part with FTBParams with
}
def allSlotsForBr =
(0 until numBr).map(getSlotForBr(_))
def setByBrTarget(brIdx: Int, pc: UInt, target: UInt) = {
def setByBrTarget(brIdx: Int, pc: Pc, target: Pc) = {
val slot = getSlotForBr(brIdx)
slot.setLowerStatByTarget(pc, target, brIdx == numBr - 1)
}
def setByJmpTarget(pc: UInt, target: UInt) =
def setByJmpTarget(pc: Pc, target: Pc) =
this.tailSlot.setLowerStatByTarget(pc, target, false)

def getTargetVec(pc: UInt, last_stage: Option[Tuple2[UInt, Bool]] = None) = {
Expand Down
42 changes: 21 additions & 21 deletions src/main/scala/xiangshan/frontend/NewFtq.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -88,14 +88,14 @@ class FtqNRSRAM[T <: Data](gen: T, numRead: Int)(implicit p: Parameters) extends
}

class Ftq_RF_Components(implicit p: Parameters) extends XSBundle with BPUUtils {
val startAddr = UInt(VAddrBits.W)
val nextLineAddr = UInt(VAddrBits.W)
val startAddr = Pc()
val nextLineAddr = Pc()
val isNextMask = Vec(PredictWidth, Bool())
val fallThruError = Bool()
// val carry = Bool()
def getPc(offset: UInt) = {
def getHigher(pc: UInt) = pc(VAddrBits - 1, log2Ceil(PredictWidth) + instOffsetBits + 1)
def getOffset(pc: UInt) = pc(log2Ceil(PredictWidth) + instOffsetBits, instOffsetBits)
def getPc(offset: UInt): UInt = {
def getHigher(pc: Pc) = pc(VAddrBits - 1, log2Ceil(PredictWidth) + instOffsetBits + 1)
def getOffset(pc: Pc) = pc(log2Ceil(PredictWidth) + instOffsetBits, instOffsetBits)
Cat(
getHigher(Mux(isNextMask(offset) && startAddr(log2Ceil(PredictWidth) + instOffsetBits), nextLineAddr, startAddr)),
getOffset(startAddr) + offset,
Expand All @@ -113,14 +113,14 @@ class Ftq_RF_Components(implicit p: Parameters) extends XSBundle with BPUUtils {
this
}
override def toPrintable: Printable =
p"startAddr:${Hexadecimal(startAddr)}"
p"startAddr:${Hexadecimal(startAddr())}"
}

class Ftq_pd_Entry(implicit p: Parameters) extends XSBundle {
val brMask = Vec(PredictWidth, Bool())
val jmpInfo = ValidUndirectioned(Vec(3, Bool()))
val jmpOffset = UInt(log2Ceil(PredictWidth).W)
val jalTarget = UInt(VAddrBits.W)
val jalTarget = Pc()
val rvcMask = Vec(PredictWidth, Bool())
def hasJal = jmpInfo.valid && !jmpInfo.bits(0)
def hasJalr = jmpInfo.valid && jmpInfo.bits(0)
Expand Down Expand Up @@ -169,7 +169,7 @@ class Ftq_1R_SRAMEntry(implicit p: Parameters) extends XSBundle with HasBPUConst
}

class Ftq_Pred_Info(implicit p: Parameters) extends XSBundle {
val target = UInt(VAddrBits.W)
val target = Pc()
val cfiIndex = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))
}

Expand Down Expand Up @@ -234,17 +234,17 @@ class FtqToCtrlIO(implicit p: Parameters) extends XSBundle with HasBackendRedire
val pc_mem_wdata = Output(new Ftq_RF_Components)
// newest target
val newest_entry_en = Output(Bool())
val newest_entry_target = Output(UInt(VAddrBits.W))
val newest_entry_target = Output(Pc())
val newest_entry_ptr = Output(new FtqPtr)
}

class FTBEntryGen(implicit p: Parameters) extends XSModule with HasBackendRedirectInfo with HasBPUParameter {
val io = IO(new Bundle {
val start_addr = Input(UInt(VAddrBits.W))
val start_addr = Input(Pc())
val old_entry = Input(new FTBEntry)
val pd = Input(new Ftq_pd_Entry)
val cfiIndex = Flipped(Valid(UInt(log2Ceil(PredictWidth).W)))
val target = Input(UInt(VAddrBits.W))
val target = Input(Pc())
val hit = Input(Bool())
val mispredict_vec = Input(Vec(PredictWidth, Bool()))

Expand Down Expand Up @@ -282,7 +282,7 @@ class FTBEntryGen(implicit p: Parameters) extends XSModule with HasBackendRedire
val cfi_is_jalr = io.cfiIndex.bits === pd.jmpOffset && new_jmp_is_jalr

def carryPos = log2Ceil(PredictWidth) + instOffsetBits
def getLower(pc: UInt) = pc(carryPos - 1, instOffsetBits)
def getLower(pc: Pc) = pc(carryPos - 1, instOffsetBits)
// if not hit, establish a new entry
init_entry.valid := true.B
// tag is left for ftb to assign
Expand Down Expand Up @@ -654,8 +654,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
ftb_entry_mem.io.wdata(0) := io.fromBpu.resp.bits.last_stage_ftb_entry

// multi-write
val update_target = Reg(Vec(FtqSize, UInt(VAddrBits.W))) // could be taken target or fallThrough //TODO: remove this
val newest_entry_target = Reg(UInt(VAddrBits.W))
val update_target = Reg(Vec(FtqSize, Pc())) // could be taken target or fallThrough //TODO: remove this
val newest_entry_target = Reg(Pc())
val newest_entry_target_modified = RegInit(false.B)
val newest_entry_ptr = Reg(new FtqPtr)
val newest_entry_ptr_modified = RegInit(false.B)
Expand Down Expand Up @@ -836,7 +836,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
val toIfuPcBundle = Wire(new Ftq_RF_Components)
val entry_is_to_send = WireInit(entry_fetch_status(ifuPtr.value) === f_to_send)
val entry_ftq_offset = WireInit(cfiIndex_vec(ifuPtr.value))
val entry_next_addr = Wire(UInt(VAddrBits.W))
val entry_next_addr = Wire(Pc())

val pc_mem_ifu_ptr_rdata = VecInit(Seq.fill(copyNum)(RegNext(ftq_pc_mem.io.ifuPtr_rdata)))
val pc_mem_ifu_plus1_rdata = VecInit(Seq.fill(copyNum)(RegNext(ftq_pc_mem.io.ifuPtrPlus1_rdata)))
Expand Down Expand Up @@ -931,7 +931,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
// TODO: remove this
XSError(
io.toIfu.req.valid && diff_entry_next_addr =/= entry_next_addr,
p"\nifu_req_target wrong! ifuPtr: ${ifuPtr}, entry_next_addr: ${Hexadecimal(entry_next_addr)} diff_entry_next_addr: ${Hexadecimal(diff_entry_next_addr)}\n"
p"\nifu_req_target wrong! ifuPtr: ${ifuPtr}, entry_next_addr: ${Hexadecimal(entry_next_addr())} diff_entry_next_addr: ${Hexadecimal(diff_entry_next_addr())}\n"
)

// when fall through is smaller in value than start address, there must be a false hit
Expand Down Expand Up @@ -1164,7 +1164,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
val newest_entry_en: Bool = RegNext(last_cycle_bpu_in || backendRedirect.valid || ifuRedirectToBpu.valid)
io.toBackend.newest_entry_en := RegNext(newest_entry_en)
io.toBackend.newest_entry_ptr := RegEnable(newest_entry_ptr, newest_entry_en)
io.toBackend.newest_entry_target := RegEnable(newest_entry_target, newest_entry_en)
io.toBackend.newest_entry_target := RegEnable(newest_entry_target(), newest_entry_en)

// *********************************************************************
// **************************** wb from exu ****************************
Expand Down Expand Up @@ -1523,7 +1523,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
val ftqBranchTraceDB = ChiselDB.createTable(s"FTQTable$hartId", new FtqDebugBundle)
// Cfi Info
for (i <- 0 until PredictWidth) {
val pc = commit_pc_bundle.startAddr + (i * instBytes).U
val pc = commit_pc_bundle.startAddr() + (i * instBytes).U
val v = commit_state(i) === c_committed
val isBr = commit_pd.brMask(i)
val isJmp = commit_pd.jmpInfo.valid && commit_pd.jmpOffset === i.U
Expand All @@ -1547,8 +1547,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
v && do_commit && isCfi,
p"cfi_update: isBr(${isBr}) pc(${Hexadecimal(pc)}) " +
p"taken(${isTaken}) mispred(${misPred}) cycle($predCycle) hist(${histPtr.value}) " +
p"startAddr(${Hexadecimal(commit_pc_bundle.startAddr)}) AddIntoHist(${addIntoHist}) " +
p"brInEntry(${inFtbEntry}) brIdx(${brIdx}) target(${Hexadecimal(target)})\n"
p"startAddr(${Hexadecimal(commit_pc_bundle.startAddr())}) AddIntoHist(${addIntoHist}) " +
p"brInEntry(${inFtbEntry}) brIdx(${brIdx}) target(${Hexadecimal(target())})\n"
)

val logbundle = Wire(new FtqDebugBundle)
Expand Down Expand Up @@ -1704,7 +1704,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
p"[in] v:${io.fromBpu.resp.valid} r:${io.fromBpu.resp.ready} " +
p"[out] v:${io.toIfu.req.valid} r:${io.toIfu.req.ready}\n"
)
XSDebug(do_commit, p"[deq info] cfiIndex: $commit_cfi, $commit_pc_bundle, target: ${Hexadecimal(commit_target)}\n")
XSDebug(do_commit, p"[deq info] cfiIndex: $commit_cfi, $commit_pc_bundle, target: ${Hexadecimal(commit_target())}\n")

// def ubtbCheck(commit: FtqEntry, predAns: Seq[PredictorAnswer], isWrong: Bool) = {
// commit.valids.zip(commit.pd).zip(predAns).zip(commit.takens).map {
Expand Down

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