Add support for 'logic' net type #14
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coreyeng
approved these changes
Jun 25, 2020
ginty
requested changes
Jul 23, 2020
| @@ -828,15 +830,17 @@ module OrigenVerilog | |||
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| # dimension ::= [ dimension_constant_expression : dimension_constant_expression ] | |||
| rule dimension | |||
| "[" s dimension_constant_expression s ":" s dimension_constant_expression s "]" { | |||
| ("[" s dimension_constant_expression s ":" s dimension_constant_expression s "]" s "[" s dimension_constant_expression s ":" s dimension_constant_expression s "]" / | |||
| "[" s dimension_constant_expression s ":" s dimension_constant_expression s "]") { | |||
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This is converting this rule from defining a single dimension to defining multiple dimensions.
Is the proper update not to change dimension somewhere to dimension+ so that it will take multiple?
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