cpu/sam0_common: flashpage: disable cache while writing

[benpicco]

Contribution description

From errata 2.14.1:

NVM reads could be corrupted when mixing NVM reads with Page Buffer writes.

Workaround

Disable cache lines before writing to the Page Buffer when executing from NVM or reading
data from NVM while writing to the Page Buffer. Cache lines are disabled by writing a one to
CTRLA.CACHEDIS0 and CTRLA.CACHEDIS1.

Testing procedure

I ran examples/suit_update on same54-xpro.
This would previously crash when not disabling the interrupts.

I also tested this on samr34-xpro to ensure no regressions on saml21.

samd21 never needed the disabled interrupts in the first place.

Issues/PRs references

[dylad]

Does this PR also affect SAML1X ?

[fabian18]

You told me about the errata and I would be happy to have the interrupts enabled again.
It does not solve #19928, but we should have this in if you say it fixes something.