As a final-year Electrical & Electronics Engineering student with a Minor in Computer Science, my primary passion lies in the world of computer architecture and RTL design. I am driven by the challenge of designing digital systems from the ground up—from writing Verilog for custom processors to verifying logic on FPGAs. While I enjoy building full-stack applications, my core focus is on the hardware that makes it all possible
- 🔭 I’m currently exploring advanced RTL design for FPGAs and digital verification methodologies.
- 🌱 My core interests are CPU Architecture, SoC Design, and High-Performance Computing.
- ⚡ I believe in a meticulous approach to design, focusing on performance, efficiency, and robust verification.
A selection of projects showcasing my experience from digital logic to full-stack applications.
Fault-Tolerant RISC-V Processor (Verilog)
A fault-tolerant, pipelined RISC-V processor featuring Triple Modular Redundancy (TMR) and SECDED memory protection. A deep-dive into reliable computer architecture, designed for synthesis and verification.
View Repository →MIPS 32-Bit Pipelined CPU (Verilog)
A custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. This project demonstrates core CPU concepts and was verified using Python testbenches.
View Repository →Elucidra - AI-Powered Learning SaaS App (TypeScript)
A modern AI-powered learning platform (SaaS) that lets users interact with intelligent virtual tutors in real time. Demonstrates full-stack development and system integration skills.
View Repository →