Skip to content
View StackedArchitect's full-sized avatar

Block or report StackedArchitect

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
StackedArchitect/README.md

Typing SVG

As a final-year Electrical & Electronics Engineering student with a Minor in Computer Science, my primary passion lies in the world of computer architecture and RTL design. I am driven by the challenge of designing digital systems from the ground up—from writing Verilog for custom processors to verifying logic on FPGAs. While I enjoy building full-stack applications, my core focus is on the hardware that makes it all possible

  • 🔭 I’m currently exploring advanced RTL design for FPGAs and digital verification methodologies.
  • 🌱 My core interests are CPU Architecture, SoC Design, and High-Performance Computing.
  • ⚡ I believe in a meticulous approach to design, focusing on performance, efficiency, and robust verification.


🛠️ My Technical Toolkit

Hardware & Architecture
Verilog Vivado Python C RISC-V

Software & Full-Stack
TypeScript Java React Node.js

Databases, Tools & Platforms
MySQL Git



🏗️ Featured Hardware & Software Projects

A selection of projects showcasing my experience from digital logic to full-stack applications.

Fault-Tolerant RISC-V Processor (Verilog)

A fault-tolerant, pipelined RISC-V processor featuring Triple Modular Redundancy (TMR) and SECDED memory protection. A deep-dive into reliable computer architecture, designed for synthesis and verification.

Verilog Vivado Architecture Fault Tolerance

View Repository →
MIPS 32-Bit Pipelined CPU (Verilog)

A custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. This project demonstrates core CPU concepts and was verified using Python testbenches.

Verilog Python MIPS CPU Design

View Repository →
Elucidra - AI-Powered Learning SaaS App (TypeScript)

A modern AI-powered learning platform (SaaS) that lets users interact with intelligent virtual tutors in real time. Demonstrates full-stack development and system integration skills.

TypeScript React AI/ML SaaS

View Repository →

📊 My GitHub Stats

StackedArchitect's GitHub Stats StackedArchitect's Top Languages



Pinned Loading

  1. MIPS32Bit-Pipelined-CPU MIPS32Bit-Pipelined-CPU Public

    This project is a custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. It demonstrates core CPU concepts and is ideal for learning…

    Verilog

  2. Fault-Tolerant-RISCV Fault-Tolerant-RISCV Public

    A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Des…

    Verilog

  3. SaaS-App SaaS-App Public

    Elucidra is a Software as a System (SAAS) Application, a modern AI-powered learning platform that lets users interact with intelligent virtual tutors in real time. Featuring personalized AI compani…

    TypeScript 1

  4. Chat-Management-and-Moderation-System Chat-Management-and-Moderation-System Public

    A POSIX-compliant chat moderation system where the App spawns Group processes, which manage the user's child processes. The Moderator scans messages for restricted words via substring matching, tra…

    C

  5. Timetable-Builder Timetable-Builder Public

    This is a Timetable Management System built in Java using Swing for the GUI. The application provides role-based access for administrators, teachers, and students to manage academic schedules, cour…

    Java

  6. Job-Recruitment-DBMS Job-Recruitment-DBMS Public

    A LinkedIn-style job recruitment platform with dynamic job listings, candidate matching, and experience-based filtering.

    Hack