Next (#650)

Jenkinsfile

@@ -1,4 +1,4 @@
 @Library('pipeline-library')_
 
-VitisLibPipeline (branch: 'master', libname: 'Vitis_Accel_Examples', run_sw_in_pr: 'true', TARGETS: 'vitis_sw_emu:vitis_hw_emu',
-                  email: '[email protected]', devtest: 'RunDeploy.sh', TOOLVERSION: '2020.1_released')
+VitisLibPipeline (branch: 'next', libname: 'Vitis_Accel_Examples', run_sw_in_pr: 'true', TARGETS: 'vitis_sw_emu:vitis_hw_emu',
+                  email: '[email protected]', devtest: 'RunDeploy.sh', TOOLVERSION: '2020.2_daily_latest')

common/includes/cmdparser/cmdlineparser.h

@@ -20,8 +20,6 @@
 #include <string>
 #include <vector>
 
-using namespace std;
-
 namespace sda {
 namespace utils {
 
@@ -37,31 +35,13 @@ bool is_file(const std::string &name);
 class CmdLineParser {
 public:
   class CmdSwitch {
-  public:
-    CmdSwitch() {}
-    CmdSwitch(const CmdSwitch &rhs) { copyfrom(rhs); }
-
-    void copyfrom(const CmdSwitch &rhs) {
-      this->key = rhs.key;
-      this->shortcut = rhs.shortcut;
-      this->default_value = rhs.default_value;
-      this->value = rhs.value;
-      this->desc = rhs.desc;
-      this->istoggle = rhs.istoggle;
-      this->isvalid = rhs.isvalid;
-    }
-
-    CmdSwitch &operator=(const CmdSwitch &rhs) {
-      this->copyfrom(rhs);
-      return *this;
-    }
 
   public:
-    string key;
-    string shortcut;
-    string default_value;
-    string value;
-    string desc;
+    std::string key;
+    std::string shortcut;
+    std::string default_value;
+    std::string value;
+    std::string desc;
     bool istoggle;
     bool isvalid;
   };
@@ -72,8 +52,9 @@ class CmdLineParser {
   virtual ~CmdLineParser();
 
   bool addSwitch(const CmdSwitch &s);
-  bool addSwitch(const string &name, const string &shortcut, const string &desc,
-                 const string &default_value = "", bool istoggle = false);
+  bool addSwitch(const std::string &name, const std::string &shortcut,
+                 const std::string &desc, const std::string &default_value = "",
+                 bool istoggle = false);
 
   /*!
    * sets default key to be able to read a 2 argumented call
@@ -88,7 +69,7 @@ class CmdLineParser {
   /*!
    * retrieve value using a key
    */
-  string value(const char *key);
+  std::string value(const char *key);
 
   int value_to_int(const char *key);
 
@@ -110,14 +91,14 @@ class CmdLineParser {
    */
   CmdSwitch *getCmdSwitch(const char *key);
 
-  bool token_to_fullkeyname(const string &token, string &fullkey);
+  bool token_to_fullkeyname(const std::string &token, std::string &fullkey);
 
 private:
-  map<string, CmdSwitch *> m_mapKeySwitch;
-  map<string, string> m_mapShortcutKeys;
-  vector<CmdSwitch *> m_vSwitches;
-  string m_strDefaultKey;
-  string m_appname;
+  std::map<std::string, CmdSwitch *> m_mapKeySwitch;
+  std::map<std::string, std::string> m_mapShortcutKeys;
+  std::vector<CmdSwitch *> m_vSwitches;
+  std::string m_strDefaultKey;
+  std::string m_appname;
 };
 
 // bool starts_with(const string& src, const string& sub);

common/platform/u200_qdma/platform.h

@@ -0,0 +1,21 @@
+/**
+* Copyright (C) 2020 Xilinx, Inc
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You may
+* not use this file except in compliance with the License. A copy of the
+* License is located at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+* License for the specific language governing permissions and limitations
+* under the License.
+*/
+
+#define DDR_BANK_CNTS 3
+#define DDR0_BANDWIDTH bandwidth_1
+#define DDR1_BANDWIDTH bandwidth_2
+#define DDR2_BANDWIDTH bandwidth_3
+#define TOTAL_BANK_CNTS 3

common/platform/u200_qdma/platform.json

@@ -0,0 +1,18 @@
+{
+    "meminfo": [
+    {
+        "type": "DDR",
+        "banks": [
+        {
+            "name": "DDR[0]"
+        },
+        {
+            "name": "DDR[1]"
+        },
+        {
+            "name": "DDR[2]"
+        }
+        ]
+    }
+    ]
+}

common/platform/u200_qdma/platform_bandwidth.ini

@@ -0,0 +1,8 @@
+[connectivity]
+sp=bandwidth_1.output:DDR[0]
+sp=bandwidth_1.input:DDR[0]
+sp=bandwidth_2.output:DDR[1]
+sp=bandwidth_2.input:DDR[1]
+sp=bandwidth_3.output:DDR[2]
+sp=bandwidth_3.input:DDR[2]
+nk=bandwidth:3

common/platform/u200_xdma/platform.h

@@ -0,0 +1,22 @@
+/**
+* Copyright (C) 2020 Xilinx, Inc
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You may
+* not use this file except in compliance with the License. A copy of the
+* License is located at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+* License for the specific language governing permissions and limitations
+* under the License.
+*/
+
+#define DDR_BANK_CNTS 4
+#define DDR0_BANDWIDTH bandwidth_1
+#define DDR1_BANDWIDTH bandwidth_2
+#define DDR2_BANDWIDTH bandwidth_3
+#define DDR3_BANDWIDTH bandwidth_4
+#define TOTAL_BANK_CNTS 4

common/platform/u200_xdma/platform.json

@@ -0,0 +1,21 @@
+{
+    "meminfo": [
+    {
+        "type": "DDR",
+        "banks": [
+        {
+            "name": "DDR[0]"
+        },
+        {
+            "name": "DDR[1]"
+        },
+        {
+            "name": "DDR[2]"
+        },
+        {
+            "name": "DDR[3]"
+        }
+        ]
+    }
+    ]
+}

common/platform/u200_xdma/platform_bandwidth.ini

@@ -0,0 +1,10 @@
+[connectivity]
+sp=bandwidth_1.output:DDR[0]
+sp=bandwidth_1.input:DDR[0]
+sp=bandwidth_2.output:DDR[1]
+sp=bandwidth_2.input:DDR[1]
+sp=bandwidth_3.output:DDR[2]
+sp=bandwidth_3.input:DDR[2]
+sp=bandwidth_4.output:DDR[3]
+sp=bandwidth_4.input:DDR[3]
+nk=bandwidth:4

common/platform/u250_gen/platform.h

@@ -0,0 +1,22 @@
+/**
+* Copyright (C) 2020 Xilinx, Inc
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You may
+* not use this file except in compliance with the License. A copy of the
+* License is located at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+* License for the specific language governing permissions and limitations
+* under the License.
+*/
+
+#define DDR_BANK_CNTS 4
+#define DDR0_BANDWIDTH bandwidth_1
+#define DDR1_BANDWIDTH bandwidth_2
+#define DDR2_BANDWIDTH bandwidth_3
+#define DDR3_BANDWIDTH bandwidth_4
+#define TOTAL_BANK_CNTS 4

common/platform/u250_gen/platform.json

@@ -0,0 +1,21 @@
+{
+    "meminfo": [
+    {
+        "type": "DDR",
+        "banks": [
+        {
+            "name": "DDR[0]"
+        },
+        {
+            "name": "DDR[1]"
+        },
+        {
+            "name": "DDR[2]"
+        },
+        {
+            "name": "DDR[3]"
+        }
+        ]
+    }
+    ]
+}

common/platform/u250_gen/platform_bandwidth.ini

@@ -0,0 +1,10 @@
+[connectivity]
+sp=bandwidth_1.output:DDR[0]
+sp=bandwidth_1.input:DDR[0]
+sp=bandwidth_2.output:DDR[1]
+sp=bandwidth_2.input:DDR[1]
+sp=bandwidth_3.output:DDR[2]
+sp=bandwidth_3.input:DDR[2]
+sp=bandwidth_4.output:DDR[3]
+sp=bandwidth_4.input:DDR[3]
+nk=bandwidth:4

common/platform/u250_gen/platform_slavebridge.ini

@@ -0,0 +1,10 @@
+[connectivity]
+sp=slavebridge_1.output:DDR[0]
+sp=slavebridge_1.input:DDR[0]
+sp=slavebridge_2.output:DDR[1]
+sp=slavebridge_2.input:DDR[1]
+sp=slavebridge_3.output:DDR[2]
+sp=slavebridge_3.input:DDR[2]
+sp=slavebridge_4.output:HOST[0]
+sp=slavebridge_4.input:HOST[0]
+nk=slavebridge:4

common/platform/u250_qdma/platform.h

@@ -0,0 +1,21 @@
+/**
+* Copyright (C) 2020 Xilinx, Inc
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You may
+* not use this file except in compliance with the License. A copy of the
+* License is located at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+* License for the specific language governing permissions and limitations
+* under the License.
+*/
+
+#define DDR_BANK_CNTS 3
+#define DDR0_BANDWIDTH bandwidth_1
+#define DDR1_BANDWIDTH bandwidth_2
+#define DDR2_BANDWIDTH bandwidth_3
+#define TOTAL_BANK_CNTS 3

common/platform/u250_qdma/platform.json

@@ -0,0 +1,18 @@
+{
+    "meminfo": [
+    {
+        "type": "DDR",
+        "banks": [
+        {
+            "name": "DDR[0]"
+        },
+        {
+            "name": "DDR[1]"
+        },
+        {
+            "name": "DDR[2]"
+        }
+        ]
+    }
+    ]
+}

common/platform/u250_qdma/platform_bandwidth.ini

@@ -0,0 +1,8 @@
+[connectivity]
+sp=bandwidth_1.output:DDR[0]
+sp=bandwidth_1.input:DDR[0]
+sp=bandwidth_2.output:DDR[1]
+sp=bandwidth_2.input:DDR[1]
+sp=bandwidth_3.output:DDR[2]
+sp=bandwidth_3.input:DDR[2]
+nk=bandwidth:3

common/platform/u250_xdma/platform.h

@@ -0,0 +1,22 @@
+/**
+* Copyright (C) 2020 Xilinx, Inc
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You may
+* not use this file except in compliance with the License. A copy of the
+* License is located at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+* License for the specific language governing permissions and limitations
+* under the License.
+*/
+
+#define DDR_BANK_CNTS 4
+#define DDR0_BANDWIDTH bandwidth_1
+#define DDR1_BANDWIDTH bandwidth_2
+#define DDR2_BANDWIDTH bandwidth_3
+#define DDR3_BANDWIDTH bandwidth_4
+#define TOTAL_BANK_CNTS 4

common/platform/u250_xdma/platform.json

@@ -0,0 +1,21 @@
+{
+    "meminfo": [
+    {
+        "type": "DDR",
+        "banks": [
+        {
+            "name": "DDR[0]"
+        },
+        {
+            "name": "DDR[1]"
+        },
+        {
+            "name": "DDR[2]"
+        },
+        {
+            "name": "DDR[3]"
+        }
+        ]
+    }
+    ]
+}

common/platform/u250_xdma/platform_bandwidth.ini

@@ -0,0 +1,10 @@
+[connectivity]
+sp=bandwidth_1.output:DDR[0]
+sp=bandwidth_1.input:DDR[0]
+sp=bandwidth_2.output:DDR[1]
+sp=bandwidth_2.input:DDR[1]
+sp=bandwidth_3.output:DDR[2]
+sp=bandwidth_3.input:DDR[2]
+sp=bandwidth_4.output:DDR[3]
+sp=bandwidth_4.input:DDR[3]
+nk=bandwidth:4

common/platform/u280/platform.h

@@ -0,0 +1,23 @@
+/**
+* Copyright (C) 2020 Xilinx, Inc
+*
+* Licensed under the Apache License, Version 2.0 (the "License"). You may
+* not use this file except in compliance with the License. A copy of the
+* License is located at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+* License for the specific language governing permissions and limitations
+* under the License.
+*/
+
+#define DDR_BANK_CNTS 2
+#define DDR0_BANDWIDTH bandwidth_1
+#define DDR1_BANDWIDTH bandwidth_2
+#define HBM_BANK_CNTS 2
+#define HBM0_BANDWIDTH bandwidth_3
+#define HBM1_BANDWIDTH bandwidth_4
+#define TOTAL_BANK_CNTS 4