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learning
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Yashas2801/README.md

Hi there 👋 I'm Yashas! 🚀

Shaping the flow of electrons  &&  Sculpting the invisible currents of logic  &&  Weaving reality from the fabric of 1s and 0s

🛠 Skills

  • Advanced Digital Design: Crafting efficient and innovative digital systems.
  • Hardware Description Languages (HDL): Expert in Verilog for designing precise digital logic.
  • Hardware Verification language (HVL) & Methodology: Proficient in SystemVerilog and UVM
  • Neovim | tmux: Vim motions, search and replace, macros, LSP support, formatting, syntax highlighting | Workflow management.

📘 Currently Learning

  • Python: Exploring scripting and automation to enhance workflows and productivity.

🌟 Open-Source Vision

My main interest lies in making VLSI related resources open source. The VLSI industry often operates on a more closed level, which I believe slows down technological advancements in this field. I aspire to be a key contributor to open-source efforts in VLSI, fostering innovation and accessibility for the next generation of engineers.

I love connecting with different people so if you want to say hi, I'll be happy to meet you more! :)

Pinned Loading

  1. UART-Verification-using-UVM UART-Verification-using-UVM Public

    UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.

    Verilog 7 1

  2. Router_1x3_verification_uvm Router_1x3_verification_uvm Public

    A 1x3 router directs incoming data packets from a single input to one of three outputs based on the destination address.

    SystemVerilog 2

  3. Grey_counter_verification_uvm Grey_counter_verification_uvm Public

    Verification of 4 bit grey counter using UVM

    SystemVerilog 1

  4. Ring_counter_verification_uvm Ring_counter_verification_uvm Public

    8-Bit Ring cocunter / Onehot counter Verification (UVM)

    SystemVerilog 2

  5. 100_days_of_python 100_days_of_python Public

    Learning python #100 day challenge

    Python