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Draft Extension: Zfbfmin, Zvfbfmin and Zvfbfwma #115

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Draft Extension: Zfbfmin, Zvfbfmin and Zvfbfwma #115

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@a4lg a4lg commented Aug 3, 2023

@a4lg a4lg added the enhancement New feature or request label Aug 3, 2023
@a4lg a4lg force-pushed the riscv-bfloat16 branch 7 times, most recently from 8e671c4 to ded5bde Compare August 8, 2023 04:11
@a4lg a4lg force-pushed the riscv-bfloat16 branch 3 times, most recently from 44397b9 to 2b34365 Compare August 15, 2023 06:37
@a4lg a4lg force-pushed the riscv-bfloat16 branch 4 times, most recently from 0f4abce to 33a7f9d Compare September 7, 2023 09:35
@a4lg a4lg force-pushed the riscv-bfloat16 branch 2 times, most recently from 1477628 to 2ace9c5 Compare October 19, 2023 03:17
a4lg added 4 commits October 19, 2023 06:58
@a4lg
UNRATIFIED RISC-V: Add 'Zfbfmin' extension
e57f731 
[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zfbfmin' extension, the scalar BF16
conversion extension.  It consists of two new instructions and four
previously 'Zfhmin'-only instructions.

This commit is based on the following specification:
<riscv/riscv-bfloat16@5578e34>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zfbfmin' -> 'F'.
	(riscv_supported_std_z_ext): Add 'Zfbfmin'.
	(riscv_multi_subset_supports): Recategory INSN_CLASS_ZFHMIN to mean
	'Zfhmin' or 'Zfbfmin'.  Add support to INSN_CLASS_ZFBFMIN.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zfbfmin.s: New test.
	* testsuite/gas/riscv/zfbfmin.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S,
	MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zfbfmin'-only instructions.
@a4lg
UNRATIFIED RISC-V: Add 'Zvfbfmin' extension
f7360d5 
[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zvfbfmin' extension, the vector BF16
conversion only extension, consisting of two narrowing / widening conversion
instructions between BF16 and FP32.

This commit is based on the following specification:
<riscv/riscv-bfloat16@5578e34>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implications
	'Zvfbfmin' -> 'Zfbfmin' and 'Zve32f'.
	(riscv_supported_std_z_ext): Add 'Zvfbfmin'.
	(riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFMIN.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvfbfmin.s: New test.
	* testsuite/gas/riscv/zvfbfmin.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W,
	MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZVFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zvfbfmin' instructions.
@a4lg
UNRATIFIED RISC-V: Add 'Zvfbfwma' extension
a780d4f 
[DO NOT MERGE]
Until RISC-V BF16 extensions are frozen/ratified and the final version
number is determined, this patch should not be merged upstream. This
commit uses unratified version 0.8 as in the latest PDF documentation
(instead of possible 1.0 after ratification).

This commit adds support for the 'Zvfbfwma' extension, the vector BF16
multiply then FP32 accumlation extension, consisting of two widening
multiply-accumulate instructions.

This commit is based on the following specification:
<riscv/riscv-bfloat16@5578e34>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zvfbfwma'
	-> 'Zvfbfmin' implication.
	(riscv_supported_std_z_ext): Add 'Zvfbfwma'.
	(riscv_multi_subset_supports): Add support to INSN_CLASS_ZVFBFWMA.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvfbfwma.s: New test.
	* testsuite/gas/riscv/zvfbfwma.d: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF,
	MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV): New.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction class
	INSN_CLASS_ZVFBFWMA.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zvfbfwma' instructions.
@a4lg
RISC-V: Tentative ".bfloat16" assembly support
fa8a3b5 
This commit adds an assembler directive ".bfloat16" to help BFloat16
extensions ('Zfbfmin', 'Zvfbfmin' and 'Zvfbfwma') users.

gas/ChangeLog:

	* config/tc-riscv.c (FLT_CHARS): Add BFloat16 'b' to supported
	floating point formats.
	(riscv_pseudo_table) Add ".bfloat16" directive.
	* testsuite/gas/riscv/bfloat16.s: Copied from
	testsuite/gas/aarch64/bfloat16-directive.s.
	* testsuite/gas/riscv/bfloat16-be.d: New test ported from
	testsuite/gas/aarch64/bfloat16-directive-be.d and float16-be.d.
	* testsuite/gas/riscv/bfloat16-le.d: New test ported from
	testsuite/gas/aarch64/bfloat16-directive-le.d and float16-le.d.
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