[1.3] Fix parallelLoopPatterns for the Intel FPGA SYCL back-end
#2457
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fwyzard
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parallelLoopPatterns for the Intel FPGA SYCL back-endparallelLoopPatterns for the Intel FPGA SYCL back-end
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psychocoderHPC
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Feb 4, 2025
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Extend
parallelLoopPatternsto use 64-bit indices to support more than 2³² elements.Add a dedicated fix for SYCL back-ends, that assume that kernel-related queries (and possibly indices) are limited to
INT_MAX, unless the-fno-sycl-id-queries-fit-in-intcompiler flag is used.Add a
Vecconstructor from aVecwith a compatible type. This seems useful in general, and is required to compileparallelLoopPatternswith these changes.The only difference with respect to #2456 is the use of
std::is_convertible_vinstead ofstd::is_nothrow_convertible_v, which has been introduced in c++20, and a workaround for NVCC 11.3 that does not properly support SFINAE.