Add Arm instructions needed for AES-XTS

[nebeid]

Description of changes:
Added decoding for:

• NOP
• LD1/ST1 post-index register offset and no offset for both 64-bit and 128-bit registers
• LD1/ST1 2 128-bit registers, post-index immediate offset
• LDRB/STRB with (shifted) register index, no shift.

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[aqjune-aws]

The sematest raises a failure at ARM_BASIC_STEP_TAC, specifically EXISTS_NONTRIVIAL_CONV because arm_NOP is unfolded. I think arm_NOP must be unfolded.. instruction.ml will have ARM_OPERATION_CLAUSES that lists the definitions to unfold.
On the other hand, EXISTS_NONTRIVIAL_CONV must print a better error message in this case. :(