fixed visual artifacts, restructured

azzeloof · Dec 8, 2020 · 87bc178 · 87bc178
1 parent 5fbd6e2
commit 87bc178
Show file tree

Hide file tree

Showing 18 changed files with 22 additions and 22 deletions.
diff --git a/apio.ini → gateware/apio.ini b/apio.ini → gateware/apio.ini
diff --git a/clk_divider.v → gateware/clk_divider.v b/clk_divider.v → gateware/clk_divider.v
diff --git a/debounce.v → gateware/debounce.v b/debounce.v → gateware/debounce.v
diff --git a/foodgen.v → gateware/foodgen.v b/foodgen.v → gateware/foodgen.v
@@ -16,12 +16,10 @@ module foodgen(
   output food_loc
 );
 
-  wire food_loc;
+  reg food_loc;
   reg [4:0] food_h;
   reg [4:0] food_v;
 
-  assign food_loc = (hpos > food_h*20) & (hpos < (food_h+1)*20) & (vpos > food_v*20) & (vpos < (food_v+1)*20);
-
   //Pseudo-random number generators
   //https://electronics.stackexchange.com/questions/30521/random-bit-sequence-using-verilog
   reg [4:0] rng0 = 1;
@@ -39,6 +37,7 @@ module foodgen(
       food_h <= rng0;
       food_v <= rng1;
     end
+    food_loc <= (hpos > food_h*20) & (hpos < (food_h+1)*20) & (vpos > food_v*20) & (vpos < (food_v+1)*20);
   end
 
 endmodule
diff --git a/hvsync_generator.v → gateware/hvsync_generator.v b/hvsync_generator.v → gateware/hvsync_generator.v
diff --git a/install_apio.bat → gateware/install_apio.bat b/install_apio.bat → gateware/install_apio.bat
diff --git a/install_apio.sh → gateware/install_apio.sh b/install_apio.sh → gateware/install_apio.sh
diff --git a/makesplash.py → gateware/makesplash.py b/makesplash.py → gateware/makesplash.py
diff --git a/pins.pcf → gateware/pins.pcf b/pins.pcf → gateware/pins.pcf
@@ -39,11 +39,11 @@
 
 # Left side of board
 set_io --warn-no-port --warn-no-port PIN_1 A2
-set_io --warn-no-port -pullup yes PIN_2 A1
-set_io --warn-no-port -pullup yes PIN_3 B1
+set_io --warn-no-port PIN_2 A1
+set_io --warn-no-port PIN_3 B1
 set_io --warn-no-port PIN_4 C2
 set_io --warn-no-port PIN_5 C1
-set_io --warn-no-port -pullup yes PIN_6 D2
+set_io --warn-no-port PIN_6 D2
 set_io --warn-no-port PIN_7 D1
 set_io --warn-no-port PIN_8 E2
 set_io --warn-no-port PIN_9 E1
@@ -63,7 +63,7 @@ set_io --warn-no-port PIN_20 A8
 set_io --warn-no-port PIN_21 B7
 set_io --warn-no-port PIN_22 A7
 set_io --warn-no-port PIN_23 B6
-set_io --warn-no-port -pullup yes PIN_24 A6
+set_io --warn-no-port PIN_24 A6
 
 # SPI flash interface on bottom of board
 set_io --warn-no-port SPI_SS F7

diff --git a/snek.v → gateware/snek.v b/snek.v → gateware/snek.v
@@ -137,11 +137,10 @@ module snek(
 
   // I think we're running at 640x480
   // Let's use a grid 32x24 (x20 factor)
-
-  // Connect all of the graphics wires
-  wire r = display_on & ((splash_r & ~gamestate) | (gamestate & ~(snek_loc)));
-  wire g = display_on & ((splash_g & ~gamestate) | (gamestate & ~(food_loc & ~deadsnek)));
-  wire b = display_on & ((splash_b & ~gamestate) | (gamestate & ~(snek_loc ^ (food_loc & ~deadsnek))));
+
+  reg r;
+  reg g;
+  reg b;
 
   assign rgb = {r, g, b};
 
@@ -184,6 +183,10 @@ module snek(
     if (food_v > 23) begin
       new_food_flag <= 1;
     end
+  r <= display_on & ((splash_r & ~gamestate) | (gamestate & ~(snek_loc)));
+  g <= display_on & ((splash_g & ~gamestate) | (gamestate & ~(food_loc & ~deadsnek)));
+  b <= display_on & ((splash_b & ~gamestate) | (gamestate & ~(snek_loc ^ (food_loc & ~deadsnek))));
   end
+
 
 endmodule
diff --git a/snekgen.v → gateware/snekgen.v b/snekgen.v → gateware/snekgen.v
@@ -25,6 +25,7 @@ module snekgen(
 
   genvar j; // index for generate-block for loops
   reg [11:0] i; // index for initial/always for loops
+  reg [11:0] k;
 
   reg [5:0] body_h [maxlen-1:0];
   reg [5:0] body_v [maxlen-1:0];
@@ -47,17 +48,10 @@ module snekgen(
   assign head_v = body_v[0];
 
   // Each bit corresponds to one segment of the snek body
-  wire [maxlen-1:0] snec_locs; // Bits HIGH when hpos and vpos intersect with the segment location
+  //wire [maxlen-1:0] snek_locs; // Bits HIGH when hpos and vpos intersect with the segment location
+  reg [maxlen-1:0] snek_locs;
+  reg snek_loc;
 
-  generate
-  for (j=0; j<maxlen; j=j+1) begin
-    assign snec_locs[j] = (hpos > body_h[j]*20) & (hpos < (body_h[j]+1)*20) & (vpos > body_v[j]*20) & (vpos < (body_v[j]+1)*20);
-  end
-  endgenerate
-
-  wire snek_loc;
-  assign snek_loc = |snec_locs; // OR all of the locations togethor to be displayed
-
   reg dead;
   reg do_grow;
   reg did_grow;
@@ -69,6 +63,10 @@ module snekgen(
     if (did_grow) begin
       do_grow <= 0;
     end
+    for (k=0; k<maxlen; k=k+1) begin
+      snek_locs[k] <= (hpos > body_h[k]*20) & (hpos < (body_h[k]+1)*20) & (vpos > body_v[k]*20) & (vpos < (body_v[k]+1)*20);
+    end
+    snek_loc = |snek_locs;
   end
 
   always @(posedge frame_clk) begin

diff --git a/splash-border.bin → gateware/splash-border.bin b/splash-border.bin → gateware/splash-border.bin
diff --git a/splash-checker.bin → gateware/splash-checker.bin b/splash-checker.bin → gateware/splash-checker.bin
diff --git a/splash.bin → gateware/splash.bin b/splash.bin → gateware/splash.bin
diff --git a/splash.png → gateware/splash.png b/splash.png → gateware/splash.png
diff --git a/splash.v → gateware/splash.v b/splash.v → gateware/splash.v
diff --git a/splash_str.v → gateware/splash_str.v b/splash_str.v → gateware/splash_str.v
diff --git a/top.v → gateware/top.v b/top.v → gateware/top.v