| SWCLK | SWDIO | TX1 | RX1 | TX2 | RX2 | TX3 | RX3 | TX4 | RX4 |
|---|---|---|---|---|---|---|---|---|---|
| PA14 | PA13 | PA9 | PA10 | PA2 | PA3 | PB10 | PB11 | PC10 | PC11 |
| TX5 | RX5 | TX6 | RX6 | TX7 | RX7 | TX8 | RX8 |
|---|---|---|---|---|---|---|---|
| PC12 | PD2 | PC0 | PC1 | PC2 | PC3 | PC4 | PC5 |
Pin Alternate Functions [ALL] [ADC] [I2C] [SPI] [SYS] [TIM] [UART/USART] [USB]
- https://www.wch-ic.com/products/CH32V303.html
- https://www.wch-ic.com/products/CH32V307.html
- https://www.wch.cn/products/CH32V303.html
- https://www.wch.cn/products/CH32V307.html
| TSSOP20 | QFN28 | LQFP48 | LQFP64 | QFN68 | LQFP100 | Pin name | Pin type | I/O structure | Main function(after reset) | Note |
|---|---|---|---|---|---|---|---|---|---|---|
| - | - | 10 | 14 | 14 | 23 | PA0-WKUP | I/O/A | - | PA0 | |
| 2 | 7 | 11 | 15 | 15 | 24 | PA1 | I/O/A | - | PA1 | |
| - | - | 12 | 16 | 16 | 25 | PA2 | I/O/A | - | PA2 | TX2 |
| - | - | 13 | 17 | 19 | 26 | PA3 | I/O/A | - | PA3 | RX2 |
| - | 7 | 14 | 20 | 20 | 29 | PA4 | I/O/A | - | PA4 | |
| 2 | 8 | 15 | 21 | 21 | 30 | PA5 | I/O/A | - | PA5 | |
| - | 9 | 16 | 22 | 22 | 31 | PA6 | I/O/A | - | PA6 | |
| - | 10 | 17 | 23 | 23 | 32 | PA7 | I/O/A | - | PA7 | |
| 18 | 29 | 41 | 43 | 67 | PA8 | I/O | FT | PA8 | ||
| 13 | - | 30 | 42 | 44 | 68 | PA9 | I/O | FT | PA9 | TX1 |
| - | - | 31 | 43 | 45 | 69 | PA10 | I/O | FT | PA10 | RX1 |
| - | 32 | 44 | 46 | 70 | PA11 | I/O/A | FT | PA11 | ||
| - | 33 | 45 | 47 | 71 | PA12 | I/O/A | FT | PA12 | ||
| 13 | 19 | 34 | 46 | 48 | 72 | PA13 | I/O | FT | SWDIO | SWDIO |
| 15 | 22 | 37 | 49 | 52 | 76 | PA14 | I/O | FT | SWCLK | SWCLK |
| - | - | 38 | 50 | 53 | 77 | PA15 | I/O | FT | PA15 | |
| - | - | 18 | 26 | 26 | 35 | PB0 | I/O/A | - | PB0 | |
| - | - | 19 | 27 | 27 | 36 | PB1 | I/O/A | - | PB1 | |
| - | - | 20 | 28 | 28 | 37 | PB2 | I/O | FT | PB2/BOOT1 | |
| - | - | 39 | 55 | 58 | 89 | PB3 | I/O | FT | PB3 | |
| - | - | 40 | 56 | 59 | 90 | PB4 | I/O | FT | PB4 | |
| - | - | 41 | 57 | 60 | 91 | PB5 | I/O | FT | PB5 | |
| 16 | 27 | 42 | 58 | 61 | 92 | PB6 | I/O | FT | PB6 | |
| 17 | 28 | 43 | 59 | 62 | 93 | PB7 | I/O | FT | PB7 | |
| - | - | 45 | 61 | 64 | 95 | PB8 | I/O/A | FT | PB8 | |
| - | - | 46 | 62 | 65 | 96 | PB9 | I/O/A | FT | PB9 | |
| 3 | 11 | 21 | 29 | 29 | 47 | PB10 | I/O/A | FT | PB10 | TX3 |
| 4 | 12 | 22 | 30 | 30 | 48 | PB11 | I/O/A | FT | PB11 | RX3 |
| 5 | 13 | 25 | 33 | 35 | 51 | PB12 | I/O/A | FT | PB12 | |
| 6 | 14 | 26 | 34 | 36 | 52 | PB13 | I/O/A | FT | PB13 | |
| 7 | 15 | 27 | 35 | 37 | 53 | PB14 | I/O/A | FT | PB14 | |
| 8 | 16 | 28 | 36 | 38 | 54 | PB15 | I/O/A | FT | PB15 | |
| - | - | - | 8 | 8 | 15 | PC0 | I/O/A | - | PC0 | TX6 |
| - | - | - | 9 | 9 | 16 | PC1 | I/O/A | - | PC1 | RX6 |
| - | 4 | - | 10 | 10 | 17 | PC2 | I/O/A | - | PC2 | TX7 |
| - | 5 | - | 11 | 11 | 18 | PC3 | I/O/A | - | PC3 | RX7 |
| - | - | - | 24 | 24 | 33 | PC4 | I/O/A | - | PC4 | TX8 |
| - | - | - | 25 | 25 | 34 | PC5 | I/O/A | - | PC5 | RX8 |
| 9 | - | - | 37 | 39 | 63 | PC6 | I/O | FT | PC6 | |
| 10 | - | - | 38 | 40 | 64 | PC7 | I/O | FT | PC7 | |
| 11 | 17 | - | 39 | 41 | 65 | PC8 | I/O | FT | PC8 | |
| 12 | 18 | - | 40 | 42 | 66 | PC9 | I/O | FT | PC9 | |
| - | 23 | - | 51 | 54 | 78 | PC10 | I/O | FT | PC10 | TX4 |
| - | 24 | - | 52 | 55 | 79 | PC11 | I/O | FT | PC11 | RX4 |
| - | 25 | - | 53 | 56 | 80 | PC12 | I/O | FT | PC12 | TX5 |
| - | - | 2 | 2 | 2 | 7 | PC13-TAMPER RTC | I/O | - | PC13 | |
| - | - | 3 | 3 | 3 | 8 | PC14-OSC32_IN | I/O/A | - | PC14 | |
| - | - | 4 | 4 | 4 | 9 | PC15-OSC32_OUT | I/O/A | - | PC15 | |
| - | 1 | - | - | - | 81 | PD0 | I/O/A | FT | PD0 | |
| - | 2 | - | - | - | 82 | PD1 | I/O/A | FT | PD1 | |
| - | 26 | - | 54 | 57 | 83 | PD2 | I/O | FT | PD2 | RX5 |
| - | - | - | - | - | 84 | PD3 | I/O | FT | PD3 | |
| - | - | - | - | - | 85 | PD4 | I/O | FT | PD4 | |
| - | - | - | - | - | 86 | PD5 | I/O | FT | PD5 | |
| - | - | - | - | - | 87 | PD6 | I/O | FT | PD6 | |
| - | - | - | - | - | 88 | PD7 | I/O | FT | PD7 | |
| - | - | - | - | 33 | 55 | PD8 | I/O | FT | PD8 | |
| - | - | - | - | 34 | 56 | PD9 | I/O | FT | PD9 | |
| - | - | - | - | - | 57 | PD10 | I/O | FT | PD10 | |
| - | - | - | - | - | 58 | PD11 | I/O | FT | PD11 | |
| - | - | - | - | - | 59 | PD12 | I/O | FT | PD12 | |
| - | - | - | - | - | 60 | PD13 | I/O | FT | PD13 | |
| - | - | - | - | - | 61 | PD14 | I/O | FT | PD14 | |
| - | - | - | - | - | 62 | PD15 | I/O | FT | PD15 | |
| - | - | - | - | 66 | 97 | PE0 | I/O | FT | PE0 | |
| - | - | - | - | - | 98 | PE1 | I/O | FT | PE1 | |
| - | - | - | - | - | 1 | PE2 | I/O | FT | PE2 | |
| - | - | - | - | - | 2 | PE3 | I/O | FT | PE3 | |
| - | - | - | - | - | 3 | PE4 | I/O | FT | PE4 | |
| - | - | - | - | - | 4 | PE5 | I/O | FT | PE5 | |
| - | - | - | - | - | 5 | PE6 | I/O | FT | PE6 | |
| - | - | - | - | - | 38 | PE7 | I/O/A | FT | PE7 | |
| - | - | - | - | - | 39 | PE8 | I/O/A | FT | PE8 | |
| - | - | - | - | - | 40 | PE9 | I/O | FT | PE9 | |
| - | - | - | - | - | 41 | PE10 | I/O | FT | PE10 | |
| - | - | - | - | - | 42 | PE11 | I/O | FT | PE11 | |
| - | - | - | - | - | 43 | PE12 | I/O | FT | PE12 | |
| - | - | - | - | - | 44 | PE13 | I/O | FT | PE13 | |
| - | - | - | - | - | 45 | PE14 | I/O/A | FT | PE14 | |
| - | - | - | - | - | 46 | PE15 | I/O/A | FT | PE15 |
-
SDIO_D0 and SDIO_D1 are mapped to PC8 and PC9 by default. only for products with the penultimate digit of the lot number greater than 1, the default mapping of SDIO_D0 and SDIO_D1 is automatically changed to PB14 and PB15 when bit[14]ETHMACEN=1 and bit[10]SDIOEN=1 in register RCC_AHBPCENR.
-
DVP_D5 is mapped to PB6 by default. only for products with the penultimate digit of the lot number greater than 1, when bit[13]DVPEN=1 and bit[11]USBHSEN=1 of register RCC_AHBPCENR and bit[2]RB_UC_RST_SIE=0 of R8_USB_CTRL, the default mapping for DVP_D5 is changed to PB3 automatically.
-
FSMC_NADV default maps to PB7. only for products with the penultimate digit of the lot number greater than 1, when register RCC_AHBPCENR's bit[8]FSMCEN=1 and bit[11]USBHSEN=1 and R8_USB_CTRL's bit[2]RB_UC_RST_SIE=0, the default FSMC_NADV mapping is automatically changed to PD2.
-
I2S3_SD is mapped to PB5 by default. only for products with the penultimate digit of the lot number greater than 2. The I2S3_SD default mapping is automatically changed to PA9 if both 10M Ethernet and I2S3 functionality are used.
-
I2S3_MCK is mapped to PC7 by default. only for products with the penultimate digit of the lot number greater than 2. The I2S3_MCK default mapping is automatically changed to PA8 if both 10M Ethernet and I2S3 functions are used.
-
SPI3_MOSI is mapped to PB5 by default, only for the product with the penultimate fifth digit of the lot number being 2. When Ethernet is used, the I2S3 default pin function is unavailable, and the chip select signal of the SPI3 default pin is unavailable, and the SPI3_MOSI default mapping is automatically changed to PA15 at this time.
