Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Option to place _begin_ keyword on a separate line #2318

Open
BrianLChen opened this issue Jan 4, 2025 · 0 comments
Open

Option to place _begin_ keyword on a separate line #2318

BrianLChen opened this issue Jan 4, 2025 · 0 comments
Labels
formatter Verilog code formatter issues

Comments

@BrianLChen
Copy link

Hi,

I a question about configure the formatter behaviour. I would like to know if there are any options to put begin keyword on a separate line.

Current behaviour

always_comb begin
   // some code
end

Expected behaviour

always_comb 
begin
   // some code
end

Is there any existing configuration option in verible to achieve this formatting style?
If not, which part of the code I should look at if I want to modify the source code to achieve behavior?

Best regards,
Brian.

@BrianLChen BrianLChen added the formatter Verilog code formatter issues label Jan 4, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
formatter Verilog code formatter issues
Projects
None yet
Development

No branches or pull requests

1 participant