[lexcer/parser] Empty content in SV if {} constraint block not supported

[kaiyushen]

Describe the bug

It looks like currently inside system verilog constraint, we don't support empty content inside if {} block

To Reproduce

class my_try_class extends uvm_object;

  rand bit some_bit;
  rand bit some_bit_2;

  `uvm_object_utils(my_try_class)

  constraint my_con_c {
    if (some_bit) {
      // after commenting out below line will trigger error
      // some_bit_2 == 1;
    }   
  }

endclass : my_try_class```

Include any options used.

**Actual behavior:**

lexer/parse error at line of "if (some_bit) {"

**Expected behavior**

Code should complain about lexer/parser error