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9 changes: 9 additions & 0 deletions regression/verilog/SVA/property_and1.desc
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KNOWNBUG
property_and1.sv
--bdd
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
This is rejected with a typechecking error.
9 changes: 9 additions & 0 deletions regression/verilog/SVA/property_and1.sv
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module main;

property P1;
1
endproperty

assert property (P1 and P1);

endmodule
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