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atmel_start_config.atstart
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atmel_start_config.atstart
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format_version: '2'
name: My Project
versions:
api: '1.0'
backend: 1.7.279
commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7
content: unknown
content_pack_name: unknown
format: '2'
frontend: 1.7.279
packs_version_avr8: 1.0.1401
packs_version_qtouch: unknown
packs_version_sam: 1.0.1373
version_backend: 1.7.279
version_frontend: ''
board:
identifier: CustomBoard
device: SAMC21E18A-AN
details: null
application: null
middlewares: {}
drivers:
ADC_0:
user_label: ADC_0
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
functionality: ADC
api: HAL:Driver:ADC_Sync
configuration:
adc_advanced_settings: true
adc_arch_adjres: 0
adc_arch_corren: false
adc_arch_dbgrun: false
adc_arch_dualsel: BOTH
adc_arch_event_settings: false
adc_arch_flushei: false
adc_arch_flushinv: false
adc_arch_gaincorr: 0
adc_arch_leftadj: false
adc_arch_offcomp: true
adc_arch_offsetcorr: 0
adc_arch_ondemand: false
adc_arch_r2r: true
adc_arch_refcomp: false
adc_arch_resrdyeo: false
adc_arch_runstdby: false
adc_arch_samplen: 0
adc_arch_samplenum: 1 sample
adc_arch_seqen: 0
adc_arch_slaveen: false
adc_arch_startei: false
adc_arch_startinv: false
adc_arch_winlt: 0
adc_arch_winmode: No window mode
adc_arch_winmoneo: false
adc_arch_winut: 0
adc_differential_mode: false
adc_freerunning_mode: false
adc_pinmux_negative: ADC AIN5 pin
adc_pinmux_positive: ADC AIN0 pin
adc_prescaler: Peripheral clock divided by 2
adc_reference: External reference A
adc_resolution: 12-bit
optional_signals:
- identifier: ADC_0:AIN/0
pad: PA02
mode: Enabled
configuration: null
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::optional_signal_definition::ADC0.AIN.0
name: ADC0/AIN/0
label: AIN/0
- identifier: ADC_0:AIN/5
pad: PA05
mode: Enabled
configuration: null
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::optional_signal_definition::ADC0.AIN.5
name: ADC0/AIN/5
label: AIN/5
- identifier: ADC_0:VREFP
pad: PA03
mode: Enabled
configuration: null
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::optional_signal_definition::ADC0.VREFP
name: ADC0/VREFP
label: VREFP
variant: null
clocks:
domain_group:
nodes:
- name: ADC
input: Generic clock generator 0
external: false
external_frequency: 0
configuration:
adc_gclk_selection: Generic clock generator 0
DMAC:
user_label: DMAC
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
functionality: System
api: HAL:HPL:DMAC
configuration:
dmac_beatsize_0: 8-bit bus transfer
dmac_beatsize_1: 8-bit bus transfer
dmac_beatsize_10: 8-bit bus transfer
dmac_beatsize_11: 8-bit bus transfer
dmac_beatsize_12: 8-bit bus transfer
dmac_beatsize_13: 8-bit bus transfer
dmac_beatsize_14: 8-bit bus transfer
dmac_beatsize_15: 8-bit bus transfer
dmac_beatsize_2: 8-bit bus transfer
dmac_beatsize_3: 8-bit bus transfer
dmac_beatsize_4: 8-bit bus transfer
dmac_beatsize_5: 8-bit bus transfer
dmac_beatsize_6: 8-bit bus transfer
dmac_beatsize_7: 8-bit bus transfer
dmac_beatsize_8: 8-bit bus transfer
dmac_beatsize_9: 8-bit bus transfer
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_10: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_11: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_12: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_13: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_14: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_15: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_2: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_4: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_5: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_6: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_7: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_8: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
the transaction
dmac_channel_0_settings: false
dmac_channel_10_settings: false
dmac_channel_11_settings: false
dmac_channel_12_settings: false
dmac_channel_13_settings: false
dmac_channel_14_settings: false
dmac_channel_15_settings: false
dmac_channel_1_settings: false
dmac_channel_2_settings: false
dmac_channel_3_settings: false
dmac_channel_4_settings: false
dmac_channel_5_settings: false
dmac_channel_6_settings: false
dmac_channel_7_settings: false
dmac_channel_8_settings: false
dmac_channel_9_settings: false
dmac_dbgrun: false
dmac_dqos: Background (no sensitive operation)
dmac_dstinc_0: false
dmac_dstinc_1: false
dmac_dstinc_10: false
dmac_dstinc_11: false
dmac_dstinc_12: false
dmac_dstinc_13: false
dmac_dstinc_14: false
dmac_dstinc_15: false
dmac_dstinc_2: false
dmac_dstinc_3: false
dmac_dstinc_4: false
dmac_dstinc_5: false
dmac_dstinc_6: false
dmac_dstinc_7: false
dmac_dstinc_8: false
dmac_dstinc_9: false
dmac_enable: false
dmac_enable_0: false
dmac_enable_1: false
dmac_enable_10: false
dmac_enable_11: false
dmac_enable_12: false
dmac_enable_13: false
dmac_enable_14: false
dmac_enable_15: false
dmac_enable_2: false
dmac_enable_3: false
dmac_enable_4: false
dmac_enable_5: false
dmac_enable_6: false
dmac_enable_7: false
dmac_enable_8: false
dmac_enable_9: false
dmac_evact_0: No action
dmac_evact_1: No action
dmac_evact_10: No action
dmac_evact_11: No action
dmac_evact_12: No action
dmac_evact_13: No action
dmac_evact_14: No action
dmac_evact_15: No action
dmac_evact_2: No action
dmac_evact_3: No action
dmac_evact_4: No action
dmac_evact_5: No action
dmac_evact_6: No action
dmac_evact_7: No action
dmac_evact_8: No action
dmac_evact_9: No action
dmac_evie_0: false
dmac_evie_1: false
dmac_evie_10: false
dmac_evie_11: false
dmac_evie_12: false
dmac_evie_13: false
dmac_evie_14: false
dmac_evie_15: false
dmac_evie_2: false
dmac_evie_3: false
dmac_evie_4: false
dmac_evie_5: false
dmac_evie_6: false
dmac_evie_7: false
dmac_evie_8: false
dmac_evie_9: false
dmac_evoe_0: false
dmac_evoe_1: false
dmac_evoe_10: false
dmac_evoe_11: false
dmac_evoe_12: false
dmac_evoe_13: false
dmac_evoe_14: false
dmac_evoe_15: false
dmac_evoe_2: false
dmac_evoe_3: false
dmac_evoe_4: false
dmac_evoe_5: false
dmac_evoe_6: false
dmac_evoe_7: false
dmac_evoe_8: false
dmac_evoe_9: false
dmac_evosel_0: Event generation disabled
dmac_evosel_1: Event generation disabled
dmac_evosel_10: Event generation disabled
dmac_evosel_11: Event generation disabled
dmac_evosel_12: Event generation disabled
dmac_evosel_13: Event generation disabled
dmac_evosel_14: Event generation disabled
dmac_evosel_15: Event generation disabled
dmac_evosel_2: Event generation disabled
dmac_evosel_3: Event generation disabled
dmac_evosel_4: Event generation disabled
dmac_evosel_5: Event generation disabled
dmac_evosel_6: Event generation disabled
dmac_evosel_7: Event generation disabled
dmac_evosel_8: Event generation disabled
dmac_evosel_9: Event generation disabled
dmac_fqos: Background (no sensitive operation)
dmac_lvl_0: Channel priority 0
dmac_lvl_1: Channel priority 0
dmac_lvl_10: Channel priority 0
dmac_lvl_11: Channel priority 0
dmac_lvl_12: Channel priority 0
dmac_lvl_13: Channel priority 0
dmac_lvl_14: Channel priority 0
dmac_lvl_15: Channel priority 0
dmac_lvl_2: Channel priority 0
dmac_lvl_3: Channel priority 0
dmac_lvl_4: Channel priority 0
dmac_lvl_5: Channel priority 0
dmac_lvl_6: Channel priority 0
dmac_lvl_7: Channel priority 0
dmac_lvl_8: Channel priority 0
dmac_lvl_9: Channel priority 0
dmac_lvlen0: false
dmac_lvlen1: false
dmac_lvlen2: false
dmac_lvlen3: false
dmac_lvlpri0: 0
dmac_lvlpri1: 0
dmac_lvlpri2: 0
dmac_lvlpri3: 0
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
dmac_runstdby_0: false
dmac_runstdby_1: false
dmac_runstdby_10: false
dmac_runstdby_11: false
dmac_runstdby_12: false
dmac_runstdby_13: false
dmac_runstdby_14: false
dmac_runstdby_15: false
dmac_runstdby_2: false
dmac_runstdby_3: false
dmac_runstdby_4: false
dmac_runstdby_5: false
dmac_runstdby_6: false
dmac_runstdby_7: false
dmac_runstdby_8: false
dmac_runstdby_9: false
dmac_srcinc_0: false
dmac_srcinc_1: false
dmac_srcinc_10: false
dmac_srcinc_11: false
dmac_srcinc_12: false
dmac_srcinc_13: false
dmac_srcinc_14: false
dmac_srcinc_15: false
dmac_srcinc_2: false
dmac_srcinc_3: false
dmac_srcinc_4: false
dmac_srcinc_5: false
dmac_srcinc_6: false
dmac_srcinc_7: false
dmac_srcinc_8: false
dmac_srcinc_9: false
dmac_stepsel_0: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the destination address
dmac_stepsel_10: Step size settings apply to the destination address
dmac_stepsel_11: Step size settings apply to the destination address
dmac_stepsel_12: Step size settings apply to the destination address
dmac_stepsel_13: Step size settings apply to the destination address
dmac_stepsel_14: Step size settings apply to the destination address
dmac_stepsel_15: Step size settings apply to the destination address
dmac_stepsel_2: Step size settings apply to the destination address
dmac_stepsel_3: Step size settings apply to the destination address
dmac_stepsel_4: Step size settings apply to the destination address
dmac_stepsel_5: Step size settings apply to the destination address
dmac_stepsel_6: Step size settings apply to the destination address
dmac_stepsel_7: Step size settings apply to the destination address
dmac_stepsel_8: Step size settings apply to the destination address
dmac_stepsel_9: Step size settings apply to the destination address
dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: Only software/event triggers
dmac_trifsrc_1: Only software/event triggers
dmac_trifsrc_10: Only software/event triggers
dmac_trifsrc_11: Only software/event triggers
dmac_trifsrc_12: Only software/event triggers
dmac_trifsrc_13: Only software/event triggers
dmac_trifsrc_14: Only software/event triggers
dmac_trifsrc_15: Only software/event triggers
dmac_trifsrc_2: Only software/event triggers
dmac_trifsrc_3: Only software/event triggers
dmac_trifsrc_4: Only software/event triggers
dmac_trifsrc_5: Only software/event triggers
dmac_trifsrc_6: Only software/event triggers
dmac_trifsrc_7: Only software/event triggers
dmac_trifsrc_8: Only software/event triggers
dmac_trifsrc_9: Only software/event triggers
dmac_trigact_0: One trigger required for each block transfer
dmac_trigact_1: One trigger required for each block transfer
dmac_trigact_10: One trigger required for each block transfer
dmac_trigact_11: One trigger required for each block transfer
dmac_trigact_12: One trigger required for each block transfer
dmac_trigact_13: One trigger required for each block transfer
dmac_trigact_14: One trigger required for each block transfer
dmac_trigact_15: One trigger required for each block transfer
dmac_trigact_2: One trigger required for each block transfer
dmac_trigact_3: One trigger required for each block transfer
dmac_trigact_4: One trigger required for each block transfer
dmac_trigact_5: One trigger required for each block transfer
dmac_trigact_6: One trigger required for each block transfer
dmac_trigact_7: One trigger required for each block transfer
dmac_trigact_8: One trigger required for each block transfer
dmac_trigact_9: One trigger required for each block transfer
dmac_wrbqos: Background (no sensitive operation)
optional_signals: []
variant: null
clocks:
domain_group: null
GCLK:
user_label: GCLK
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
functionality: System
api: HAL:HPL:GCLK
configuration:
enable_gclk_gen_0: true
enable_gclk_gen_0__externalclock: 1000000
enable_gclk_gen_1: false
enable_gclk_gen_1__externalclock: 1000000
enable_gclk_gen_2: false
enable_gclk_gen_2__externalclock: 1000000
enable_gclk_gen_3: false
enable_gclk_gen_3__externalclock: 1000000
enable_gclk_gen_4: false
enable_gclk_gen_4__externalclock: 1000000
enable_gclk_gen_5: false
enable_gclk_gen_5__externalclock: 1000000
enable_gclk_gen_6: false
enable_gclk_gen_6__externalclock: 1000000
enable_gclk_gen_7: false
enable_gclk_gen_7__externalclock: 1000000
gclk_arch_gen_0_enable: true
gclk_arch_gen_0_idc: false
gclk_arch_gen_0_oe: false
gclk_arch_gen_0_oov: false
gclk_arch_gen_0_runstdby: false
gclk_arch_gen_1_enable: false
gclk_arch_gen_1_idc: false
gclk_arch_gen_1_oe: false
gclk_arch_gen_1_oov: false
gclk_arch_gen_1_runstdby: false
gclk_arch_gen_2_enable: false
gclk_arch_gen_2_idc: false
gclk_arch_gen_2_oe: false
gclk_arch_gen_2_oov: false
gclk_arch_gen_2_runstdby: false
gclk_arch_gen_3_enable: false
gclk_arch_gen_3_idc: false
gclk_arch_gen_3_oe: false
gclk_arch_gen_3_oov: false
gclk_arch_gen_3_runstdby: false
gclk_arch_gen_4_enable: false
gclk_arch_gen_4_idc: false
gclk_arch_gen_4_oe: false
gclk_arch_gen_4_oov: false
gclk_arch_gen_4_runstdby: false
gclk_arch_gen_5_enable: false
gclk_arch_gen_5_idc: false
gclk_arch_gen_5_oe: false
gclk_arch_gen_5_oov: false
gclk_arch_gen_5_runstdby: false
gclk_arch_gen_6_enable: false
gclk_arch_gen_6_idc: false
gclk_arch_gen_6_oe: false
gclk_arch_gen_6_oov: false
gclk_arch_gen_6_runstdby: false
gclk_arch_gen_7_enable: false
gclk_arch_gen_7_idc: false
gclk_arch_gen_7_oe: false
gclk_arch_gen_7_oov: false
gclk_arch_gen_7_runstdby: false
gclk_gen_0_div: 1
gclk_gen_0_div_sel: false
gclk_gen_0_oscillator: 48MHz Internal Oscillator (OSC48M)
gclk_gen_1_div: 1
gclk_gen_1_div_sel: false
gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_2_div: 1
gclk_gen_2_div_sel: false
gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_3_div: 1
gclk_gen_3_div_sel: false
gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_4_div: 1
gclk_gen_4_div_sel: false
gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_5_div: 1
gclk_gen_5_div_sel: false
gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_6_div: 1
gclk_gen_6_div_sel: false
gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_7_div: 1
gclk_gen_7_div_sel: false
gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
optional_signals: []
variant: null
clocks:
domain_group: null
MCLK:
user_label: MCLK
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
functionality: System
api: HAL:HPL:MCLK
configuration:
cpu_clock_source: Generic clock generator 0
cpu_div: '1'
enable_cpu_clock: true
nvm_wait_states: '0'
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: CPU
input: CPU
external: false
external_frequency: 0
configuration: {}
OSC32KCTRL:
user_label: OSC32KCTRL
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
functionality: System
api: HAL:HPL:OSC32KCTRL
configuration:
enable_osc32k: false
enable_osculp32k: true
enable_rtc_source: false
enable_xosc32k: false
osc32k_arch_calib: 0
osc32k_arch_calib_enable: false
osc32k_arch_en1k: false
osc32k_arch_en32k: false
osc32k_arch_enable: false
osc32k_arch_ondemand: false
osc32k_arch_runstdby: false
osc32k_arch_startup: 92us
osculp32k_calib: 0
osculp32k_calib_enable: false
rtc_1khz_selection: false
rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
xosc32k_arch_cfden: false
xosc32k_arch_cfdeo: false
xosc32k_arch_en1k: false
xosc32k_arch_en32k: false
xosc32k_arch_enable: false
xosc32k_arch_ondemand: true
xosc32k_arch_runstdby: false
xosc32k_arch_startup: 122us
xosc32k_arch_swben: false
xosc32k_arch_xtalen: true
optional_signals: []
variant: null
clocks:
domain_group: null
OSCCTRL:
user_label: OSCCTRL
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
functionality: System
api: HAL:HPL:OSCCTRL
configuration:
enable_fdpll96m: false
enable_osc48m: true
enable_xosc: false
fdpll96m_arch_enable: false
fdpll96m_arch_filter: Default filter mode
fdpll96m_arch_lbypass: false
fdpll96m_arch_lpen: false
fdpll96m_arch_ltime: No time-out, automatic lock
fdpll96m_arch_ondemand: true
fdpll96m_arch_runstdby: false
fdpll96m_arch_wuf: false
fdpll96m_clock_div: 0
fdpll96m_ldr: 1463
fdpll96m_ldrfrac: 13
fdpll96m_presc: '1'
fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
osc48m_arch_enable: true
osc48m_arch_ondemand: true
osc48m_arch_runstdby: false
osc48m_arch_startup: 21.333us
osc48m_div: 11
xosc_arch_ampgc: false
xosc_arch_cfden: false
xosc_arch_cfdeo: false
xosc_arch_enable: false
xosc_arch_gain: 2MHz
xosc_arch_ondemand: true
xosc_arch_runstdby: false
xosc_arch_startup: 31us
xosc_arch_swben: false
xosc_arch_xtalen: false
xosc_frequency: 400000
optional_signals: []
variant: null
clocks:
domain_group: null
PORT:
user_label: PORT
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT
functionality: System
api: HAL:HPL:PORT
configuration:
enable_port_input_event_0: false
enable_port_input_event_1: false
enable_port_input_event_2: false
enable_port_input_event_3: false
porta_event_action_0: Output register of pin will be set to level of event
porta_event_action_1: Output register of pin will be set to level of event
porta_event_action_2: Output register of pin will be set to level of event
porta_event_action_3: Output register of pin will be set to level of event
porta_event_pin_identifier_0: 0
porta_event_pin_identifier_1: 0
porta_event_pin_identifier_2: 0
porta_event_pin_identifier_3: 0
porta_input_event_enable_0: false
porta_input_event_enable_1: false
porta_input_event_enable_2: false
porta_input_event_enable_3: false
optional_signals: []
variant: null
clocks:
domain_group: null
TIMER_0:
user_label: TIMER_0
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::RTC::driver_config_definition::Timer::HAL:Driver:Timer
functionality: Timer
api: HAL:Driver:Timer
configuration:
rtc_arch_comp_val: 32
rtc_arch_init_reset: true
rtc_arch_prescaler: OFF(Peripheral clock divided by 1)
rtc_cmpeo0: false
rtc_event_control: false
rtc_ovfeo: false
rtc_pereo0: false
rtc_pereo1: false
rtc_pereo2: false
rtc_pereo3: false
rtc_pereo4: false
rtc_pereo5: false
rtc_pereo6: false
rtc_pereo7: false
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: RTC
input: RTC source
external: false
external_frequency: 0
configuration:
rtc_clk_selection: RTC source
USART_0:
user_label: USART_0
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::SERCOM0::driver_config_definition::UART::HAL:Driver:USART.Sync
functionality: USART
api: HAL:Driver:USART_Sync
configuration:
usart_advanced: false
usart_arch_clock_mode: USART with internal clock
usart_arch_cloden: false
usart_arch_dbgstop: Keep running
usart_arch_dord: LSB is transmitted first
usart_arch_enc: No encoding
usart_arch_fractional: 0
usart_arch_ibon: false
usart_arch_lin_slave_enable: Disable
usart_arch_runstdby: false
usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
usart_arch_sampr: 16x arithmetic
usart_arch_sfde: false
usart_baud_rate: 115200
usart_character_size: 8 bits
usart_parity: No parity
usart_rx_enable: true
usart_stop_bit: One stop bit
usart_tx_enable: true
optional_signals: []
variant:
specification: TXPO=1, RXPO=1, CMODE=0
required_signals:
- name: SERCOM0/PAD/1
pad: PA09
label: RX
- name: SERCOM0/PAD/2
pad: PA10
label: TX
clocks:
domain_group:
nodes:
- name: Core
input: Generic clock generator 0
external: false
external_frequency: 0
- name: Slow
input: Generic clock generator 3
external: false
external_frequency: 0
configuration:
core_gclk_selection: Generic clock generator 0
slow_gclk_selection: Generic clock generator 3
DELAY_0:
user_label: DELAY_0
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::SysTick::driver_config_definition::Delay::HAL:Driver:Delay
functionality: Delay
api: HAL:Driver:Delay
configuration:
systick_arch_tickint: false
optional_signals: []
variant: null
clocks:
domain_group: null
PWM_0:
user_label: PWM_0
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::TC4::driver_config_definition::PWM::HAL:Driver:PWM
functionality: PWM
api: HAL:Driver:PWM
configuration:
tc_arch_alock: The Lock Update bit is not affected on overflow/underflow and
re-trigger event
tc_arch_dbgrun: false
tc_arch_evact: Event action disabled
tc_arch_mceo0: false
tc_arch_mceo1: false
tc_arch_ondemand: false
tc_arch_ovfeo: false
tc_arch_presync: Reload or reset counter on next GCLK
tc_arch_runstdby: false
tc_arch_tcei: false
tc_arch_tcinv: false
tc_arch_wave_duty_val: 500
tc_arch_wave_per_val: 1000
tc_mode: Counter in 16-bit mode
tc_prescaler: No division
timer_event_control: false
optional_signals:
- identifier: PWM_0:WO/1
pad: PA15
mode: PWM output
configuration: null
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::optional_signal_definition::TC4.WO.1
name: TC4/WO/1
label: WO/1
variant: null
clocks:
domain_group:
nodes:
- name: TC
input: Generic clock generator 0
external: false
external_frequency: 0
configuration:
tc_gclk_selection: Generic clock generator 0
TEMPERATURE_SENSOR_0:
user_label: TEMPERATURE_SENSOR_0
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::TSENS::driver_config_definition::TSENS::HAL:Driver:Temperature.Sync
functionality: Temperature_Sensor
api: HAL:Driver:Temperature_Sync
configuration:
tsens_advanced_settings: false
tsens_calibration_settings: false
tsens_event_settings: false
tsens_frequency_calibration: 0
tsens_gain_calibration: 960
tsens_offset_calibration: 0
tsens_runstdby: false
tsens_startei: false
tsens_startinv: false
tsens_temperature_calibration: 0
tsens_wineo: false
tsens_winmode: temperature out of the low and high threshold range
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: TSENS
input: Generic clock generator 0
external: false
external_frequency: 0
configuration:
tsens_gclk_selection: Generic clock generator 0
pads:
ANALOG_IN:
name: PA02
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::pad::PA02
mode: Analog
user_label: ANALOG_IN
configuration: null
ADC_POS:
name: PA03
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::pad::PA03
mode: Analog
user_label: ADC_POS
configuration: null
ADC_NEG:
name: PA05
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::pad::PA05
mode: Analog
user_label: ADC_NEG
configuration: null
UART_RX:
name: PA09
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::pad::PA09
mode: Peripheral IO
user_label: UART_RX
configuration: null
UART_TX:
name: PA10
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::pad::PA10
mode: Peripheral IO
user_label: UART_TX
configuration: null
LED:
name: PA15
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21E18A-AN::pad::PA15
mode: Peripheral IO
user_label: LED
configuration: null
toolchain_options: []