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Merge pull request #924 from fastmachinelearning/vu13p
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Update default FPGA part number from KU115 to VU13P
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jmitrevs authored Nov 15, 2023
2 parents 14f06d5 + 2240b42 commit d9391dd
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4 changes: 2 additions & 2 deletions docs/api/configuration.rst
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Expand Up @@ -70,7 +70,7 @@ It looks like this:
OutputPredictions: keras/KERAS_3layer_predictions.dat
# Backend section (Vivado backend)
Part: xcku115-flvb2104-2-i
Part: xcvu13p-flga2577-2-e
ClockPeriod: 5
IOType: io_parallel # options: io_parallel/io_stream
Expand All @@ -97,7 +97,7 @@ There are a number of configuration options that you have. Let's go through the
The backend-specific section of the configuration depends on the backend. You can get a starting point for the necessary settings using, for example `hls4ml.templates.get_backend('Vivado').create_initial_config()`.
For Vivado backend the options are:

* **Part**\ : the particular FPGA part number that you are considering, here it's a Xilinx Virtex-7 FPGA
* **Part**\ : the particular FPGA part number that you are considering, here it's a Xilinx Virtex UltraScale+ VU13P FPGA
* **ClockPeriod**\ : the clock period, in ns, at which your algorithm runs
Then you have some optimization parameters for how your algorithm runs:
* **IOType**\ : your options are ``io_parallel`` or ``io_stream`` which defines the type of data structure used for inputs, intermediate activations between layers, and outputs. For ``io_parallel``, arrays are used that, in principle, can be fully unrolled and are typically implemented in RAMs. For ``io_stream``, HLS streams are used, which are a more efficient/scalable mechanism to represent data that are produced and consumed in a sequential manner. Typically, HLS streams are implemented with FIFOs instead of RAMs. For more information see `here <https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-stream>`__.
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4 changes: 2 additions & 2 deletions hls4ml/backends/vivado/vivado_backend.py
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Expand Up @@ -175,10 +175,10 @@ def get_default_flow(self):
def get_writer_flow(self):
return self._writer_flow

def create_initial_config(self, part='xcku115-flvb2104-2-i', clock_period=5, io_type='io_parallel'):
def create_initial_config(self, part='xcvu13p-flga2577-2-e', clock_period=5, io_type='io_parallel'):
config = {}

config['Part'] = part if part is not None else 'xcku115-flvb2104-2-i'
config['Part'] = part if part is not None else 'xcvu13p-flga2577-2-e'
config['ClockPeriod'] = clock_period
config['IOType'] = io_type
config['HLSConfig'] = {}
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2 changes: 1 addition & 1 deletion hls4ml/converters/__init__.py
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Expand Up @@ -74,7 +74,7 @@ def parse_yaml_config(config_file):
KerasH5: my_keras_model.h5
OutputDir: my-hls-test
ProjectName: myproject
Part: xcku115-flvb2104-2-i
Part: xcvu13p-flga2577-2-e
ClockPeriod: 5
IOType: io_stream
HLSConfig:
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2 changes: 1 addition & 1 deletion scripts/hls4ml
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Expand Up @@ -40,7 +40,7 @@ def main():
)
config_parser.add_argument('-p', '--project', help='Project name', default='myproject')
config_parser.add_argument('-d', '--dir', help='Project output directory', default='my-hls-test')
config_parser.add_argument('-f', '--fpga', help='FPGA part', default='xcku115-flvb2104-2-i')
config_parser.add_argument('-f', '--fpga', help='FPGA part', default='xcvu13p-flga2577-2-e')
config_parser.add_argument('-bo', '--board', help='Board used.', default='pynq-z2')
config_parser.add_argument(
'-ba', '--backend', help='Backend to use (Vivado, VivadoAccelerator, Quartus)', default='Vivado'
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