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Development #12
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Fix Vertical flip bit not working on HW and adding feature -ve y_offset
* fast_divide: Optimize performance Benchamrking shows that average latency per division is reduced from 13 clock cycles to 8 clock cycles. * fast_divide: Bugfix. This may be a bug in Vivado. At least, the previous version worked fine with the GHDL simulator. I'm guessing Vivado has a problem with the "variable length" assignment. The fix introduced here ensures that all 32 bits are assigned always. --------- Co-authored-by: Michael Finn Jørgensen <[email protected]>
* Changed the multiplication routine in audio_mixer.vhdl to not discard the top bit, changed mixer behaviour to peak at instead of overflowing (resolves #793) * Made overflow code respect sign from before overflow, should allow repeated positive and negative overflows to still make sound * Implemented overflow check on the SID mixer as well, fixes a clicking in the output on overflow * Fixed multiplication in audio_mixer.vhdl to allow for full signed 16 bit range * Removed an accidental tab that I somehow didn't notice * Switched SID mixing in audio_complex.vhdl to 18 bit instead of 16 bit * Implemented fix mentioned in #631 * potential sid voice thingy fix, idk
This reverts commit b14fa7c.
also get rid of some compilerr warnings for attic compiles
also add some useful info below the MAC entry field
this frees abot 700 bytes of code space.
… the current (chain of) DMA job(s) #826
…und-at-mb-boundaries 826 dma srcdst addresses wrap around at mb boundaries
Sustain is a level rather than a duration. This commit will change the naming of the register as well as the description.
Integrate HDMI audio bugfix from the Tyto 2 project.
Condensed changes: * feat(sdcardio.vhdl): limit HWERRATA to max supported level #829 also changes documentation to be more verbose and adds searchable terms for finding places where it is used. * docs(sdcardio.vhdl): change HWERRATA Table to also have HWERRATA:LEVEL tags #829 * fix(sdcardio.vhdl): remove unneeded hw_errata_level_int #829 also move signal intialisation to machine.vhdl instead of port list * doc(viciv.vhdl): mark NOBUGCOMPAT as deprecated #829
docs(Changelog.md): add 736 to Changelog
Fixing and adding missing documentation about the RTC
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