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get rid of some empty lines in the generated asm
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irmen committed Jan 5, 2025
1 parent 3b5cda8 commit f0e8ff0
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Showing 8 changed files with 60 additions and 157 deletions.
2 changes: 1 addition & 1 deletion codeCore/src/prog8/code/core/Enumerations.kt
Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@ class DataType private constructor(val base: BaseDataType, val sub: BaseDataType
if(actualElementDt.isNumericOrBool && actualElementDt != BaseDataType.LONG)
DataType(BaseDataType.ARRAY, actualElementDt)
else
throw NoSuchElementException("invalid element dt "+elementDt)
throw NoSuchElementException("invalid element dt $elementDt")
}
}
}
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9 changes: 3 additions & 6 deletions codeGenCpu6502/src/prog8/codegen/cpu6502/AsmGen.kt
Original file line number Diff line number Diff line change
Expand Up @@ -961,8 +961,7 @@ $repeatLabel""")
bne +
cpy #>${value.toHex()}
beq $choiceLabel
+
""")
+""")
}
}
}
Expand Down Expand Up @@ -1109,8 +1108,7 @@ $repeatLabel""")
cmp #$80
bcc +
dey
+
""")
+""")
else -> throw AssemblyError("need byte type")
}
}
Expand All @@ -1124,8 +1122,7 @@ $repeatLabel""")
cmp #$80
bcc +
dex
+
""")
+""")
else -> throw AssemblyError("need byte type")
}
}
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Original file line number Diff line number Diff line change
Expand Up @@ -1491,17 +1491,15 @@ internal class AssignmentAsmGen(
assignExpressionToRegister(left, RegisterOrPair.AY, dt.isSigned)
val castedSymname = asmgen.asmVariableName(castedValue)
if (expr.operator == "+")
asmgen.out(
"""
asmgen.out("""
clc
adc $castedSymname
bcc +
iny
+"""
)
else
asmgen.out(
"""
asmgen.out("""
sec
sbc $castedSymname
bcs +
Expand Down Expand Up @@ -2677,8 +2675,7 @@ $endLabel""")
lda #<$sourceName
ldy #>$sourceName
sta ${target.asmVarname}
sty ${target.asmVarname}+1
""")
sty ${target.asmVarname}+1""")
}
target.datatype.isString || target.datatype.isUnsignedByteArray || target.datatype.isByteArray -> {
asmgen.out("""
Expand Down Expand Up @@ -2798,13 +2795,11 @@ $endLabel""")
RegisterOrPair.AY -> asmgen.out(" ldy $sourceName+1 | lda $sourceName")
RegisterOrPair.XY -> asmgen.out(" ldy $sourceName+1 | ldx $sourceName")
in Cx16VirtualRegisters -> {
asmgen.out(
"""
asmgen.out("""
lda $sourceName
sta cx16.${target.register.toString().lowercase()}
lda $sourceName+1
sta cx16.${target.register.toString().lowercase()}+1
""")
sta cx16.${target.register.toString().lowercase()}+1""")
}
else -> throw AssemblyError("can't load word in a single 8-bit register")
}
Expand All @@ -2825,8 +2820,7 @@ $endLabel""")
asmgen.out("""
ldx #<${target.asmVarname}
ldy #>${target.asmVarname}
jsr floats.MOVMF
""")
jsr floats.MOVMF""")
}
TargetStorageKind.ARRAY -> {
asmgen.assignExpressionToRegister(target.array!!.index, RegisterOrPair.A, false)
Expand Down Expand Up @@ -2924,8 +2918,7 @@ $endLabel""")
TargetStorageKind.VARIABLE -> {
asmgen.out("""
lda $sourceName
sta ${target.asmVarname}
""")
sta ${target.asmVarname}""")
}
TargetStorageKind.MEMORY -> {
asmgen.out(" lda $sourceName")
Expand All @@ -2951,13 +2944,11 @@ $endLabel""")
RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldx $sourceName")
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
in Cx16VirtualRegisters -> {
asmgen.out(
"""
asmgen.out("""
lda $sourceName
sta cx16.${target.register.toString().lowercase()}
lda #0
sta cx16.${target.register.toString().lowercase()}+1
""")
sta cx16.${target.register.toString().lowercase()}+1""")
}
else -> throw AssemblyError("weird register")
}
Expand All @@ -2975,8 +2966,7 @@ $endLabel""")
ora #$7f
bmi +
lda #0
+ sta ${wordtarget.asmVarname}+1
""")
+ sta ${wordtarget.asmVarname}+1""")
}
TargetStorageKind.ARRAY -> {
if(wordtarget.array!!.splitWords) {
Expand Down Expand Up @@ -3759,17 +3749,15 @@ $endLabel""")
stz ${target.asmVarname}+1
stz ${target.asmVarname}+2
stz ${target.asmVarname}+3
stz ${target.asmVarname}+4
""")
stz ${target.asmVarname}+4""")
else
asmgen.out("""
lda #0
sta ${target.asmVarname}
sta ${target.asmVarname}+1
sta ${target.asmVarname}+2
sta ${target.asmVarname}+3
sta ${target.asmVarname}+4
""")
sta ${target.asmVarname}+4""")
}
TargetStorageKind.ARRAY -> {
asmgen.assignExpressionToRegister(target.array!!.index, RegisterOrPair.A, false)
Expand Down Expand Up @@ -3815,8 +3803,7 @@ $endLabel""")
sty P8ZP_SCRATCH_W2
ldy #>${target.asmVarname}
sty P8ZP_SCRATCH_W2+1
jsr floats.set_array_float
""")
jsr floats.set_array_float""")
}
TargetStorageKind.MEMORY -> throw AssemblyError("can't assign float to memory byte")
TargetStorageKind.REGISTER -> {
Expand All @@ -3837,8 +3824,7 @@ $endLabel""")
TargetStorageKind.VARIABLE -> {
asmgen.out("""
lda ${address.toHex()}
sta ${target.asmVarname}
""")
sta ${target.asmVarname}""")
}
TargetStorageKind.MEMORY -> {
asmgen.out(" lda ${address.toHex()}")
Expand All @@ -3857,13 +3843,11 @@ $endLabel""")
RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldy ${address.toHex()}")
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
in Cx16VirtualRegisters -> {
asmgen.out(
"""
asmgen.out("""
lda ${address.toHex()}
sta cx16.${target.register.toString().lowercase()}
lda #0
sta cx16.${target.register.toString().lowercase()}+1
""")
sta cx16.${target.register.toString().lowercase()}+1""")
}
else -> throw AssemblyError("weird register")
}
Expand Down Expand Up @@ -3893,12 +3877,10 @@ $endLabel""")
RegisterOrPair.XY -> asmgen.out(" tax | ldy #0")
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
in Cx16VirtualRegisters -> {
asmgen.out(
"""
asmgen.out("""
sta cx16.${target.register.toString().lowercase()}
lda #0
sta cx16.${target.register.toString().lowercase()}+1
""")
sta cx16.${target.register.toString().lowercase()}+1""")
}
else -> throw AssemblyError("weird register")
}
Expand Down Expand Up @@ -4232,8 +4214,7 @@ $endLabel""")
asmgen.out("""
lda ${target.asmVarname}+1
eor #$80
sta ${target.asmVarname}+1
""")
sta ${target.asmVarname}+1""")
}
TargetStorageKind.ARRAY -> assignPrefixedExpressionToArrayElt(makePrefixedExprFromArrayExprAssign("-", assign), scope)
else -> throw AssemblyError("weird target for in-place float negation")
Expand Down
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