RISC-V-Processor

A single cycle processor implemented in Verilog. Final Project for ENG EC413 - Computer Organization (Fall 2019).

Note: All files in the .src folder should be added as sources to your Vivado project (including the .vmh files, if you intend to use them)

Name		Name	Last commit message	Last commit date
Latest commit History 56 Commits
RISCV_Single_Cycle_Processor		RISCV_Single_Cycle_Processor
ALU.v		ALU.v
ALU_tb.v		ALU_tb.v
README.md		README.md
decode.v		decode.v
decode_tb.v		decode_tb.v
fetch.v		fetch.v
fetch_tb.v		fetch_tb.v
fibonacci.dump		fibonacci.dump
fibonacci.vmh		fibonacci.vmh
gcd.dump		gcd.dump
gcd.vmh		gcd.vmh
ram.v		ram.v
ram_tb.v		ram_tb.v
regFile.v		regFile.v
regFile_tb.v		regFile_tb.v
top.v		top.v
top_tb.v		top_tb.v

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